13 results about "S-box" patented technology

The invention discloses a dynamic S-box and cross-channel diffusion image encryption method based on six-dimensional hyper-chaos driving, and belongs to the field of information security, and the method comprises the implementation steps: 1) constructing a novel six-dimensional hyper-chaos system; 2) constructing a cross-channel diffusion scheme based on the six-dimensional hyperchaotic system; 3) constructing a dynamic S box library based on a six-dimensional hyperchaotic system; according to the invention, by introducing an inter-channel coupling mechanism, the potential safety hazard of traditional sub-channel encryption is effectively relieved. A dynamic S box generated based on chaotic system state self-adaption enhances the nonlinear confusion characteristic, and Arnodcat mapping transformation realizes global pixel scrambling. Theoretical and experimental results show that the method overcomes the limitation of a low-dimensional system, and the aspects of statistical analysis, key sensitivity, attack resistance and the like are remarkably improved.

The invention relates to a power secondary equipment fingerprint construction method and system, an electronic device and a storage medium, belongs to the field of network security, and solves the problems that the power secondary equipment is inaccurate in identity recognition, large in resource consumption and easy to be interfered by the environment. Comprising the following steps: periodically acquiring multi-dimensional features of the power secondary equipment according to an acquisition period and preprocessing the multi-dimensional features; based on the stability index value of each feature, dynamically allocating a weight for each feature, and performing tolerance mapping on the preprocessed features based on the weights to generate a robust feature character string; generating a dynamic S box exclusive to the power secondary equipment based on the plurality of high-stability characteristics of the power secondary equipment; and utilizing the exclusive dynamic S box to encrypt the robust feature character string through a lightweight encryption algorithm, carrying out Hash operation on an encryption result, and dynamically generating a fixed-length equipment fingerprint of the current acquisition period. And safe, efficient and stable identity authentication of the power secondary equipment is realized.

The application discloses a kind of security detection method and device of cryptographic algorithm, the method includes: setting target plaintext data, and the target plaintext is processed by predefined cryptographic algorithm, and target ciphertext is obtained;The inverse operation of CBC chain operation is carried out to the target ciphertext, and intermediate ciphertext is obtained;The target plaintext data and the intermediate ciphertext are compared, and S box is cracked;According to the S box, inverse S box is constructed;According to the intermediate ciphertext and the inverse S box, solution is obtained, and decryption result is obtained;The decryption result and the target plaintext data are compared, and comparison result is obtained.The device includes memory and processor for executing the security detection method of the above cryptographic algorithm.The application provides a new direction for the security performance detection of encryption method.The application can be widely applied in the field of security detection.

The invention discloses an 8-bit S box construction method based on greedy random adaptive search, which comprises the following steps of: firstly, introducing a nonlinear term power function, a trigonometric function and a logarithmic function to construct a two-dimensional hyper-chaotic system TDHM on the basis of a benchmark test function Himelblau function; secondly, constructing a bijection initial S box based on a random number sequence generated by a two-dimensional hyper-chaotic system TDHM; and finally, respectively carrying out linearity and differential uniformity optimization on the S boxes of which the cryptographic properties do not meet the requirements, setting corresponding cost function values as optimization constraint conditions, selecting an optimized exchange strategy according to corresponding greedy rules, carrying out local search on the S boxes to optimize the linearity and differential uniformity of the S boxes, and carrying out optimization on the S boxes. And the password S box meeting the target condition is constructed. According to the method, the success rate of searching the S box meeting the target requirement is improved, and the average iteration frequency of the algorithm is effectively reduced.

The invention provides a self-anti-S box construction method and system based on m-sequence generation and logic optimization, and belongs to the technical field of cryptography and hardware security. The method comprises the following steps: firstly, constructing an n-level linear feedback shift register according to a set S box number n and a primitive polynomial, generating an m sequence in a non-all-zero initial state, and adding an all-zero state at the tail; a self-reverse S box lookup table is constructed through a symmetric mapping strategy, so that the ith element in the sequence and the element at the symmetric position form mapping, and the same S box is used for encryption and decryption. Thirdly, the lookup table serves as a Boolean function truth table, is simplified into a simplest expression through a logic minimization algorithm and is decomposed into a layered logic circuit; during actual processing, N data blocks are converted into a bit plane format from block type storage, then parallel operation is carried out through a hierarchical circuit, and finally a result is transposed back to block type storage. According to the method, the same S box hardware module can be reused in the encryption and decryption process, and hardware resources are remarkably saved.

The invention provides a data processing method and device based on a logic gate, and relates to the technical field of communication. The method comprises the following steps: acquiring input data, wherein the input data belongs to a finite field; the input data is processed through an S box, the S box is used for a symmetric encryption algorithm, the S box comprises a plurality of logic gates, and the plurality of logic gates comprise three input logic gates. According to the method in the embodiment of the invention, the calculation efficiency of the symmetric encryption algorithm can be improved.

The application relates to a power secondary equipment fingerprint construction method and system, an electronic device and a storage medium, and belongs to the network security field, and solves the problems of inaccurate power secondary equipment identity recognition, large resource consumption and easy environmental interference. The method comprises the following steps: periodically collecting multi-dimensional characteristics of power secondary equipment according to a collection period and preprocessing; based on stability index values of the characteristics, dynamically assigning weights to the characteristics, and based on the weights, performing tolerance mapping on the preprocessed characteristics to generate a robust feature string; based on a plurality of high-stability characteristics of the power secondary equipment, generating a dynamic S box special for the power secondary equipment; and using the special dynamic S box to encrypt the robust feature string through a lightweight encryption algorithm, and performing a hash operation on the encryption result to dynamically generate a fixed-length device fingerprint of the current collection period. The identity authentication of the power secondary equipment is safe, efficient and stable.

The invention discloses a security detection method and device for a cryptographic algorithm, and the method comprises the steps: setting target plaintext data, and carrying out the processing of a target plaintext through a predefined cryptographic algorithm, and obtaining a target ciphertext; performing inverse operation of CBC chain operation on the target ciphertext to obtain an intermediate ciphertext; comparing the target plaintext data with the intermediate ciphertext, and cracking to obtain an S box; constructing an inverse S box according to the S box; solving according to the intermediate ciphertext and the inverse S box to obtain a decryption result; and comparing the decryption result with the target plaintext data to obtain a comparison result. The device comprises a memory and a processor used for executing the security detection method of the cryptographic algorithm. The invention provides a new direction aiming at the security performance detection of the encryption method. The method can be widely applied to the field of security detection.

The invention provides an encryption / decryption method and device. The method comprises the steps that multiple rounds of operation are carried out based on input data and a secret key to generate output data, each round of operation is used for processing N pieces of grouped data to generate rounds of output data, and the N pieces of grouped data of the first round of operation are obtained after random mask processing is carried out on the input data, the N grouped data of the other rounds of operation are obtained according to the N-1 grouped data of the previous round of operation and the round output data. In each round of operation, performing random mask processing according to the round key and N-1 grouped data of the round of operation to generate first data; performing nonlinear transformation on the first data by using the S box with the mask to generate second data; performing linear transformation on the second data to generate third data; performing XOR operation on the other packet data of the current round of operation and the third data to generate fourth data; and performing mask processing on the fourth data to generate round output data of the round of operation. According to the method, the security of equipment and data can be improved.

The invention discloses a minimum time delay S-box circuit searching method based on an STP solver, and the method comprises the steps: constructing a constraint model comprising circuit topology, logic functions and process library weighted time delay, and employing an automatic tool STP solver to achieve the searching of a minimum time delay S-box circuit under the given logic gate number and depth limitation. And the S-box circuit which meets the specific cryptographic property and has the minimum physical time delay is automatically searched. According to the method, the security of the S box for resisting the password attack is considered, the physical delay of the critical path can be accurately constrained and optimized, and meanwhile, the low delay characteristic of the composite logic gate can be utilized to explore and determine the delay performance boundary of the S box under a specific process.

The application discloses a differential fault attack method of a lightweight cipher GIFT based on a byte model, and comprises the following steps: obtaining correct cipher texts generated by using the GIFT algorithm to encrypt plaintexts without injecting byte faults and error cipher texts generated by encrypting the plaintexts after injecting byte faults, wherein the GIFT algorithm is encrypted through a plurality of S boxes; performing an exclusive or operation on the correct cipher texts and the error cipher texts to obtain output differentials of each corresponding S box in the encryption process of target plaintexts, and determining a target S box injected with a byte fault in the plurality of S boxes according to the output differentials of each S box and input differentials of each S box obtained in advance; determining an input value of the target S box in the encryption process of plaintexts without injecting byte faults as a correct input value of the target S box according to the input differentials and the output differentials of the target S box; and recovering an encryption key used by the plaintexts without injecting byte faults and the plaintexts with injecting byte faults through the correct input value of the target S box.

The invention discloses a fast implementation method for an FBC block cipher algorithm based on an x86 processor. The method comprises the following steps of: performing slice recombination and parallel arrangement on plaintext data to be encrypted; carrying out bit-level expansion on the secret key, and carrying out bitwise exclusive-or operation on the multi-path slice data which are arranged in parallel and the expanded round secret key; performing secondary slicing on the data subjected to round key operation according to bytes, and inputting the data into an S box which is converted into a Boolean algebra expression for parallel operation; performing parallel optimization on linear operations such as row shift and column confusion by using an AVX2 instruction set; and finally, performing inverse arrangement on the bit slicing result, outputting ciphertext groups, and completing data encryption. According to the method, on the premise of not changing an FBC block cipher algorithm structure and security characteristics, the parallel computing capability of the instruction set is fully utilized, high-speed parallel encryption of the FBC block cipher is realized, and the encryption efficiency and throughput performance of software implementation are effectively improved.

The application discloses a kind of SM4 fast software implementation methods based on AES- NI instruction set, this method includes: based on AVX2 (Advanced Vector Extensions) instruction set and AES- NI (Advanced Encryption Standard New Instructions) instruction set, SM4 algorithm is optimized, realizes 8 groups of plaintext parallel encryption, by finding the isomorphism between finite field, S box in SM4 algorithm is mapped to the S box of AES algorithm, and the S box operation of SM4 algorithm is completed using AES- NI extension instruction;In algorithm implementation, the shuffle instruction in AVX2 instruction set is used to improve the matrix operation efficiency in round function.