147 results about "Data contention" patented technology

A system and method for ensuring consistency of data and preventing data races, including steps of: receiving and examining a computer program written in an object-oriented language; receiving sequences of accesses that form logical operations on a set of memory locations used by the program; receiving definitions of atomic sets of data from the memory locations, wherein said atomic sets are sets of data that indicate an existence of a consistency property without requiring the consistency property itself; inferring which code blocks of the computer program must be synchronized in order to prevent one or more data races in the computer program, wherein synchronization is inferred by determining by analysis for each unit of work, what atomic sets are read and written by the unit of work; and providing a message indicating where synchronization is required.

An embodiment of a ultra low-power data retention latch circuit involves a slave latch SL that concurrently latches the same data that is loaded into a main circuit (such as a main latch ML) during normal operation. When the circuit enters a low power (data retention) mode, power (VCC) to the main latch ML is removed and the slave latch SL retains the most recent data (retained data SA, SA-). When power is being restored to the main latch ML, the slave latch's retained data SA, SA- is quickly restored to the main latch ML through what constitute Set and Reset inputs SAR, SAR- of the ML. This arrangement ensures that data restoration is much quicker than conventional arrangements that require the output data path DATA- to be stabilized before power is re-applied to the main latch. Further, there is no need to wait for power to the ML to be stable before restoring data from the SL to the ML, providing an increase in data restoration speed over conventional data retention latches. Using retained data SA, SA- (as mirrored in SAR, SAR-) to control the Set and Reset inputs prevents data contention in the main latch ML. Moreover, compared to known arrangements, the arrangement provides minimal loading on the DATA, DATA- output paths (driving only N7, N8), thus not compromising speed on the data path (DATAIN . . . DATA / DATA-) through the main latch during normal operation.

Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface.

A system and method for analyzing a concurrent program employ asynchronous function calls for communication and recursion. A control flow graph is constructed based on a context-sensitive pointer analysis, whereupon encountering a function pointer, a points-to set of the function pointer is computed in a context-sensitive fashion to determine a set of potential function calls. The context-sensitive pointer analysis is terminated when no new potential function calls are encountered and where the potential function calls may contribute new data races other than those that exist in the contexts traversed thus far. To decide this, a characterization of pointer aliasing based upon complete update sequences is employed. A set of contexts that may contribute to different data races are enumerated by tracking update sequences for function and lock pointers and pointers that are shared or point to shared memory locations. Data race detection is carried out on the control flow graph.

An encryption device eliminates data contention and minimizes area by accessing twice data for a given time by using a memory device of two times faster access time. The encryption device for performing encryption of plain text blocks using data encryption standard algorithm, wherein the encryption device includes an initial permutation unit, a data encryption unit having n-stage (n is an even number) pipeline structure using a first clock, a second clock and a third clock, and an inverse initial permutation unit, the encryption device includes: a multiplexer for selecting one of n / 3 48-bit inputs; 8 S-Boxes, each for receiving 6-bit address among the selected 48-bit and outputting 4-bit data; a demultiplexer for distributing 32-bit data from the S-Boxes to n / 3 outputs; and a controller for control the multiplexer and the demultiplexer with a fourth clock and a fifth clock, wherein the fourth and the fifth clock are faster than the first, the second and the third clocks by n / 3 times.

A technique for low overhead contention-based switching between ticket locking and queued locking to access shared data may include establishing a ticket lock, establishing a queue lock, operating in ticket lock mode using the ticket lock to access the shared data during periods of relatively low data contention, and operating in queue lock mode using the queue lock to access the shared data during periods of relatively high data contention.

Disclosed herein are systems and networks comprising a network operations server application for improving a packet-switched communications network, the application configured to: receive data from data source nodes; provide a management console allowing a user to configure a network multi-access protocol for: i) a node, ii) a type of node, iii) a group of nodes, iv) a type of data packet from a node, v) a type of data packet from a type of node, vi) a type of data packet from a group of nodes, or vii) a specific instance of a data packet from a node, the network multi-access protocol a scheduled or random access protocol; and dynamically create channel assignments to allocate bandwidth of the network among channels based on the configured network multi-access protocols to prevent network saturation and minimize data collisions in the packet-switched network.

The disclosed system and methods involve controlling the timing and order in which numerous motors and sensors exchange data over a data bus. The method can be used with, for example, motion control, automotive, industrial automation, and medical equipment applications using data buses. As an example of one possible medical equipment application, the method of exchanging data on a bus can be used with a remote catheter guidance system. The disclosed system and methods help optimize data exchange over a bus and avoid collisions by grouping the transmission of sensor readings, by grouping the transmission of motor commands, and by predetermining the order of these groups. Further, the method provides a way of ensuring that incomplete data sets are not exchanged over the bus. The method also provides a way of synchronizing motor actuation based on data transmitted to the data bus.

Static data race analysis of at least a portion of a multi-threaded application in order to identify potential data race defects in the multi-threaded application. The static data race analysis includes intra-component static analysis as well as inter-component static analysis. The intra-component static analysis for a given component involves identifying a set of memory accesses operations in the component. For each of at least one of the set of memory access operations, the analysis determines whether there is a data race protection element associated with the memory access command.