21 results about "CORDIC" patented technology

The invention provides a WiFi network digital down-conversion system which comprises a multi-phase mixer and a resampling filter. The multi-phase mixer is used for converting a high-speed digital band-pass signal into a low-speed mode so as to realize digital down-conversion (DDC) on an FPGA (Field Programmable Gate Array) platform; and the resampling filter is used for reducing the sampling rate and removing unwanted frequency spectrum components to generate a complex baseband frequency spectrum. The multi-phase mixer PM of the present invention employs a parallel coordinate rotation digital computer (CORDIC) processor and a low pass filter array to reduce high speed data rates while minimizing resource utilization. The resampling filter comprises a cascade integral combination (CIC) filter and a multi-channel pulse finite impulse response (FIR) filter, optimal hardware cost is achieved, a floating point data type is converted into a fixed point data type, and resources are remarkably saved.

The invention provides a CORDIC-based hardware implementation method, device, equipment and medium, and is applied to a CORDIC-based hardware implementation device, the device comprises an input module, a control module and an operation module, and the method comprises the following steps: the input module inputs a to-be-calculated parameter and loads an initialization parameter; the control module determines configuration parameters and determines that the operation module is in a rotation mode; the configuration parameters are used for determining the number of calculation units executing rotation operation in the operation module; the operation module controls all the calculation units to execute rotation operation on the to-be-calculated parameters based on the initialization parameters in the rotation mode, the vector modulus length in the rotation process is kept unchanged, the rotation angle and the rotation direction are dynamically updated according to the current intermediate result after each rotation operation is finished, and finally the operation result of the to-be-calculated parameters is obtained. Therefore, under the condition of limited hardware resources of the FPGA, higher calculation precision and calculation efficiency are achieved, and meanwhile logic units and storage resources needed by hardware implementation are reduced.

According to the sinusoidal signal generation method and device and the cosine signal generation method and device provided by the invention, based on triangle and angle formula expansion, a sinusoidal signal is generated in a manner of generating an iterative value through preconfiguration of a basic value and pipeline multiplication and addition iteration, and complex logics such as data cache management of a DDS and multi-round iterative calculation of Cordic are avoided. Moreover, the multiply-add operation module of the m-level assembly line splits the logic combination of multiplication and addition operation in multiply-add operation into m clock periods, so that the operation frequency of the FPGA is optimized. The method only depends on common logic operations such as accumulative counting, data selection and basic multiplication and addition, a large number of BRAMs for storing sine wave complete data in a DDS scheme are not needed, large-scale parallel iterative logic needed by a Cordic scheme for guaranteeing precision and throughput rate is also avoided, only a small number of LUT tables and DSP resources are needed in actual implementation, and hardware resource occupation of an FPGA is greatly reduced.

The invention relates to a multi-channel modularized ultrasonic front-end system based on an FPGA (Field Programmable Gate Array), belongs to the field of ultrasonic equipment, and solves the problems of slow delay parameter calculation and low delay precision of the existing system. The system comprises an FPGA main control module, a high-voltage driving circuit, an ultrasonic probe and a receiving and conditioning circuit, wherein the FPGA main control module comprises a transmitting module and a receiving module; the transmitting module generates a control signal based on the delay parameter, triggers the high-voltage driving circuit to generate a high-voltage pulse, and excites the ultrasonic probe to transmit a wave beam; the ultrasonic probe converts the reflected wave beam into an electric signal, sends the electric signal as an echo signal to a receiving conditioning circuit for processing, and transmits the echo signal to a receiving module to form a focusing signal; the receiving module comprises a delay signal calculation module and a focusing signal calculation module, and the delay signal calculation module converts the processed echo signal into a delay signal by adopting a mode of combining coarse delay and fine delay based on a radix-4-CORDIC algorithm; the latter adopts a radix-4-CORDIC algorithm to calculate a focusing signal based on the delay signal. The ultrasonic imaging front-end system is high in speed and precision.

A device includes a Coordinate Rotation Digital Computer (CORDIC), a memory, a first Direct Memory Access (DMA) engine, and a second DMA engine. The memory stores an array of calculation data sets and an array of result data sets corresponding to the calculation data sets. The first DMA engine copies each data set of the array of calculation data sets from the memory to the CORDIC. The second DMA engine copies each result data set of the array of result data sets from the CORDIC to the memory and generates a trigger in response to copying a final result data set of the array of result data sets to the memory.

The application discloses a method and device for realizing CORDIC, and the method comprises the following steps: obtaining a target angle; judging whether the absolute value of the target angle is within a set threshold range; if yes, performing a jump-step CORDIC iteration operation; otherwise, performing a full-step CORDIC iteration operation; the full-step CORDIC iteration operation refers to performing a 0-n step CORDIC iteration operation; the jump-step CORDIC iteration operation refers to skipping a 0-m step CORDIC iteration operation, and performing a m+1-n+m+1 step CORDIC iteration operation, wherein m is 0 or a positive integer. According to the application, the calculation precision of CORDIC can be improved.

The invention discloses a Cordic calculation circuit, a Cordic calculation method and an accelerated calculation system, and relates to the technical field of electronic circuits. The Cordic calculation circuit comprises a logic control module, an X calculation module and a Y calculation module, the logic control module is connected with the X calculation module and the Y calculation module; the logic control module is used for determining a calculation execution signal and a calculation type signal according to the obtained X input value, Y input value and calculation order; the X calculation module is used for acquiring an X input value, performing calculation on the X input value according to the calculation execution signal and outputting an X calculation result; and the Y calculation module is used for acquiring a Y input value, performing calculation on the Y input value according to the calculation execution signal and outputting a Y calculation result.

A device includes a Coordinate Rotation Digital Computer (CORDIC), a memory, a first Direct Memory Access (DMA) engine, and a second DMA engine. The memory stores an array of calculation data sets and an array of result data sets corresponding to the calculation data sets. The first DMA engine copies each data set of the array of calculation data sets from the memory to the CORDIC. The second DMA engine copies each result data set of the array of result data sets from the CORDIC to the memory and generates a trigger in response to copying a final result data set of the array of result data sets to the memory.

The invention relates to a method for simulating Doppler diffusion and multipath time delay of a wireless channel, belongs to the field of wireless communication channel simulation, and is used for simulating Doppler diffusion and multipath time delay of a Rayleigh channel. According to the method, the maximum number of sine waves of a channel simulator is expanded through a time division multiplexing Cordic calculation module, a limited number of sine waves are superposed to generate a channel envelope, the channel sampling rate is improved through a CIC interpolation filter, fractional time delay in a wireless channel is simulated through a Farrow structure filter based on Lagrange interpolation, and the frequency of the wireless channel is improved. Therefore, the multi-path number is flexibly expanded, the resource consumption is reduced, the channel simulation precision and the sampling rate are improved, and the multi-path fractional time delay is flexibly simulated. Compared with an ROM table look-up method, the method has the advantages of being low in resource consumption, high in channel simulation precision, easy to implement and deploy and the like, and is suitable for the fields of wireless communication channel simulators, signal processing and the like.

The invention discloses a CORDIC inverse trigonometric function solving system based on prefix binary tree mapping, and the system comprises a prefix binary tree mapping module which is used for carrying out the multi-stage prefix comparison of an input independent variable x, and directly outputting a unit vector corresponding to the (k + 1) th iteration, so as to replace the first k stages of micro-rotation iterations of a CORDIC algorithm; and the CORDIC iteration module is used for taking the unit vector output by the prefix binary tree mapping module as an initial value, taking an input independent variable x as an initial comparison value, continuing to finish the rest (M-k-1)-level iteration from the (k + 1)-th level, and outputting a final iteration result. According to the CORDIC anti-trigonometric function solving system based on prefix binary tree mapping provided by the invention, on the premise of keeping the calculation precision, the early-stage iteration process of a CORDIC algorithm is effectively replaced, the calculation resource consumption and the operation time delay are remarkably reduced, meanwhile, the precision loss caused by approximate gain compensation is thoroughly avoided, and the calculation efficiency is improved. Therefore, the requirement of a real-time high-performance computing system for high-precision transcendental function operation is met.

The present disclosure provides a crest factor reduction system and method for suppressing peak regrowth. The system receives a complex signal from the physical layer (PHY) of a base station equipped with an orthogonal frequency division multiplexing (OFDM) function. Further, the system uses a coordinate rotation digital computer (CORDIC) to convert the complex signal into polar form. Also, the system utilizes an advanced interpolation processing (AIP) technique to minimize the peak regrowth that may occur at x4 (digital upconversion (DUC)) in the latter half of the downlink chain. Thereby, the initial problem of peak regrowth associated with the DUC process can be suppressed by the proposed CFR design. Further, in the CFR design of the present invention, since multiple multiple-input multiple-output (MIMO) channels can be operated by multiplexing in the time domain, the resource utilization rate can be further reduced.

The application relates to the technical field of digital signal processing and integrated circuit, and provides a pipeline high-precision fixed-point complex modulus circuit and method, wherein after in-depth analysis, reasoning and verification according to the principle of CORDIC algorithm, a new fixed-point complex modulus circuit logic is improved and designed, so that the complex Euclidean norm operation can be replaced by simple addition and subtraction and shift operation, the circuit logic structure is greatly simplified, the hardware resource consumption of the modulus operation is greatly reduced, finally, a high-efficiency low-resource-consumption fixed-point modulus operation is formed, and the circuit supports pipeline operation, so that the calculation speed is ensured.

The present disclosure provides a system and a method for crest factor reduction (CFR) with a restricted peak regrowth. The system receives a complex signal from a physical layer (PHY) of a base station equipped with orthogonal frequency division multiplexing (OFDM). The system uses a coordinate rotation digital computer (CORDIC) to convert the complex signal into a polar form. Further, the system utilizes an advanced interpolation processing (AIP) technique to minimize the peak regrowth that can happen in an x4 (digital up-conversion (DUC) in the later stage of a downlink chain. Hence, a teething problem of peak growth due to DUC process is restricted to a limited regrowth in the proposed CFR design. Further, the CFR design can operate multiple multiple-input multiple-output (MIMO) channels by multiplexing in time domain which further reduces resource utilization.

The invention provides a pipeline structure CORDIC circuit, an implementation method thereof, equipment and a medium. The method comprises the following steps: acquiring an initial value of a rotation angle and a complex number coordinate of an input signal; the quadrant where the complex coordinates are located is judged so that the complex coordinates can be corrected; judging whether the ordinate of the complex coordinates is positive or negative, so as to iterate the rotation angle and update the complex coordinates until a preset number of iterations is reached; correcting the rotation angle according to a quadrant judgment result; and judging whether the rotation angle reaches a threshold value or not so as to correct the rotation angle and obtain a final angle value. The CORDIC circuit adopting a pipeline structure is small in area and high in throughput, complex signals can be input into the CORDIC circuit realized by the method in a pipeline mode, and a continuous conversion result can be obtained after long time delay of the pipeline.

The invention discloses a multi-channel parallel frequency offset estimation method, relates to the field of optical fiber and terahertz communication, and aims at searching a maximum frequency offset value corresponding to a likelihood function by adopting pipeline type multi-channel parallel after comprehensively considering time delay and resources. Besides, the algorithm of the two-stage assembly line is provided to realize range limitation, the limitation can be realized only through judgment, addition and subtraction, and a large number of register resources and DSP resources are not needed; and after range limitation is realized, a complex index is calculated by using a CORDIC IP core, so that frequency offset compensation is realized for symbols before frequency offset correction. According to the range limiting algorithm, DSP resources are not needed, and a large number of register resources needed by a traditional algorithm are reduced.

The invention discloses a DRM channel modulator based on a CORDIC algorithm. The DRM channel modulator comprises an FPGA module used for realizing logical operation and supporting double-clock domain operation; the memory module is used for caching rate mismatch data between the front-stage encoder and the rear-stage modulator; the clock module is provided with double frequencies, the clock module is used for serving high-speed operation and low-speed signal processing, and the clock module realizes synchronization of two paths of clocks through an MMCM; and the high-speed AD / DA module is used for digital pre-distortion closed-loop correction expansion. Parallel processing of 1024 subcarriers is supported through the assembly line CORDIC, and the single symbol delay is far smaller than the minimum symbol period of the DRM. Due to the one-hot code and check bit design, the bit error rate during signal-to-noise ratio is reduced by two orders of magnitude compared with that of a traditional scheme; iFFT (Inverse Fast Fourier Transform) points can be configured, DRM30 and DRM + modes are supported, and an existing transmitter modulation module can be directly replaced.

The invention provides a trigonometric function calculation method, device and equipment and a readable storage medium, and the method comprises the steps: carrying out the splitting of a to-be-solved angle if the to-be-solved angle corresponding to a trigonometric function meets a preset condition, and obtaining a first angle; determining iteration information corresponding to the first angle from an iteration information storage table; based on the iteration information, determining a residual solving angle corresponding to the angle to be solved; and carrying out iterative calculation on the residual solving angles by using a coordinate rotation digital calculation (CORDIC) unit to obtain a solving result corresponding to the angle to be solved. Therefore, by adopting the method of combining the table look-up method and the CORDIC, the effects of reducing the iterative calculation times of the trigonometric function and accelerating angle convergence can be realized, so that the calculation delay is reduced, the hardware resources are reduced, and a high-precision solving result is obtained.

The invention is applicable to the field of digital signal processing, and discloses an FFT (Fast Fourier Transform) calculation method, system, equipment and medium based on CORDIC (Coordinated Rotation Digital Integrated Circuit) of an angle precoding circumference system, the method comprises the following steps: acquiring an input angle to be calculated, and obtaining a vector and a residual angle by inquiring a predefined distribution table; based on residual angle block coding, obtaining a non-scaling twiddle factor corresponding to the coded angle through Taylor expansion, and rotating the vector to obtain a rotated vector and a micro angle; obtaining a trigonometric function value corresponding to the input angle by combining approximate processing with multiply-add operation based on the rotated vector and the micro angle; and according to the received sampling sequence data, applying the trigonometric function value as a twiddle factor, and executing complex multiplication and data exchange in each level of butterfly operation unit of the FFT to obtain FFT spectrum data. The CORDIC algorithm with few iterations, high calculation precision and low hardware resource consumption is realized, and the FFT calculation efficiency and performance are improved.

The application relates to the technical field of digital signal processing, in particular to a non-scaling reconfigurable CORDIC calculation method based on a lookup table and a micro-rotation angle set, which comprises the following steps: input angle and a mode selection signal are acquired; based on the mode selection signal, a first-stage rotation operation is performed on the input angle through the lookup table, the input angle is mapped to a small-angle region, and a first-rotation-vector value and a first residual angle after the first-stage rotation operation are output; a multi-stage iterative micro-rotation operation is performed on the first residual angle by using the micro-rotation angle set, and a final-rotation-vector value is output; wherein the circular rotation and the hyperbolic rotation share the address of the lookup table, the micro-rotation angle set and the rotation operation hardware resources, and the mode switching is performed through the mode selection signal, so that the high reconfigurability of the hardware resources is realized. The method can solve the technical problem that the existing CORDIC architecture is difficult to balance among the convergence range, the hardware resources, the calculation accuracy and the reconfigurability.

The invention provides a circuit based on a CORDIC algorithm and an operation method thereof, and relates to the technical field of hardware implementation of functions. The circuit comprises a control module, an iterative operation module and a post-processing module, the control module is used for generating target configuration information so as to configure a function type included in the iterative operation module, an operation mode corresponding to the function type and the number of iterations, and the iterative operation module is used for generating target configuration information. The iterative calculation module is used for carrying out iterative calculation on the preprocessed intermediate data based on the target configuration information to obtain target data, and the post-processing module is used for carrying out post-processing on the target data obtained after iteration is completed and outputting a processed result. According to the invention, the calculation of the trigonometric function, the linear function and the hyperbolic function is realized through iterative approximation, and the calculation is realized by configuring the corresponding number of iterations according to the precision required by the use demand, so that the use efficiency of the CORDIC algorithm circuit is improved.