8 results about "CORDIC" patented technology

The invention provides a WiFi network digital down-conversion system which comprises a multi-phase mixer and a resampling filter. The multi-phase mixer is used for converting a high-speed digital band-pass signal into a low-speed mode so as to realize digital down-conversion (DDC) on an FPGA (Field Programmable Gate Array) platform; and the resampling filter is used for reducing the sampling rate and removing unwanted frequency spectrum components to generate a complex baseband frequency spectrum. The multi-phase mixer PM of the present invention employs a parallel coordinate rotation digital computer (CORDIC) processor and a low pass filter array to reduce high speed data rates while minimizing resource utilization. The resampling filter comprises a cascade integral combination (CIC) filter and a multi-channel pulse finite impulse response (FIR) filter, optimal hardware cost is achieved, a floating point data type is converted into a fixed point data type, and resources are remarkably saved.

The application discloses a method and device for realizing CORDIC, and the method comprises the following steps: obtaining a target angle; judging whether the absolute value of the target angle is within a set threshold range; if yes, performing a jump-step CORDIC iteration operation; otherwise, performing a full-step CORDIC iteration operation; the full-step CORDIC iteration operation refers to performing a 0-n step CORDIC iteration operation; the jump-step CORDIC iteration operation refers to skipping a 0-m step CORDIC iteration operation, and performing a m+1-n+m+1 step CORDIC iteration operation, wherein m is 0 or a positive integer. According to the application, the calculation precision of CORDIC can be improved.

The invention discloses a CORDIC inverse trigonometric function solving system based on prefix binary tree mapping, and the system comprises a prefix binary tree mapping module which is used for carrying out the multi-stage prefix comparison of an input independent variable x, and directly outputting a unit vector corresponding to the (k + 1) th iteration, so as to replace the first k stages of micro-rotation iterations of a CORDIC algorithm; and the CORDIC iteration module is used for taking the unit vector output by the prefix binary tree mapping module as an initial value, taking an input independent variable x as an initial comparison value, continuing to finish the rest (M-k-1)-level iteration from the (k + 1)-th level, and outputting a final iteration result. According to the CORDIC anti-trigonometric function solving system based on prefix binary tree mapping provided by the invention, on the premise of keeping the calculation precision, the early-stage iteration process of a CORDIC algorithm is effectively replaced, the calculation resource consumption and the operation time delay are remarkably reduced, meanwhile, the precision loss caused by approximate gain compensation is thoroughly avoided, and the calculation efficiency is improved. Therefore, the requirement of a real-time high-performance computing system for high-precision transcendental function operation is met.

The application relates to the technical field of digital signal processing and integrated circuit, and provides a pipeline high-precision fixed-point complex modulus circuit and method, wherein after in-depth analysis, reasoning and verification according to the principle of CORDIC algorithm, a new fixed-point complex modulus circuit logic is improved and designed, so that the complex Euclidean norm operation can be replaced by simple addition and subtraction and shift operation, the circuit logic structure is greatly simplified, the hardware resource consumption of the modulus operation is greatly reduced, finally, a high-efficiency low-resource-consumption fixed-point modulus operation is formed, and the circuit supports pipeline operation, so that the calculation speed is ensured.

The invention discloses a DRM channel modulator based on a CORDIC algorithm. The DRM channel modulator comprises an FPGA module used for realizing logical operation and supporting double-clock domain operation; the memory module is used for caching rate mismatch data between the front-stage encoder and the rear-stage modulator; the clock module is provided with double frequencies, the clock module is used for serving high-speed operation and low-speed signal processing, and the clock module realizes synchronization of two paths of clocks through an MMCM; and the high-speed AD / DA module is used for digital pre-distortion closed-loop correction expansion. Parallel processing of 1024 subcarriers is supported through the assembly line CORDIC, and the single symbol delay is far smaller than the minimum symbol period of the DRM. Due to the one-hot code and check bit design, the bit error rate during signal-to-noise ratio is reduced by two orders of magnitude compared with that of a traditional scheme; iFFT (Inverse Fast Fourier Transform) points can be configured, DRM30 and DRM + modes are supported, and an existing transmitter modulation module can be directly replaced.

The invention is applicable to the field of digital signal processing, and discloses an FFT (Fast Fourier Transform) calculation method, system, equipment and medium based on CORDIC (Coordinated Rotation Digital Integrated Circuit) of an angle precoding circumference system, the method comprises the following steps: acquiring an input angle to be calculated, and obtaining a vector and a residual angle by inquiring a predefined distribution table; based on residual angle block coding, obtaining a non-scaling twiddle factor corresponding to the coded angle through Taylor expansion, and rotating the vector to obtain a rotated vector and a micro angle; obtaining a trigonometric function value corresponding to the input angle by combining approximate processing with multiply-add operation based on the rotated vector and the micro angle; and according to the received sampling sequence data, applying the trigonometric function value as a twiddle factor, and executing complex multiplication and data exchange in each level of butterfly operation unit of the FFT to obtain FFT spectrum data. The CORDIC algorithm with few iterations, high calculation precision and low hardware resource consumption is realized, and the FFT calculation efficiency and performance are improved.

The application relates to the technical field of digital signal processing, in particular to a non-scaling reconfigurable CORDIC calculation method based on a lookup table and a micro-rotation angle set, which comprises the following steps: input angle and a mode selection signal are acquired; based on the mode selection signal, a first-stage rotation operation is performed on the input angle through the lookup table, the input angle is mapped to a small-angle region, and a first-rotation-vector value and a first residual angle after the first-stage rotation operation are output; a multi-stage iterative micro-rotation operation is performed on the first residual angle by using the micro-rotation angle set, and a final-rotation-vector value is output; wherein the circular rotation and the hyperbolic rotation share the address of the lookup table, the micro-rotation angle set and the rotation operation hardware resources, and the mode switching is performed through the mode selection signal, so that the high reconfigurability of the hardware resources is realized. The method can solve the technical problem that the existing CORDIC architecture is difficult to balance among the convergence range, the hardware resources, the calculation accuracy and the reconfigurability.