321results about "Multi-frequency-changing modulation transference" patented technology

The invention relates to the technical field of radio frequency, in particular to a radio frequency conversion assembly, and the assembly comprises a baseband processing unit which employs a millimeter wave SoC chip and is used for generating and processing an initial transmitting signal of 79-81GHz and an initial receiving signal of 79-81GHz; the frequency conversion unit comprises an up-conversion subunit and a down-conversion subunit, and the local oscillation synthesis unit is used for generating and providing a local oscillation signal with a fixed frequency; the mode switching and processing system is used for selectively performing down-conversion processing on the echo signal or a target radio frequency signal from an external non-cooperative irradiation source in two working modes and then transmitting the echo signal or the target radio frequency signal to the baseband processing unit; the working mode comprises an active mode and a passive mode.

The invention discloses a highly integrated V-band broadband multichannel multimode detector front-end chip, which belongs to the field of millimeter wave integrated circuits and comprises a phase-locked loop module PLL, a radio frequency local oscillator chain module LO, a dual-transmitting channel module TX, a dual-receiving channel module RX, a pulse time sequence control module and an SPI configuration interface module. According to the invention, the problems of difficulty in broadband signal generation, serious multi-channel phase mismatch, complexity and low efficiency of a multi-mode system and difficulty in consideration of transmission link speed and power consumption in the existing V-band detector chip are solved.

The invention relates to the technical field of wireless communication and signal processing, in particular to a short-wave spectrum efficient sampling method and system based on compressed sensing, and the method comprises the steps: collecting full-band power spectrum density data through a low-speed scanning receiver; determining a strong interference frequency point set; generating a binary null observation sequence; loading the binary null observation sequence to an analog front-end frequency mixing circuit, performing analog domain orthogonal frequency mixing and integral processing on the input radio frequency signal, and outputting a voltage sampling value; resolving to obtain a signal sparse coefficient through a compressed sensing reconstruction algorithm; calculating a reconstruction residual error according to the voltage sampling value and the signal sparse coefficient; in response to the condition that the reconstruction residual error is greater than a preset error threshold, triggering a reacquisition process of the power spectral density data; outputting a signal sparse coefficient in response to the condition that the reconstruction residual error is smaller than or equal to a preset error threshold; according to the invention, the problems of limited dynamic range and weak signal submerging are solved, and the receiving sensitivity of weak signals in a strong interference environment is obviously improved.

An electronic device may include an antenna, a receiver, and a transmission line path that couples the antenna to the receiver. A peak detector may receive a radio-frequency signal from the transmission line path and may output a DC voltage indicative of a peak voltage level of the signal. The peak detector may include a pair of square law transistors having source-drain terminals coupled to an output of the peak detector. The peak detector may include a differential pair of transistors coupled between a power supply voltage and the output. The peak detector may include diode-connected transistors coupled between the source-drain terminals and gate terminals of the square law transistors. The diode-connected transistors may cause noise current to flow along feedback loop paths from the source-drain terminals onto the gate terminals of the square law transistors. This may remove noise from the output of the peak detector.

This application discloses a signal processing system and a related apparatus, and relates to the field of millimeter-wave radar technologies. The signal processing system includes: a signal generation unit, a frequency mixing and phase shifting unit, and N transmit ports, where the signal generation unit is configured to generate one baseband signal, where the one baseband signal includes a first baseband signal and a second baseband signal, and the first baseband signal and the second baseband signal are quadrature signals; the frequency mixing and phase shifting unit is configured to perform frequency mixing processing and phase shifting processing on the one baseband signal to obtain N radio frequency signals, where phases or frequencies of the N radio frequency signals are different from each other; and the N transmit ports are configured to respectively transmit the N radio frequency signals, where N is a positive integer. The signal processing system can solve problems of poor linearity and long settling time.

Circuitry is provided that includes a matching circuit, a first mixer coupled to the matching circuit and configured to receive a signal with an oscillation frequency, a second mixer coupled to the matching circuit, a first transmission line path coupled between the matching circuit and an input of the first mixer, and one or more capacitors coupled to the input of the first mixer and configured to reject signals at a harmonic frequency of the oscillation frequency. The wireless circuitry can further include a second transmission line path coupled between the matching circuit and an input of the second mixer. The transmission line path can include a first transmission line for conveying signals between the matching circuit and the first mixer, a second transmission line for conveying signals between the matching circuit and the first mixer, and a floating transmission line interposed between the first and second transmission lines.

In a first aspect, the disclosure provides an apparatus (412a) for wireless communication, comprising: a first clock loop (420) comprising a first plurality of latches (422, 424) that generate a first plurality of clock signals (I, Q) having a corresponding first plurality of phases (I, Q); and a second clock loop (430) comprising a second plurality of latches (432, 434) generating a second plurality of clock signals (I45, Q45) having a corresponding second plurality of phases, where the first clock loop is configured to be enabled or disabled based on the first enable signal and the second clock loop is configured to be enabled or disabled based on the second enable signal. And wherein the second clock loop is configured to be enabled or disabled based on a second enable signal (en).

The embodiment of the invention relates to jitter compensation calibration. According to one embodiment, a method for calibrating a local oscillator in an amplitude shift keying (ASK) demodulator of a wireless power transmitter is presented. The method includes: receiving a digital signal corresponding to a voltage or a current of a transmitter coil in a wireless power system implemented with frequency jitter; iteratively adjusting a counter value associated with a jitter table of the local oscillator; wherein for each iteration, the method comprises generating an in-phase (I) component and a quadrature (Q) component using a local oscillator, calculating a metric based on the I component and the Q component, and storing a counter value if the calculated metric exceeds a previously stored optimal metric; and configuring the local oscillator with the stored counter value associated with the optimal metric.

The invention relates to a multichannel down-conversion chip, a multichannel down-conversion circuit and a receiver, and the chip comprises a local oscillator signal processing module which accesses a local oscillator signal, carries out the amplification and power division of the local oscillator signal, and obtains a plurality of local oscillator power division signals; based on the local oscillator power division signal, phase shifting is carried out to obtain a phase-shifted local oscillator signal, and the phase-shifted local oscillator signal is input of a frequency mixer in a corresponding channel; each channel of the multi-channel module is provided with a radio frequency amplifier, a frequency mixer and an intermediate frequency amplifier which are connected in sequence, the input end of each radio frequency amplifier is used for accessing a received radio frequency signal, and the output end of each intermediate frequency amplifier is the output end of the corresponding channel; by adopting the chip, the number of components required in the down-conversion circuit can be effectively reduced, the manufacturing cost of the down-conversion circuit is reduced, and the plurality of components such as the radio frequency amplifier, the frequency mixer and the intermediate frequency amplifier are integrated in the same chip, so that the size of the down-conversion circuit can be reduced, and the miniaturization requirement can be met.

The invention provides a hundred-time frequency range ultra-wideband frequency conversion circuit, a hundred-time frequency range ultra-wideband frequency conversion structure and a miniaturization design method of the hundred-time frequency range ultra-wideband frequency conversion circuit. The hundred-time frequency range ultra-wideband frequency conversion circuit comprises an amplitude limiting amplification circuit, the frequency division preselection filtering module is used for carrying out segmented filtering on the ultra wide band radio frequency signal so as to reduce the influence of a harmonic signal and an out-of-band spurious signal on the circuit; the multi-stage frequency mixing module is used for mixing frequency; the local oscillation module is used for driving the multi-stage frequency mixing link to perform frequency conversion; the ultra-wideband frequency conversion circuit realizes ultra-wideband frequency conversion. The invention further designs a frequency conversion structure based on the circuit, the structure adopts a ceramic three-dimensional stacked structure design, grooves are formed in corresponding ceramic tube shells, the corresponding circuits are arranged in the corresponding grooves or formed cavities, and the circuits are isolated through a sealing process; the problem of low integration level of a circuit system in the prior art is solved through the frequency conversion structure.

The invention relates to the technical field of delay module design, in particular to a multi-channel broadband radio frequency signal delay device and method, and the method comprises the steps: sampling an input multi-channel broadband radio frequency signal, converting an analog signal into a digital signal, carrying out the filtering of the sampled digital signal, and outputting a filtered signal; screening out a frequency component of a target frequency band; converting the filtered digital signals into two paths of I / Q complex digital signals; writing the converted two paths of I / Q complex digital signals into a synchronous FIFO (First In First Out) storage module in an AXIS flow form; performing interpolation processing on the two I / Q complex digital signals read from the FIFO storage module; and IQ modulation is carried out on the digital signal after interpolation processing, and the digital signal is converted into an analog radio frequency signal to be output. Accurate control of multi-channel broadband radio frequency signal delay is realized, and strict requirements on signal delay precision in different application scenes can be met.

The invention relates to a transmitting link frequency conversion method for a 92-94 GHz millimeter wave radar system. The method comprises the following steps: acquiring a 79-81 GHz input radio frequency signal and a 13 GHz local oscillator signal; frequency mixing processing is carried out through a frequency mixer, and a frequency mixing output signal containing 92-94 GHz target frequency components and non-target frequency components is generated; determining a frequency parameter, an amplitude parameter and a phase parameter of the non-target frequency component based on the sampling data sequence; generating a compensation signal according to the frequency parameter, the amplitude parameter and the phase parameter of the non-target frequency component; and synthesizing the compensation signal and the frequency mixing output signal to obtain a 92-94 GHz output signal. According to the invention, the frequency spectrum purity of 92-94 GHz output signals is improved.

Architectures are presented for transmitters and receivers that use a harmonic rejection mixer that uses a 6-phase clock signal, while also using a differential in-phase / quadrature input signal (for the transmitter) or output signal (for the receiver). This results in crosstalk between the in-phase and quadrature components, where a digital correction circuit forms a linear combination of the baseband I / Q signals to generate the I / Q for the mixer in order to obtain the desired baseband signal. By using a differential I / Q signal, only two DACs / ADCs are needed, saving circuitry area and power consumption, while providing strong 2nd, 3rd, and 4th clock harmonic rejection. The clock signal can be composed of two sets of 3-phase signals, each signal having a 33% duty cycle.

The embodiment of the invention provides a frequency multiplication amplification circuit applied to a phase-locked loop and communication equipment, and the frequency multiplication amplification circuit applied to the phase-locked loop comprises a local oscillator frequency division module which is electrically connected with the output end of the phase-locked loop and is used for receiving a radio frequency signal output by the phase-locked loop and outputting a local oscillator signal according to the radio frequency signal; the frequency mixing module is electrically connected with the output end of the phase-locked loop and the output end of the local oscillator frequency division module, and is used for synthesizing a frequency mixing signal according to the radio frequency signal and the local oscillator signal; wherein the frequency of the frequency mixing signal is greater than that of the radio frequency signal. According to the technical scheme, the frequency multiplication amplification circuit is arranged outside the phase-locked loop, the frequency of the output signal of the phase-locked loop can be amplified, the output frequency of the phase-locked loop can be expanded without changing a core circuit in the phase-locked loop, and the frequency multiplication amplification circuit applied to the phase-locked loop is simple in structure.

A semiconductor device comprising at least one transmit path is provided. The transmit path comprises an input node for receiving a digital baseband signal. Further, the transmit path comprises digital mixer circuitry coupled to the input node and configured to generate an upconverted digital baseband signal by upconverting a frequency of the digital baseband signal. Additionally, the transmit path comprises Digital-to-Analog Converter (DAC) circuitry coupled to the digital mixer circuitry and configured to generate an analog radio frequency signal based on the upconverted digital baseband signal. The transmit path comprises first analog mixer circuitry coupleable to an output of the DAC circuitry, and second analog mixer circuitry coupleable to the output of the DAC circuitry. Further, the transmit path comprises a first output node coupleable to an output of the first analog mixer circuitry, and a second output node coupleable to an output of the second analog mixer circuitry.

The invention belongs to the technical field of measurement and testing, and relates to a multichannel ultra-low noise phase synchronization frequency selectable clock synthesis device. The device comprises an ultra-low phase noise frequency multiplication unit, an analog discrete phase-locked loop unit, a frequency mixing filtering unit and a multi-path synchronous power division unit which are connected in sequence. An analog microwave device is selected, so that the phase noise influence of a digital device on a clock signal is avoided; and meanwhile, a plurality of analog discrete phase-locked loops are adopted to realize an ultra-low phase noise clock signal, frequency mixing and filtering are performed to obtain a clock signal with the required frequency, and the phase is synchronized with an external reference clock. Functional unitization is carried out, the design logic is clear, and combination design is facilitated.

The invention discloses a frequency duplex synthesis method for realizing a terahertz ultra-wideband frequency multiplier, and relates to the technical field of submillimeter wave / terahertz solid-state frequency multipliers, a'frequency division-frequency multiplication-frequency combination 'duplex circuit architecture is adopted, a frequency division circuit and a frequency combination circuit are both based on a hybrid network type waveguide duplexer design, and the frequency division-frequency multiplication-frequency combination duplex circuit design is adopted. The frequency multiplier circuit is realized by adopting a hybrid integrated frequency doubler, the cost is low, the cavity structure is completely processed by adopting a CNC milling process, and the solid-state characteristic is realized; therefore, under the condition that the frequency doubling / frequency conversion efficiency is not reduced, the frequency doubler capable of covering the full frequency band of 170-260GHz (WR-4 frequency band) can be realized, namely, the double advantages of wide frequency band and high efficiency of the frequency doubler are considered, and the technical problem that the wide frequency band and the high efficiency of a submillimeter wave / terahertz schottky frequency doubler at the present stage cannot be achieved at the same time is solved.

The utility model relates to a Ka frequency band multichannel frequency conversion assembly in the field of spaceflight measurement and control. The Ka frequency band multichannel frequency conversion assembly comprises a front selection filter, a low noise amplification unit, a switch selection network unit, a multichannel frequency conversion unit and an assembly power supply and control unit. Wherein each channel comprises a front selection filter and a low-noise amplification unit; the switch selection network is used for shunting each path of input signal and selecting the signal through a multi-stage switch; the multi-channel frequency conversion unit completes frequency conversion of multi-channel signals and frequency multiplication, shunting and amplification of local oscillation signals; and the external imaging baseband unit issues control data to the component power supply and control unit to control the switch selection network output signal. According to the utility model, each frequency conversion link is subjected to twice frequency conversion, filters are arranged before and after frequency conversion, and the link spurious suppression degree is high. According to the utility model, all the modules are designed in an integrated manner, interconnection cables do not exist among the modules, the integration level is high, the reliability is high, the stray is less, and the anti-interference capability is strong.

The application discloses a multi-octave wideband frequency conversion assembly, which comprises a frequency conversion circuit, an amplitude control circuit and a switch filter set, wherein the frequency conversion circuit expands the input radio frequency to an intermediate frequency signal through two local oscillator frequency points for the input radio frequency signal and outputs the intermediate frequency signal to the amplitude control circuit; the amplitude control circuit adjusts the amplitude of the intermediate frequency signal output by the frequency conversion circuit; the switch filter set filters the signal output by the amplitude control circuit through a multi-path filter set, filters out harmonics and stray signals, and performs amplitude correction to obtain a multi-octave intermediate frequency output signal. The 3-4GHz signal is expanded to a ten-octave signal of 0.2-2GHz which can be directly processed by a digital circuit through the two local oscillator frequency points of 4 / 5GHz, the output power reaches 10dBm, the harmonic suppression reaches more than 48dBc, the power flatness reaches ±1dB, the dynamic range reaches more than 60dB, and the step is only 0.25dB.

Certain aspects provide a circuit for frequency translation. The circuit includes first mixer circuitry coupled to a load circuit and having a first mixer configured to generate, based on a first differential input signal and a second differential input signal, a first portion of a frequency translated differential signal to be provided to the load circuit, and a second mixer configured to generate, based on a third differential input signal and a fourth differential input signal, a second portion of the frequency translated differential signal. The circuit also includes second mixer circuitry coupled to another load circuit and having a third mixer configured to generate, based on the first differential input signal and the fourth differential input signal, a first portion of another frequency translated differential signal, and a fourth mixer configured to generate, based on the third differential input signal and the second differential input signal, a second portion of the another frequency translated differential signal.

The invention is suitable for the technical field of terahertz frequency mixing, and provides a terahertz monolithic integrated harmonic mixer. The mixer comprises a substrate and devices. The radio frequency port, the local oscillator port and the first matching transition structure are respectively connected with each coupling end of the coupler; the output end of the first matching transition structure is connected with the input end of the second matching transition structure and the first end of the anti-parallel diode pair. The second end of the anti-parallel diode pair is provided with a third grounding through hole. The output end of the second matching transition structure is connected with the input end of the low-pass filter; the output end of the low-pass filter is connected with the intermediate frequency port; the radio frequency port, the local oscillator port and the intermediate frequency port are GSG interfaces with grounding through holes; and a layer of metal is integrally arranged on the back surface of the substrate to connect the grounding through holes to form a coplanar waveguide. According to the mixer, harmonic mixing is realized through a simple process, the complexity is low, and meanwhile, the problems that the mixer cannot be integrated and the working frequency is low can be solved.

The present application discloses a communication circuit. The communication circuit includes: a clock input; and a clock divider configured to generate an output clock signal having a fundamental frequency substantially equal to the fundamental frequency of an input clock signal received at the clock input divided by a factor (2 N +1) / 2 N , wherein the clock divider is configured to generate 2 based at least in part on the input clock signal N +1 pre-aligned phase-shifted clock signal; based at least in part on 2 N +1 pre-aligned phase-shifted clock signal to generate 2 N A specific phase-shifted clock signal, where 2 N The phase of a specific phase-shifted clock signal is basically 360 / 2 N degree of separation; and based at least in part on 2 N a specific phase-shifted clock signal to generate an output clock signal; and a mixer configured to receive the output clock signal.

The invention discloses a high-precision digital double-mixing phase discriminator, and belongs to the technical field of time transfer. Comprising a sampling amplification module, the output end of the sampling amplification module is connected with a signal processing module, and the output end of the signal processing module is connected with a result output module; the sampling and amplifying module is used for receiving two paths of input clock signals fCLKA and fCLKB, and sampling and amplifying the fCLKA and fCLKB by cascading two paths of multi-stage D triggers, so that the phase difference of the two paths of input clock signals is reserved and amplified, and the probability of metastable state occurrence is reduced; the signal processing module is used for carrying out jitter optimization processing on the two paths of sampled and amplified signals and extracting stable signal edges; and the result output module is used for measuring the amplified phase difference according to the two paths of signals subjected to jitter optimization, and obtaining the original phase difference through scaling down. Digital amplification is adopted, analog devices are not needed, noise introduction and delay uncertainty are avoided, and therefore the linearity and reliability of measurement are improved.

This disclosure provides systems, methods, and devices for wireless communication that support reconfiguring degeneration components in a converged RF transceiver supporting carrier aggregation across sub-6 GHz frequency bands and mmWave frequency bands. In a first aspect, an apparatus includes an input port configured to receive a mixer input signal; a first mixer forming at least a portion of an HRM mixer and coupled to the input port; a first configurable degeneration component of a first processing path coupled between the input port and the first mixer; and a controller coupled to the first degeneration component, wherein the controller is configured to control a first aspect of a first degeneration component. Other aspects and features are also claimed and described.

The application discloses a terahertz mixer, comprising: a radio frequency input waveguide, a local oscillator input waveguide, a local oscillator filter and an intermediate frequency output waveguide, wherein the intermediate frequency output waveguide comprises a built-in fin line transition structure and a Schottky diode pair; one end of the fin line transition structure is connected with the radio frequency input waveguide, the other end of the fin line transition structure is connected with the local oscillator filter, the Schottky diode pair is connected with one side of the fin line transition structure and connected with an intermediate frequency output port of the intermediate frequency output waveguide; after the local oscillator signal is filtered by the local oscillator filter, the local oscillator signal is transmitted to the fin line transition structure, the radio frequency signal and the local oscillator signal are loaded into the Schottky diode pair through the fin line transition structure for frequency mixing, and the intermediate frequency signal is output through the intermediate frequency output port. In this case, the fin line transition structure simultaneously carries the radio frequency signal and the local oscillator signal, which can realize spatial superposition and power efficient injection of the signals, and has good impedance matching characteristics.

The utility model discloses a low power consumption multichannel transmit-receive frequency agility device, which comprises a fast hopping frequency source unit, an up-conversion channel unit, a down-conversion channel unit and a control and power supply unit, and a frequency source assembly comprises a one-to-two power divider A, a first phase-locked loop branch, a second phase-locked loop branch, a one-out-of-two switch, a one-to-two power divider B and a frequency multiplier. The first phase-locked loop branch and the second phase-locked loop branch are respectively connected between the one-to-two power divider A and the one-out-of-two switch, the one-out-of-two switch is connected with the one-to-two power divider B, the rear end of the one-to-two power divider B is provided with a first output branch and a second output branch, and the frequency multiplier is arranged in the second output branch; the up-conversion channel unit and the down-conversion channel unit are respectively connected with the frequency source assembly. Two phase-locked loop circuits are configured for a channel to form a set of architecture in which a local oscillator signal 1 and a local oscillator signal 2 share a frequency source, so that the use of phase-locked loops is reduced, and the power consumption and the heat consumption are reduced.

The invention provides a W-band sixteen-channel chip circuit model, and relates to the technical field of radio frequency integrated microsystems. The model comprises an up-conversion frequency mixing circuit, a down-conversion frequency mixing circuit and sixteen channel circuits connected in parallel, and each channel circuit comprises two branch circuits connected in parallel. Wherein one branch is sequentially connected in series with a low-noise amplification circuit, a first six-bit numerical control phase shift circuit, a first driving amplification circuit, a five-bit numerical control attenuation circuit and a second driving amplification circuit, and the other branch is sequentially connected in series with a first power amplification circuit, a second six-bit numerical control phase shift circuit and a second power amplification circuit. The sixteen channel circuits are all connected to an input port of the radio frequency switch circuit S. The up-conversion frequency mixing circuit and the down-conversion frequency mixing circuit are respectively connected with two output ends of the radio frequency switch circuit S. According to the method, the design speed of a complex circuit or system can be increased, and a priori condition is provided for research of a large-scale complex network.

The invention relates to a microstrip double-balanced quadrature mixer, which comprises a power divider, a first three-port balun, a second three-port balun, a first double-balanced mixer, a second double-balanced mixer, a first four-port balun, a second four-port balun and a 90-degree directional coupler, a local oscillator signal port, a radio frequency signal port, a first intermediate frequency signal port and a second intermediate frequency signal port are arranged; wherein the output ends of the two three-port Baluns and the output ends of the two four-port Baluns generate a pair of differential signals with the difference of 180 degrees; the 90-degree directional coupler generates two radio frequency signals with the difference of 90 degrees; two intermediate frequency signals are led out from the isolation ports of the two four-port Baluns. Therefore, a group of orthogonal radio frequency differential signals can be generated through the 90-degree directional coupler, and frequency mixing processing is performed through the double-balanced frequency mixer, so that the isolation degree of a radio frequency port and a local oscillation port is greatly improved, leakage of signals of the local oscillation port and signals of an intermediate frequency port is suppressed, and the image frequency rejection degree is improved.

The application discloses a kind of very small step local oscillator devices, comprising: reference signal source;DDS synthesizer is used to receive the output signal of reference signal source, and output the first output signal of lower frequency;First filter is used to filter the first output signal, and obtain the first to-be-mixed signal;Frequency multiplier is used to receive the output signal of reference signal source, and output the second output signal of higher frequency;Second filter is used to filter the second output signal, and obtain the second to-be-mixed signal;Mixing frequency ware is used to mix the first to-be-mixed signal and the second to-be-mixed signal, and obtain mixed signal;Third filter is used to filter mixed signal, and obtain phase-locked loop reference signal;Phase-locked loop module is used to receive phase-locked loop reference signal, and output local oscillator signal.It also discloses a kind of very small step local oscillator method.The application is while realizing very small step local oscillator scheme, also has very low decimal step spur.

The present application relates to a method and system for improving the broadband active mixer reversible design method of reversible neural network, the method comprises: obtaining the response of the broadband active mixer, wherein the response comprises the conversion gain G and the noise figure NF; inputting the response into the R-INN model, and outputting the design parameters of the broadband active mixer, wherein the design parameters comprise resistance and capacitance, the R-INN model is constructed by combining real non-volume preserving transformation with reversible neural network, the R-INN model is obtained by training the training set, and the training set comprises the design parameters in the preset range and the corresponding response. By introducing an improved reversible neural network model combined with real non-volume preserving transformation technology, the accuracy of forward prediction is optimized, and the posterior distribution of the design parameters is effectively back calculated, thereby improving the efficiency and accuracy of the optimization design of the broadband active mixer.