471 results about "Phase relation" patented technology

A waveguide busbar for converting a plurality of high-frequency input signals into high-frequency output signals, includes a waveguide, a plurality of input ports, which are arranged along the waveguide, such that each input port is intended to receive a high-frequency input signal, an output port on the waveguide for delivering the high-frequency output signal and at least one parallel resonator, which is connected to the waveguide busbar between two input ports. The parallel resonator has a mechanically adjustable volume with which a phase relation of the waveguide is adjustable between the two input ports.

The invention relates to a method for transmitting a plurality of antenna signals in a wireless Base Transceiver Station (BTS) using Remote Radio Head (RRH) technology and the corresponding system. The method includes the steps of: transmitting signals over the transmit channel using Synchronous Digital Hierarchy (SDH)/Optical Transmission Network (OTN), multiplexing the plurality of antenna signals adopting the manners of time division multiplex or GFP frame-level multiplex; forming the multiplexed antenna signal stream and in-band control signaling stream into Generic Framing Procedure (GFP) frame; or forming the plurality of antenna signals and the plurality of respective control signals on the in-band control signaling channel into a plurality of respective GFP frames in parallel; and further mapping the GFP frames to STM-N/OTM-n frames, therefore multiplexing the plurality of antenna signals and the in-band control signaling stream to realize the SDH/OTN-based transmission. According to the invention, in the circumstance of using a plurality of antennas for transmitting signals, the strict time and phase relations between various antenna signals can be ensured, and also system complexity can be simplified, the transmission delays from various antenna signals to CBTS are totally the same.

The invention discloses a multi-analog-to-digital converter (ADC) high-speed time alternating acquisition system with a data synchronous identification function. Phase relation between multiple ADC data synchronous clocks is measured by adding a test pulse forming module, a high-precision time interval measuring unit, a data feedback control module and a data sequence identification module, and the sequence of sampled data is fed back and controlled according to a measuring result, so real-time correct splicing of parallel time alternating sampling data sequences is realized, reliable guarantee is provided to the processing of sampled data at the rear end, the stable operation of the system is effectively ensured, and the technology lays a firm foundation for construction of a multi-ADC acquisition system with higher sampling rate.

Clock signals are supplied, with a phase shift of 1/n cycles between adjacent clock signals. A data acquisition unit acquires serial data at a timing of each of the clock signals. A phase detection unit detects the phase of the transition edge of the serial data using n bits of data. An effective bit number determination unit determines the effective bit number, which is the number of bits to be acquired, based upon the phase of the transition edge of the serial data in the current data-bit acquisition step and the phase of the transition edge of the serial data in the previous data-bit acquisition step. A data-bit output unit outputs the effective bit number of the bits of data acquired at a timing of each clock signal having a predetermined phase relation with the transition edge of the serial data.

The invention relates to a method for detecting an eccentric load of a roller washing machine by a vibrating sensor. The front-most part or the rearmost part of the outer edge of the outer barrel of the roller washing machine is provided with the vibrating sensor; by utilizing an amplitude and phase relation between vibrations measured in two directions, the vibration state of the outer barrel is judged; a vibration value is tested while rotate speed variation or eccentric weight are tested by adopting an original eccentric load detection method; according to the vibration state of the outer barrel, the distribution of the eccentric load in a roller is judged, and a preset value of the eccentric load is adjusted, and therefore, the weakness that dynamic eccentricity cannot be detected by adopting the original eccentric detection method is overcome. The detection and the protection of the dynamic eccentricity are added, and therefore, the detection precision of the eccentric load is improved, the vibrations and noise when drying is performed are reduced, and the product grade of the rolling washing machine is improved.

A fluctuation characteristic of registration between images printed by individual printing units (4A, 4B, 4C, 4D) while changing print speed is predicted for each of particular printing conditions that affect the registration fluctuation characteristic. Based on the predicted fluctuation characteristic of registration, a control characteristic of the phase between plate cylinders (5, 5, 5, 5) of the individual printing units (4A, 4B, 4C, 4D) is preliminarily set so as to compensate for vertical image misregistration between images printed by the individual printing units (4A, 4B, 4C, 4D), and is stored in a database (32). Then, when the print speed is being changed, from among the plural phase control characteristics thus preliminarily stored in the database (32), a phase control characteristic that corresponds to a printing condition concerning the current printing is selected, and the phase relation between the plate cylinders (5, 5, 5, 5) of the individual printing units (4A, 4B, 4C, 4D) is being modified according to the selected phase control characteristic. Thereby vertical image misregistration can be suppressed and the occurrence of brokes due to the change of print speed can be prevented.

The invention discloses a multichannel parallel acquisition system with a multi-device asynchronous reset recognition correction function. In N ADC and FPGA modules of the multi-channel parallel acquisition system, the first FPGA module sends a reset signal according to a system reset start command to complete the reset operation of the ADC and the DCM, thereby generating a stable data work clock CCLK1 in the FPGA; each of the second to the N-th FPGA modules contains a synchronous recognition module and a reset control module; the synchronous recognition module is used for adjusting a delay value of the data work clock of the former FPGA module, and synchronously recognizing the data work clocks of the current FPGA and the former FPGA through the adoption of a de-serializer and a sequence detection module, using the delay value in synchronization as the time interval, and then adjusting the delay value from the reset signal to the corresponding ADC and the clock management unit according to the time interval, thereby completing the multi-device asynchronous reset recognition correction. Through the adoption of the system disclosed by the invention, the reset accuracy can be guaranteed; therefore, the phase relation of the multi-channel data work clock after each synchronous resetting is determined.

The invention relates to a nuclear phase method for a digital transformer substation, comprising the following steps: 1) in a digital transformer substation realized in a point-to-point mode, a nuclear phase device accesses high-speed serial communication data from different interval merging units, and sends the received communication data to a personal computer (PC), and the PC randomly selects one phase voltage as a standard and respectively and intuitively inspects the correctness of the amplitude and phase relation of each phase voltage of the same voltage class or different voltage classes, thereby completing secondary nuclear phase in the process of starting the digital transformer substation; and 2) in a digital transformer substation realized in a networking mode, the nuclear phase device accesses Ethernet communication data from different interval merging units by means of an IEC61850 switched network device, and then sends the communication data to the PC, and when carrying out voltage nuclear phase, the PC randomly selects one phase voltage as a standard and respectively inspects the correctness of the amplitude and phase relation of voltages of the same voltage class or different voltage classes.

An improved AC power supply is described. The supply identifies the load through monitoring the current and voltage wave forms and phase relations with the AC Mains. The comparison is done in conditions where the power to the load is programmably varied through use of a control switch located in the line and neutral between the AC mains and the load. The program of controlling the switch is varied to optimize the ability to distinguish similar load types. The switch can be further used to control power to the load that varies according to a set of rules based upon the identity of the load. In a preferred embodiment, the design enables high efficiency with minimal components that may be fully integrated onto silicon.

The invention relates to a spatial carrier based interference confocal measuring device and a method, belonging to the technical filed of measurement of surface topography. The measuring device comprises a laser, a collimation focusing objective lens, a pinhole, a collimation expander objective lens, a polarization beam splitter, a quarter wave plate, a beam splitter, a detection focusing objective lens, a second microdrive and a collecting objective lens, wherein the rear side of the beam splitter along the direction of a primary optical axis of the laser is sequentially provided with an auxiliary reference lens and a first microdrive, a main reference lens is arranged between the beam splitter and the detection focusing objective lens, a CCD camera is placed on a focus position of the collecting objective lens, and a master control computer is connected with the CCD camera and the first microdrive. The method comprises the steps: establishing displacement and phase relation by a secondary confocal method, introducing a carrier signal by tilting the auxiliary reference lens, obtaining a carrier interferogram, acquiring the phase information of a measured surface by a spatial carrier phase-shifting algorithm, and finally fitting surface topography and three-dimensional profile. The invention is suitable for dynamic, quick and high-precision measurement of micro-structure three-dimensional topography.

A bit synchronization circuit comprising an initial phase determining unit for rapidly determining, during a period of receiving a preamble of burst data, a clock with a phase synchronized with received burst data from among multi-phase clocks having the same frequency as an internal reference clock and a phase tracking unit for modifying the synchronized phase clock responsive to phase variation of received data during a period of receiving a payload of burst data by taking the synchronized phase clock determined by the initial phase determining unit as an initial phase. The bit synchronization circuit retimes burst data with a data retiming clock having a predetermined phase relation with the synchronized phase clock and outputs the burst data in synchronization with the internal reference clock.

The invention discloses a method of realizing line-to-ground fault phase selection by using a sequence voltage phase characteristic. The method comprises the steps of firstly using the phase relation between zero-sequence voltage and A phase negative sequence voltage to form a criterion and accurately judging whether a transmission line fault is a grounded short circuit fault; secondarily using the magnitude relation between interphase fault impedance and setting impedance to form a criterion; and differentiating a single-phase grounded short circuit fault and a two-phase grounded short circuit fault. When a high impedance grounded short circuit fault occurs on a transmission line at a weak power source side and under the condition that the system operation mode is changed greatly, the method is high enough in phase selection sensitivity, the specific grounded fault phase can be accurately judged, the method is applicable to the fault phase selection of the whole fault process of the transmission line grounded short circuit fault, and is applicable to the fault phase selection of a climbing transmission line high impedance grounded short circuit, and accurate and reliable fault phase information can be provided for distance protection and automatic reclosing lock correct operation.

The invention relates to a state diagnosis method for a small-current ground fault line selection device, which comprises the following steps of: firstly, sequentially doing an instantaneous ground fault experiment for a plurality of lines connected on a bus by utilizing the small-current ground fault line selection device to be diagnosed, wherein if the lines of which zero-sequence current phases are lagged behind a zero-sequence voltage phase of the bus by 90 degrees are more than the lines of which the zero-sequence current phases are ahead of the zero-sequence voltage phase by 90 degrees in the ground fault experiment, the PT (Potential Transformer) connecting mode of the bus is correct, or the PT connecting mode of the bus is wrong; and then, on the premise of determining that the PT connecting mode of the bus is correct, according to a phase relation of a zero-sequence current of each line and a zero-sequence voltage of the bus of a substation, judging whether the CT connecting mode of each line is correct. According to the invention, the connecting fault of the small-current ground fault line selection device can be rapidly and accurately diagnosed and the debugging period of the line selection device is shortened, so that the maintenance cost of the line selection device is reduced.

The invention discloses a precision digital delay synchronization method based on phase compensation. The method comprises the following steps: measuring a phase relation between external triggering and a local clock by using a TDC based on a FPGA carry chain in one FPGA, performing computing by fusing the triggering relation between the external triggering and the local clock and the preset delayparameter by combining the coarse counting with the fine delay, thereby obtaining corresponding coarse counting value and fine delay series; compensating the phase of the external triggering signal when the external triggering signal and the local clock are asynchronous, thereby realizing the situation that the external triggering jittering of the digital delay synchronizer is less than 100ps, and the delay precision is 100ps. The phase of the external triggering signal is compensated when the external triggering signal and the local clock are asynchronous, thereby effectively reducing the triggering error of the delay synchronizer; the fine delay processing is performed by using IODELAY resource, and the delay resolution is greatly improved; all TDC circuits, a computing control circuitand a delay circuit are integrated into one FPGA, and the circuit is simple and reliable, high in integration degree and small in power consumption.

A transmit/receive filter includes a substrate, an antenna terminal, a transmit filter assembly arranged on a first substrate portion, an output of the transmit filter assembly being connected to the antenna terminal, a receive filter assembly arranged on a second substrate portion, and a discrete phase shifter arranged on a third substrate portion, the discrete phase shifter being formed of discrete circuit elements and an input of the receive filter assembly being connected to the antenna terminal via the discrete phase shifter, the discrete phase shifter being formed to set a predetermined phase relation to decouple the receive filter assembly from the transmit filter assembly.

The invention relates to a method for quickly positioning a phase-sensitive optical time-domain reflection distributed optical fiber sensing system. The method comprises the following steps of: constructing a Rayleigh scattering light digital signal matrix corresponding to a plurality of optical pulses; selecting test windows and test columns on the signal matrix at certain intervals; acquiring the phases of respective test columns; roughly positioning a disturbance source section according to adjacent test windows test column phase; and extracting a section signal (between two adjacent test window test columns) including the disturbance source for accurate disturbance positioning. The method analyzes the phase relation of the Rayleigh scattering light at different positions of an optical fiber to realize a rough positioning-precise positioning process of a [phi]-OTDR optical fiber sensing system, reduces the burden of the system by neglecting a large amount of invalid sensing information, solves poor real-time performance in the distributed sensing system caused by a large signal data size and a large system calculation magnitude, and is suitable for various coherent detection demodulation [phi]-OTDR system.

The invention relates to a method for constructing central pattern generator (CPG) control network topology structure of biped robot. The method comprises the steps of separating a CPG control network into a body network portion for controlling hip joints and a leg network portion for controlling leg joints to achieve symmetry of control signals for left and right leg joints and control over reasonable phase relations of left and right legs; optimizing coupling connection modes among neuron units in the CPG control network to reduce the complexity of the CPG control network; and performing parameters setting on the CPG control network to construct an optimal network topology structure. Compared with the prior art, the method has the advantages of being low in complexity, reasonable in control network structure and the like.

The invention provides a method and a system for locking detection of a phase-locked loop and a phase-locked loop circuit. The method comprises the following steps: acquiring an input signal and a feedback signal; delaying the input signal and the feedback signal, wherein the corresponding time delay links of the input signal and the feedback signal are a first reference signal and a second reference signal respectively; judging the phase relations among the second reference signal, the input signal and the first reference signal, wherein the rising edge of the second reference signal is a leading phase before the rising edge of the input signal and the rising edge of the first reference signal and is a lag phase after the rising edge of the input signal and the rising edge of the first reference signal; and accumulating the leading phase and the lag phase in a predetermined counting period, and determining that the link of the phase-locked loop is not locked when the continuous occurrence number of the leading phase or the lag phase exceeds a predetermined numerical value. By adopting the double-output phase relation between the feedback clock delay link and the input clock delay link, the large input jitter is determined by the accumulation number, so the tolerance of the phase-locked loop to the input jitter is enhanced.