Multichannel parallel acquisition system with multi-device asynchronous reset recognition correction function

Abstract

The invention discloses a multichannel parallel acquisition system with a multi-device asynchronous reset recognition correction function. In N ADC and FPGA modules of the multi-channel parallel acquisition system, the first FPGA module sends a reset signal according to a system reset start command to complete the reset operation of the ADC and the DCM, thereby generating a stable data work clock CCLK1 in the FPGA; each of the second to the N-th FPGA modules contains a synchronous recognition module and a reset control module; the synchronous recognition module is used for adjusting a delay value of the data work clock of the former FPGA module, and synchronously recognizing the data work clocks of the current FPGA and the former FPGA through the adoption of a de-serializer and a sequence detection module, using the delay value in synchronization as the time interval, and then adjusting the delay value from the reset signal to the corresponding ADC and the clock management unit according to the time interval, thereby completing the multi-device asynchronous reset recognition correction. Through the adoption of the system disclosed by the invention, the reset accuracy can be guaranteed; therefore, the phase relation of the multi-channel data work clock after each synchronous resetting is determined.

Description

technical field [0001] The invention belongs to the technical field of ultra-high-speed data acquisition, and more specifically relates to a multi-channel parallel acquisition system with multi-device synchronous reset, identification and correction functions. Background technique [0002] With the rapid development of science and technology, the complexity of the signal is increasing, and the requirements for the sampling rate of the acquisition system are gradually increasing. Due to the restriction of the sampling rate of the single-chip ADC (Analog-to-Digital Converter) chip, only The sampling rate of the system is increased by means of parallel acquisition. A more popular approach is to use time-alternative analog-to-digital conversion (TIADC) technology to increase the sampling rate of the system. However, it is difficult for the system of parallel acquisition of multiple devices to reset completely at the same time due to the reset signal, so the asynchronous reset s...

AI Technical Summary

Problems solved by technology

These two methods can solve the problem of multi-ADC synchronous reset, but either the required hardware is more complex, or the debugging process is more cumbersome, and it is difficult to be effectively implemented in actual projects.

Moreover, they are greatly affected by temperature. Once the temperature changes, the corrected phase will shift again, increasing the risk of reset uncertainty.

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