46 results about "Clock management unit" patented technology

The invention relates to a high-speed data synchronous acquisition and emission system suitable for a satellite communication MIMO (Multiple Input Multiple Output) system. The system comprises two acquisition and emission daughter cards and a clock management unit, the acquisition and emission daughter card comprises a multi-channel ADC acquisition unit and a multi-channel DAC refreshing unit; a multi-channel ADC acquisition unit of the acquisition and emission daughter card sends acquired data to an FPGA for processing through a JESD204B interface, and then the data is forwarded through an optical module; a multi-channel DAC refreshing unit of the acquisition and emission daughter card sends data received by the optical module to an FPGA for processing, and then the data is sent to a DAC through a JESD204B interface for interpolation filtering and IQ conversion, refreshed and output to a radio frequency front end; and the clock management unit realigns the phase of the device clock and the phase of the reference clock in each power-on process by using a trigger signal of the clock chip so as to realize inter-board synchronization. The system can improve the synchronization performance and reduce the power consumption.

A semiconductor device includes a retention circuit configured to retain a data value during a power gating operation, a non-retention circuit configured not to retain a data value during the power gating operation, a clock management unit (CMU) configured to provide a first operation clock to the retention circuit and provide a second operation clock to the non-retention circuit, and a power management unit (PMU) configured to provide a reference clock used to generate the first and second operation clocks to the CMU, generate a first isolation signal to permit a first signal to be output from the CMU, and generate a second isolation signal to permit a second signal to be output from the retention circuit and to permit a third signal to be output from the non-retention circuit.

A semiconductor device includes a retention circuit configured to retain a data value during a power gating operation, a non-retention circuit configured not to retain a data value during the power gating operation, a clock management unit (CMU) configured to provide a first operation clock to the retention circuit and provide a second operation clock to the non-retention circuit, and a power management unit (PMU) configured to provide a reference clock used to generate the first and second operation clocks to the CMU, generate a first isolation signal to permit a first signal to be output from the CMU, and generate a second isolation signal to permit a second signal to be output from the retention circuit and to permit a third signal to be output from the non-retention circuit.

The present invention discloses a physical construction method suitable for meeting triple modular redundancy. In the layout stage, a customized design is adopted for the clock management unit. The three registers in the same group are effectively controlled through scripts during implementation. Since the existing triple modular registers increase the clock delay and have the characteristic of large delay differences under different process corners in advanced processes, the difficulty of timing convergence is reduced, and the design efficiency is effectively accelerated. Finally, the triple modular clock phase difference check is completed by using the clock length comparison method. The present invention can ensure that the single event effect is effectively improved while ensuring that the triple modular design quickly meets the design specifications. The present invention has the advantages of simple process, strong operability, and fast timing convergence speed, and can meet other tape-out sign-off conditions.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronous circuits connected by a scan chain, a test data input (TDI) line, a test data output (TDO) line connected to the output terminal, a test access port (TAP) controller that controls operations of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal, and a test mode select (TMS) signal, a power management unit that controls power gating of the blocks, and a clock management unit that controls a clock signal supplied to the blocks. The TAP controller includes a first register that stores first data used to generate a first control signal that controls the power and clock management unit, the power and clock management unit controlling operations of the blocks based on the first control signal.

The invention relates to the technical field of electronic system time sequence control, in particular to a multi-system clock synchronization method based on a low-frequency calibration clock, which is characterized in that a main system adopts a high-stability clock source and simultaneously generates a high-frequency data clock and the low-frequency calibration clock of which the frequency is less than one thousandth of that of the data clock through a clock management unit; the characteristics of strong anti-interference and high transmission quality of the low-frequency clock are utilized, and the low-frequency clock is sent to each slave system through the optimized clock distribution network. Each slave system extracts a low-frequency calibration clock through a clock recovery circuit, a high-precision time interval measurement unit is adopted to measure the time difference between a local clock and the calibration clock, and the measurement precision and stability are improved through digital signal processing. And each slave system inputs the time difference as a control quantity into a digital regulation system, dynamically regulates the phase of a local clock, and judges a synchronous locking state through a locking state detection mechanism, thereby realizing high-precision, long-term and stable clock synchronization among multiple systems.

The present disclosure relates to a test mode control system capable of testing a clock component that configures a clock management unit and generating a test clock by driving the clock component that generates a functional clock and a system-on-chip including the same. The test mode control system according to an embodiment of the present disclosure includes: a test mode controller that transmits a clock control signal to a clock source that configures a high-speed domain of a clock management unit in a test mode; and a test multiplexer that transfers a clock control signal input from the test mode controller to the clock source in the test mode and transfers a clock control signal input from a clock control circuit corresponding to the clock source to the clock source in a functional mode.

The invention relates to a system and a method for designing a clock management unit in a code-free mode, which can be used for testing a clock component and generating a test clock based on a functional clock path. The system includes a memory to store instructions, and a processor to execute the instructions. The instructions include generating a clock instance including a clock source block, a clock control signal block, and a test multiplexer block; generating a test mode controller instance containing the test data register block; setting connection between the two; and instructions to generate hardware code.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronization circuits connected by a scan-chain, a test data in (TDI) line, a test data out (TDO) line connected to the output terminal, a test access port (TAP) controller to control an operation of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal and a test mode select (TMS) signal, a power management unit to control power gating for the blocks, and a clock management unit to control a clock signal provided to the blocks. The TAP controller includes a first register that stores a first data for generating a first control signal controlling the power and clock management units, which control the operation of the blocks based on the first control signal.

The present invention discloses an electronic countermeasure system with integrated transceiver, and relates to the field of radio frequency technology. The signal processor of the present invention includes a data receiving and sending unit, a data processing and main control unit, and a clock management unit, wherein the data processing and main control unit are respectively connected to the data receiving and sending unit and the clock management unit; the data receiving and sending unit includes multiple synchronously working integrated transceiver chips, and the multiple integrated transceiver chips realize beam synthesis by setting multiple independent local oscillators or by setting multiple identical local oscillators; the data processing and main control unit is composed of multiple FPGAs; the clock management unit includes a clock generation module and a clock synchronization module, and the clock synchronization module is used for inter-board synchronization and intra-board synchronization. The present invention integrates the functions of reconnaissance, direction finding, interference, etc. through multi-chip synchronous acquisition, bandwidth splicing and FPGA technology, which greatly simplifies the design difficulty of traditional superheterodyne architecture receivers, greatly reduces the design cost, and expands the scope of application.

The invention relates to the technical field of computers, in particular to a post quantum cryptography chip integration system and terminal equipment, and the system comprises a main processor which is used for transmitting a post quantum cryptography calculation task; the power consumption detection module is used for receiving the current data provided by the post quantum cryptography chip and the execution state of the post quantum cryptography calculation task, and calculating the power consumption of the post quantum cryptography chip according to the current data; the clock management unit is used for adjusting the clock signal frequency required by the post quantum cryptography chip according to the power consumption and the execution state; the voltage management unit is used for adjusting the voltage required by the post quantum cryptography chip according to the power consumption and the execution state; by flexibly adjusting the clock signal frequency and voltage required by the post quantum cryptography chip, the requirement of terminal equipment for low power consumption is met, reasonable utilization of resources is realized, and long-time standby work is realized.

The invention discloses a semiconductor system and a reset work clock control method thereof, which can input a reference clock slower than a functional clock to a clock work unit through a clock multiplexer when a reset work or a reset release work is performed, thereby easily capturing a reset timing. A semiconductor system according to an embodiment of the present invention comprises: a clock management unit that operates according to a functional clock and generates and outputs an output functional clock for operation of the semiconductor system; and a power management unit that performs power management of the semiconductor system including a reset operation or a reset release operation. The clock management unit comprises a clock working unit which works according to the function clock in a working mode and generates and outputs the output function clock; and the clock multiplexer performs different selections on input clocks input to the clock working unit and outputs the input clocks to the clock working unit in the working mode and the reset mode.

An electronic device includes a clock management unit configured to generate a clock signal, an intellectual property (IP) device configured to receive the clock signal and is configured to perform a task according to the clock signal in an active state, a first counter configured to count cycles of the clock signal while the IP device is in the active state, and is configured to generate a first count, and a frequency controller configured to control the clock management unit to change a frequency of the clock signal when the first count reaches a first reference count.

The invention relates to the technical field of vehicles, in particular to a method and a device for generating a controller of a multi-chip Flash memory and electronic equipment. The method comprises the following steps: acquiring a control parameter written based on a SpinalHDL programming language; wherein the control parameters comprise a first configuration parameter of a register bus, a second configuration parameter of a data reading bus, third configuration parameters of a register unit, a clock management unit, a control unit and a plurality of driving units in the controller, and fourth configuration parameters of at least one Flash memory controlled by the controller; generating a control circuit of the controller based on the control parameter; wherein the control circuit comprises a register bus, a data reading bus and a controller, the controller comprises a register unit, a clock management unit, a control unit and a plurality of driving units, and one driving unit corresponds to one Flash memory.

To provide an image sensor that minimizes the delay of a clock supply by reducing the electric power, and an operation method for the same.SOLUTION: An image sensor includes a plurality of clock consumers (CCs), a plurality of block clock management units (BCMUs), and a top clock management unit (TCMU). Each BCMU transmits a second clock demand signal to TCMU in response to a first clock demand signal received from at least one CC among the CCs. TCMU transmits each clock response signal in accordance with each second clock demand signal. TCMU transmits a second clock signal to each BCMU through a channel formed in transmission and reception of the second clock demand signal and the clock response signal. While the second clock signal is transmitted through the channel, each BCMU transmits the first clock signal corresponding to the first clock demand signal to the CC to which the first clock demand signal has been transmitted among the CCs, on the basis of the second clock signal.SELECTED DRAWING: Figure 1

Disclosed are clock management unit design system and method for designing an internal function module of clock elements constituting a clock management unit and connections between the clock elements using a no-code approach. A clock management unit design system using a no-code approach includes: a memory configured to store at least one instruction; a clock component storage configured to store clock component information constituting a clock management unit; a hardware code logic storage configured to store hardware code logic for generating a designed clock management unit as hardware code; and at least one processor configured to execute the at least one instruction stored in the memory

The present application discloses an air conditioner wire controller circuit and a control method thereof. The circuit includes: a control processing chip provided with a first GPIO port and a second GPIO port; a touch button unit, a WIFI unit, an infrared remote control receiving circuit, an EEPROM storage unit, an indoor unit communication unit, a power-off detection unit, a power supply circuit unit, a clock management unit, and a power management unit electrically connected to the control processing chip. When the first GPIO port outputs a high level and the second GPIO port outputs a low level, i.e., when entering power-off mode, the control processing chip turns on the low-speed clock module of the clock management unit, controls the touch button unit and other functional modules to stop running, and maintains the input of the EEPROM storage unit unchanged. Based on the solution of the present application, when entering power-off mode, the interface input of the EEPROM storage unit remains unchanged, thereby reducing the power consumption of the EEPROM of the air conditioner wire controller and increasing the service life of the EEPROM of the air conditioner wire controller, thereby reducing the cost of the air conditioner wire controller.

Disclosed are a semiconductor system and a method of controlling a reset operation clock of the semiconductor system for easily determining a reset timing by inputting a reference clock slower than a function clock to a clock operation unit by a clock multiplexer during a reset operation or reset release operation. The semiconductor system includes a clock management unit configured to operate according to a function clock to generate and output an output function clock for an operation of the semiconductor system, and a power management unit configured to perform power management of the semiconductor system including a reset operation or a reset release operation. The clock management unit includes a clock operation unit configured to operate according to the function clock in an operation mode to generate and output the output function clock, and a clock multiplexer configured to select different input clocks to be input to the clock operation unit in the operation mode and a reset mode and output the input clocks to the clock operation unit.

The invention discloses a multi-rate controllable 1553 bus controller module, which belongs to the field of avionics and data buses and comprises a 1553 protocol processing module, a Manchester encoder, a Manchester decoder, a sending channel, a receiving channel and an internal clock management unit. The internal clock management unit generates a core clock signal corresponding to a target communication rate according to a signal input by the external rate control pin; and the Manchester encoder / decoder performs data encoding and decoding by using the core clock signal, so that the adjustable switching of the communication rate among 1Mbps, 2Mbps and 4Mbps is realized. Flexible configuration of the communication rate is achieved through hardware pin control, the problems that a traditional 1553 controller is fixed in rate and lack of flexibility are solved, and the controller has the advantages of being high in compatibility, low in cost and high in integration degree.

The invention discloses a 1.6 T Flip Chip high-speed optical module and a flip packaging method, and belongs to the technical field of optical communication. The system comprises a multi-layer rewiring fan-out substrate, a flip chip silicon optical engine, an eight-channel linear driving DSP, a high-speed electrical / optical interface, an active temperature control and heat dissipation system and a power supply and clock management unit, and through the hybrid interconnection technology of Cu / SnAg micro-bump flip bonding and gold wire bonding, the device interconnection distance smaller than or equal to 30 microns and the chip interconnection distance smaller than or equal to 5 mm are achieved. The packaging method comprises the five steps of PD-TIA inversion and lead bonding, PIC integration and interconnection, passive device assembly, MPO coupler active alignment and sealing cover testing. Key process parameters are as follows: the height of a PD-TIA bump is 15 + / -2 microns, the length of a PIC bonding wire is less than or equal to 300 microns, and the MPO coupling loss is less than or equal to 0.5 dB. According to the invention, the size of the optical engine is reduced by 40%, the 3dB bandwidth is improved by 20%, and the failure rate of the device is lt; 100FIT, power consumption lt; the method meets the OSFP-XD standard, and is suitable for a 1.6 T high-speed interconnection scene of a data center.

This application discloses a clock configuration system and method. It includes: a clock generation circuit and a communication module; the communication module includes a configuration unit, a clock management unit, and a communication circuit; the clock generation circuit is connected to the clock management unit in the communication module; the clock management unit is connected to the communication circuit; the communication circuit is connected to the configuration unit; the clock generation circuit provides a reference clock to the communication module; the configuration unit configures the line rate and data bit width of data transmission in the communication circuit, determines a clock division factor based on the line rate and the data bit width, and configures the clock division factor in the clock management unit; the clock management unit determines the operating clock frequency based on the reference clock and the clock division factor, and provides the operating clock frequency to the communication circuit. Determining the operating clock frequency by configuring the line rate and data bit width reduces the complexity of clock configuration in the communication module.

The application provides a RT-THREAD resident system based on D1-H, which comprises a user module and a BIOS module, wherein the BIOS module comprises a hardware abstraction layer, an RTOS layer, and an API layer; the RTOS layer comprises an RT-Thread kernel, a thread management unit, a synchronization and communication unit, a clock management unit, and a memory management unit; the hardware abstraction layer comprises a driver construction, a software component, and a BootLoader; and the API layer comprises a driver component interface, a software component interface, and an RTOS service calling interface.The application has the advantages of reducing the programming threshold, improving the portability of application programs, and improving the compiling speed; the starting process after the RT-Thread is resident is analyzed, a resident test experiment is designed taking the synchronization and communication as an example, and the test result proves the feasibility of the RT-Thread resident.

The present invention relates to a multi-channel data training method based on joint phase adjustment. In this method, a receiver samples a fixed-code training word sent by a transmitter in real time. The FPAG control logic delays the input data by adjusting the IODLEAY data delay unit, completing multi-channel delay alignment. The FPAG control logic adjusts the sampling clock phase by controlling the DCM unit. The FPAG control logic controls the receiver latch position until the data position identical to the training word sent by the transmitter is latched, completing data training. The present invention utilizes the DCM clock management unit and the IODELAY data delay unit within the FPGA to achieve joint phase adjustment of the sampling clock and data input delay, effectively improving the training reliability of high-speed data communications, ensuring that high-speed data can be reliably acquired by the receiver, reducing the bit error rate, and extending its applicability.

The present disclosure relates to a controller, a time synchronization method, and a device control system. A controller, a time synchronization method, and a device control system are provided. The controller includes: a controller clock management unit configured to receive global time data indicating a global time associated with an external global clock, synchronize a controller clock within the controller with the global clock based on the global time, and set a controller time based on the synchronized controller clock; and a notification unit configured to transmit the controller time data indicating the controller time to at least one local device via periodic communication.

This invention discloses a three-in-one sensor for in-ear headphones, comprising: a substrate; a bare die disposed on the top of the substrate, the bare die including a differential delay chain, a microprocessor, and a power and clock management unit, the differential delay chain being electrically connected to the microprocessor, the microprocessor being electrically connected to the power and clock management unit, a pin frame disposed at the top edge of the substrate, and further including pins, the pins being disposed on the top of the substrate through the pin frame. This three-in-one sensor for in-ear headphones, through a highly stable internal reference discharge circuit, absoluteifies the relative diffusion time, thereby quantizing the discharge circuit composed of the external capacitor under test and the internal reference resistor, realizing high-speed, low-power multi-channel capacitance measurement.

The invention discloses a multi-mode fundus imaging system based on an FPGA and a real-time eye movement compensation method, and belongs to the field of medical imaging equipment. The system comprises an optical imaging and tracking module, an FPGA processing control module, a storage module and a system control and display unit. A unified frame-level clock management unit is arranged in the FPGA module and is used for synchronously scheduling scanning of the tracking light beam and the imaging light beam; eyeball displacement parameters are solved in real time through a hardware feature matching unit, and initial coordinates of cSLO and SD-OCT scanning galvanometers are corrected in a feedforward mode according to the parameters before each imaging frame or scanning block starts, so that frame-level eye movement compensation is achieved; meanwhile, preprocessing, displacement-based multi-frame alignment accumulation and image registration and fusion are performed on cSLO and SD-OCT data streams in parallel in a hardware pipeline. According to the invention, real-time synchronization, motion artifact suppression and high-precision fusion of multi-modal data are realized through full-hardware processing, and the imaging quality, the system response speed and the repeatability of follow-up scanning are remarkably improved.

The invention provides a digital atomic clock group management system and method, and the system comprises a plurality of atomic clocks, each atomic clock is connected with an ADC, each ADC is connected with the corresponding output end of the same multi-path power divider, each ADC is connected with a phase frequency detector, each phase frequency detector is connected with a stationary processor, and each stationary processor is connected with an analog-to-digital converter. And each stationary processor is connected with the corresponding input end of the same weighted averager. The output end of the weighted averager is connected with the loop filter, the loop filter is connected with the DAC controller, the DAC controller is connected with the DACs, each DAC is connected with the same adder circuit, and the adder circuit is connected with the VCXO. The clock group management unit comprises a scale algorithm module, a frequency modulation, phase modulation and drift modulation device, a loop parameter controller, a clock authorization manager, a working mode manager, a management mode selector, a clock group manager, a main clock selector, a channel controller, a weight controller and a phase difference and frequency difference demodulator. The system has the advantages of digitization, integration and expandability. The clock group management scheme and the time frequency scale algorithm are separated. According to the invention, high-precision generation of the satellite-borne VCXO voltage-controlled signal is realized.

This invention provides a communication device and a base station. The device includes a clock management resource pool and a power management resource pool. The device further includes at least one of the following: a baseband resource pool, a general computing resource pool, and a network switching processing resource pool. The baseband resource pool includes at least one baseband processing unit; the general computing resource pool includes at least one computing unit; the clock management resource pool includes at least one clock management unit; the network switching processing resource pool includes at least one network switching processing unit; and the power management resource pool includes at least one power management unit.

A clock frequency regulating circuit includes a memory circuit, a frequency detection circuit, and a clock management unit (CMU). The memory circuit is configured to store data according to an input clock, and to output the data according to an output clock. The frequency detection circuit is coupled with the memory circuit, and configured to detect the variation in a used amount of a storage space of the memory circuit and accordingly generate a frequency detection result. The CMU is coupled with the frequency detection circuit, and configured to regulate the frequency of the output clock according to the frequency detection result.

The application provides a clock management unit, a system on chip and an electronic device. The i-th group of low-power top interfaces of the interface selector is a first type of top interface, and the interface selector connects the i-th group of low-power top interfaces and the i-th group of low-power bottom interfaces in the interface selector; the i-th group of low-power top interfaces of the interface selector is a second type of top interface, and the interface selector connects the analog processor module and the i-th group of low-power distribution interfaces of the low-power distributor; and the clock controller performs clock management on the network on chip system according to the monitoring results of the low-power distributor, the target module and the analog processor module. When the processor module deployed on the top of the system on chip is increased or reduced, only the software configuration of the interface selector is needed, without changing the connection of the low-power distributor, without re-designing the code, and without re-dividing the chip layout, thereby reducing the overall design cost and improving the flexibility of clock management.