9 results about "Clock management unit" patented technology

A semiconductor device includes a retention circuit configured to retain a data value during a power gating operation, a non-retention circuit configured not to retain a data value during the power gating operation, a clock management unit (CMU) configured to provide a first operation clock to the retention circuit and provide a second operation clock to the non-retention circuit, and a power management unit (PMU) configured to provide a reference clock used to generate the first and second operation clocks to the CMU, generate a first isolation signal to permit a first signal to be output from the CMU, and generate a second isolation signal to permit a second signal to be output from the retention circuit and to permit a third signal to be output from the non-retention circuit.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronous circuits connected by a scan chain, a test data input (TDI) line, a test data output (TDO) line connected to the output terminal, a test access port (TAP) controller that controls operations of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal, and a test mode select (TMS) signal, a power management unit that controls power gating of the blocks, and a clock management unit that controls a clock signal supplied to the blocks. The TAP controller includes a first register that stores first data used to generate a first control signal that controls the power and clock management unit, the power and clock management unit controlling operations of the blocks based on the first control signal.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronization circuits connected by a scan-chain, a test data in (TDI) line, a test data out (TDO) line connected to the output terminal, a test access port (TAP) controller to control an operation of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal and a test mode select (TMS) signal, a power management unit to control power gating for the blocks, and a clock management unit to control a clock signal provided to the blocks. The TAP controller includes a first register that stores a first data for generating a first control signal controlling the power and clock management units, which control the operation of the blocks based on the first control signal.

The application provides a RT-THREAD resident system based on D1-H, which comprises a user module and a BIOS module, wherein the BIOS module comprises a hardware abstraction layer, an RTOS layer, and an API layer; the RTOS layer comprises an RT-Thread kernel, a thread management unit, a synchronization and communication unit, a clock management unit, and a memory management unit; the hardware abstraction layer comprises a driver construction, a software component, and a BootLoader; and the API layer comprises a driver component interface, a software component interface, and an RTOS service calling interface.The application has the advantages of reducing the programming threshold, improving the portability of application programs, and improving the compiling speed; the starting process after the RT-Thread is resident is analyzed, a resident test experiment is designed taking the synchronization and communication as an example, and the test result proves the feasibility of the RT-Thread resident.

This invention discloses a three-in-one sensor for in-ear headphones, comprising: a substrate; a bare die disposed on the top of the substrate, the bare die including a differential delay chain, a microprocessor, and a power and clock management unit, the differential delay chain being electrically connected to the microprocessor, the microprocessor being electrically connected to the power and clock management unit, a pin frame disposed at the top edge of the substrate, and further including pins, the pins being disposed on the top of the substrate through the pin frame. This three-in-one sensor for in-ear headphones, through a highly stable internal reference discharge circuit, absoluteifies the relative diffusion time, thereby quantizing the discharge circuit composed of the external capacitor under test and the internal reference resistor, realizing high-speed, low-power multi-channel capacitance measurement.

The application provides a clock management unit, a system on chip and an electronic device. The i-th group of low-power top interfaces of the interface selector is a first type of top interface, and the interface selector connects the i-th group of low-power top interfaces and the i-th group of low-power bottom interfaces in the interface selector; the i-th group of low-power top interfaces of the interface selector is a second type of top interface, and the interface selector connects the analog processor module and the i-th group of low-power distribution interfaces of the low-power distributor; and the clock controller performs clock management on the network on chip system according to the monitoring results of the low-power distributor, the target module and the analog processor module. When the processor module deployed on the top of the system on chip is increased or reduced, only the software configuration of the interface selector is needed, without changing the connection of the low-power distributor, without re-designing the code, and without re-dividing the chip layout, thereby reducing the overall design cost and improving the flexibility of clock management.

The application discloses a soft and hard cooperative optimization method of a large model multi-directory isolation scheduling architecture, and is based on an original multi-directory level isolation safety management and control architecture and a no-bypass full-process management and control module. The hardware layer realizes no-conflict autonomous optimization through on-chip firmware exclusive configuration permission. The on-chip integrated multi-dimensional sensor, the clock management unit and the storage controller complete advanced fault tolerance such as junction temperature timing compensation, firmware-level power gating and storage bad block mapping. The software layer completes full-dimensional lightweight performance optimization according to the multi-directory independent permission domain thread level isolation queue at the only compliance execution opportunity, and the software and hardware have no bus competition and deep cooperation.

The utility model provides a kind of programming frequency divider with dynamically adjustable frequency division ratio, comprising: first frequency division circuit, second frequency division circuit, third frequency division circuit, fourth frequency division circuit, buffer circuit, the first frequency division circuit, the second frequency division circuit, the third frequency division circuit and the fourth frequency division circuit, all be connected in the input end of the buffer circuit.The utility model has real-time programmable ability, can simultaneously output a variety of different frequency division ratio, meet the demand of a variety of clock frequency to complex digital system, in frequency synthesizer, clock management unit and communication system has extensive application prospect.