16 results about "Clock management unit" patented technology

A semiconductor device includes a retention circuit configured to retain a data value during a power gating operation, a non-retention circuit configured not to retain a data value during the power gating operation, a clock management unit (CMU) configured to provide a first operation clock to the retention circuit and provide a second operation clock to the non-retention circuit, and a power management unit (PMU) configured to provide a reference clock used to generate the first and second operation clocks to the CMU, generate a first isolation signal to permit a first signal to be output from the CMU, and generate a second isolation signal to permit a second signal to be output from the retention circuit and to permit a third signal to be output from the non-retention circuit.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronous circuits connected by a scan chain, a test data input (TDI) line, a test data output (TDO) line connected to the output terminal, a test access port (TAP) controller that controls operations of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal, and a test mode select (TMS) signal, a power management unit that controls power gating of the blocks, and a clock management unit that controls a clock signal supplied to the blocks. The TAP controller includes a first register that stores first data used to generate a first control signal that controls the power and clock management unit, the power and clock management unit controlling operations of the blocks based on the first control signal.

The invention relates to the technical field of electronic system time sequence control, in particular to a multi-system clock synchronization method based on a low-frequency calibration clock, which is characterized in that a main system adopts a high-stability clock source and simultaneously generates a high-frequency data clock and the low-frequency calibration clock of which the frequency is less than one thousandth of that of the data clock through a clock management unit; the characteristics of strong anti-interference and high transmission quality of the low-frequency clock are utilized, and the low-frequency clock is sent to each slave system through the optimized clock distribution network. Each slave system extracts a low-frequency calibration clock through a clock recovery circuit, a high-precision time interval measurement unit is adopted to measure the time difference between a local clock and the calibration clock, and the measurement precision and stability are improved through digital signal processing. And each slave system inputs the time difference as a control quantity into a digital regulation system, dynamically regulates the phase of a local clock, and judges a synchronous locking state through a locking state detection mechanism, thereby realizing high-precision, long-term and stable clock synchronization among multiple systems.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronization circuits connected by a scan-chain, a test data in (TDI) line, a test data out (TDO) line connected to the output terminal, a test access port (TAP) controller to control an operation of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal and a test mode select (TMS) signal, a power management unit to control power gating for the blocks, and a clock management unit to control a clock signal provided to the blocks. The TAP controller includes a first register that stores a first data for generating a first control signal controlling the power and clock management units, which control the operation of the blocks based on the first control signal.

The invention discloses a multi-rate controllable 1553 bus controller module, which belongs to the field of avionics and data buses and comprises a 1553 protocol processing module, a Manchester encoder, a Manchester decoder, a sending channel, a receiving channel and an internal clock management unit. The internal clock management unit generates a core clock signal corresponding to a target communication rate according to a signal input by the external rate control pin; and the Manchester encoder / decoder performs data encoding and decoding by using the core clock signal, so that the adjustable switching of the communication rate among 1Mbps, 2Mbps and 4Mbps is realized. Flexible configuration of the communication rate is achieved through hardware pin control, the problems that a traditional 1553 controller is fixed in rate and lack of flexibility are solved, and the controller has the advantages of being high in compatibility, low in cost and high in integration degree.

This application discloses a clock configuration system and method. It includes: a clock generation circuit and a communication module; the communication module includes a configuration unit, a clock management unit, and a communication circuit; the clock generation circuit is connected to the clock management unit in the communication module; the clock management unit is connected to the communication circuit; the communication circuit is connected to the configuration unit; the clock generation circuit provides a reference clock to the communication module; the configuration unit configures the line rate and data bit width of data transmission in the communication circuit, determines a clock division factor based on the line rate and the data bit width, and configures the clock division factor in the clock management unit; the clock management unit determines the operating clock frequency based on the reference clock and the clock division factor, and provides the operating clock frequency to the communication circuit. Determining the operating clock frequency by configuring the line rate and data bit width reduces the complexity of clock configuration in the communication module.

The application provides a RT-THREAD resident system based on D1-H, which comprises a user module and a BIOS module, wherein the BIOS module comprises a hardware abstraction layer, an RTOS layer, and an API layer; the RTOS layer comprises an RT-Thread kernel, a thread management unit, a synchronization and communication unit, a clock management unit, and a memory management unit; the hardware abstraction layer comprises a driver construction, a software component, and a BootLoader; and the API layer comprises a driver component interface, a software component interface, and an RTOS service calling interface.The application has the advantages of reducing the programming threshold, improving the portability of application programs, and improving the compiling speed; the starting process after the RT-Thread is resident is analyzed, a resident test experiment is designed taking the synchronization and communication as an example, and the test result proves the feasibility of the RT-Thread resident.

This invention discloses a three-in-one sensor for in-ear headphones, comprising: a substrate; a bare die disposed on the top of the substrate, the bare die including a differential delay chain, a microprocessor, and a power and clock management unit, the differential delay chain being electrically connected to the microprocessor, the microprocessor being electrically connected to the power and clock management unit, a pin frame disposed at the top edge of the substrate, and further including pins, the pins being disposed on the top of the substrate through the pin frame. This three-in-one sensor for in-ear headphones, through a highly stable internal reference discharge circuit, absoluteifies the relative diffusion time, thereby quantizing the discharge circuit composed of the external capacitor under test and the internal reference resistor, realizing high-speed, low-power multi-channel capacitance measurement.

The invention discloses a multi-mode fundus imaging system based on an FPGA and a real-time eye movement compensation method, and belongs to the field of medical imaging equipment. The system comprises an optical imaging and tracking module, an FPGA processing control module, a storage module and a system control and display unit. A unified frame-level clock management unit is arranged in the FPGA module and is used for synchronously scheduling scanning of the tracking light beam and the imaging light beam; eyeball displacement parameters are solved in real time through a hardware feature matching unit, and initial coordinates of cSLO and SD-OCT scanning galvanometers are corrected in a feedforward mode according to the parameters before each imaging frame or scanning block starts, so that frame-level eye movement compensation is achieved; meanwhile, preprocessing, displacement-based multi-frame alignment accumulation and image registration and fusion are performed on cSLO and SD-OCT data streams in parallel in a hardware pipeline. According to the invention, real-time synchronization, motion artifact suppression and high-precision fusion of multi-modal data are realized through full-hardware processing, and the imaging quality, the system response speed and the repeatability of follow-up scanning are remarkably improved.

The invention provides a digital atomic clock group management system and method, and the system comprises a plurality of atomic clocks, each atomic clock is connected with an ADC, each ADC is connected with the corresponding output end of the same multi-path power divider, each ADC is connected with a phase frequency detector, each phase frequency detector is connected with a stationary processor, and each stationary processor is connected with an analog-to-digital converter. And each stationary processor is connected with the corresponding input end of the same weighted averager. The output end of the weighted averager is connected with the loop filter, the loop filter is connected with the DAC controller, the DAC controller is connected with the DACs, each DAC is connected with the same adder circuit, and the adder circuit is connected with the VCXO. The clock group management unit comprises a scale algorithm module, a frequency modulation, phase modulation and drift modulation device, a loop parameter controller, a clock authorization manager, a working mode manager, a management mode selector, a clock group manager, a main clock selector, a channel controller, a weight controller and a phase difference and frequency difference demodulator. The system has the advantages of digitization, integration and expandability. The clock group management scheme and the time frequency scale algorithm are separated. According to the invention, high-precision generation of the satellite-borne VCXO voltage-controlled signal is realized.

The application provides a clock management unit, a system on chip and an electronic device. The i-th group of low-power top interfaces of the interface selector is a first type of top interface, and the interface selector connects the i-th group of low-power top interfaces and the i-th group of low-power bottom interfaces in the interface selector; the i-th group of low-power top interfaces of the interface selector is a second type of top interface, and the interface selector connects the analog processor module and the i-th group of low-power distribution interfaces of the low-power distributor; and the clock controller performs clock management on the network on chip system according to the monitoring results of the low-power distributor, the target module and the analog processor module. When the processor module deployed on the top of the system on chip is increased or reduced, only the software configuration of the interface selector is needed, without changing the connection of the low-power distributor, without re-designing the code, and without re-dividing the chip layout, thereby reducing the overall design cost and improving the flexibility of clock management.

The application discloses a soft and hard cooperative optimization method of a large model multi-directory isolation scheduling architecture, and is based on an original multi-directory level isolation safety management and control architecture and a no-bypass full-process management and control module. The hardware layer realizes no-conflict autonomous optimization through on-chip firmware exclusive configuration permission. The on-chip integrated multi-dimensional sensor, the clock management unit and the storage controller complete advanced fault tolerance such as junction temperature timing compensation, firmware-level power gating and storage bad block mapping. The software layer completes full-dimensional lightweight performance optimization according to the multi-directory independent permission domain thread level isolation queue at the only compliance execution opportunity, and the software and hardware have no bus competition and deep cooperation.

The utility model provides a kind of programming frequency divider with dynamically adjustable frequency division ratio, comprising: first frequency division circuit, second frequency division circuit, third frequency division circuit, fourth frequency division circuit, buffer circuit, the first frequency division circuit, the second frequency division circuit, the third frequency division circuit and the fourth frequency division circuit, all be connected in the input end of the buffer circuit.The utility model has real-time programmable ability, can simultaneously output a variety of different frequency division ratio, meet the demand of a variety of clock frequency to complex digital system, in frequency synthesizer, clock management unit and communication system has extensive application prospect.

The invention belongs to the technical field of precision laser processing, and particularly relates to a multi-channel super-synchronous control femtosecond laser processing system and method, and the system comprises a radio frequency current reference clock source; at least one femtosecond laser generator; at least one high-speed scanning system; a super synchronous controller; the super-synchronous controller comprises a clock management unit used for locking the radio frequency current reference clock source and generating a global synchronous clock signal; the delay control unit is used for carrying out programmable delay on the global synchronous clock signal to generate planned laser triggering time; and the drift compensation unit is used for calculating the time sequence drift compensation amount of the system in real time. According to the multi-channel femtosecond laser processing system, high-precision synchronous control of the multi-channel femtosecond laser processing system can be realized through unified global clock reference, high-precision programmable delay, real-time drift compensation and bidirectional predictive synchronous decision, time sequence drift is effectively inhibited, space-time conflicts among channels are avoided, and processing consistency and efficiency are improved.

The application relates to a high-speed data synchronous acquisition and transmission system suitable for a satellite communication MIMO system, the system comprising two acquisition and transmission subcards and a clock management unit; the acquisition and transmission subcard comprises a multichannel ADC acquisition unit and a multichannel DAC refreshing unit; the multichannel ADC acquisition unit of the acquisition and transmission subcard sends the acquired data to an FPGA for processing through a JESD204B interface, and then forwards the data through an optical module; the multichannel DAC refreshing unit of the acquisition and transmission subcard sends the data received by the optical module to the FPGA for processing, and then sends the data to a DAC through the JESD204B interface for interpolation filtering and IQ conversion and then refreshes and outputs to a radio frequency front end; the clock management unit utilizes the trigger signal of a clock chip to realign the phases of the device clock and the reference clock in each power-on process, so that the inter-board synchronization is realized. The system can improve the synchronization performance and reduce the power consumption.

The invention relates to the technical field of display control, in particular to an FPGA-based display panel adaptive time sequence kernel generation method and system, the FPGA sends a detection signal sequence containing multiple groups of candidate time sequences to a target panel according to a default initial time sequence, and collects a physical resolution identifier and an interface type identifier fed back by the panel; the parameter resolving state machine maps the identifier into a standardized display driving parameter through an internal lookup table, directly configures counter parameters of the line field synchronizing signal generator and the clock management unit, and generates hardware sequential logic matched with the panel; the FPGA drives the panel according to the hardware time sequence logic and continuously monitors a synchronous locking indication signal returned by the panel, and parameter solidification or time sequence reconfiguration triggering is determined according to the locking state. According to the method, full-hardware active detection, closed-loop verification and self-adaptive adjustment of display time sequence parameters are realized, and the method has high robustness and fault-tolerant capability.