103 results about "Clock management unit" patented technology

A system-on-chip includes a symmetric multi-processor including a plurality of cores, each configured to operate in a high performance operating mode and a low performance operating mode. The system-on-chip further includes a clock management unit configured to provide an operating clock signal to the symmetric multi-processor, a state management unit configured to monitor operating states of the cores, a temperature management unit configured to monitor a temperature of the symmetric multi-processor, and a symmetric multi-processor control unit configured to determine the operating clock signal and the operating states of the cores based on a workload of the symmetric multi-processor. The symmetric multi-processor control unit is further configured to differentially determine a maximum operating clock frequency for the cores based on the temperature and the operating states of the cores, which indicate a quantity of cores that are currently in operation.

The invention discloses a multichannel parallel acquisition system with a multi-device asynchronous reset recognition correction function. In N ADC and FPGA modules of the multi-channel parallel acquisition system, the first FPGA module sends a reset signal according to a system reset start command to complete the reset operation of the ADC and the DCM, thereby generating a stable data work clock CCLK1 in the FPGA; each of the second to the N-th FPGA modules contains a synchronous recognition module and a reset control module; the synchronous recognition module is used for adjusting a delay value of the data work clock of the former FPGA module, and synchronously recognizing the data work clocks of the current FPGA and the former FPGA through the adoption of a de-serializer and a sequence detection module, using the delay value in synchronization as the time interval, and then adjusting the delay value from the reset signal to the corresponding ADC and the clock management unit according to the time interval, thereby completing the multi-device asynchronous reset recognition correction. Through the adoption of the system disclosed by the invention, the reset accuracy can be guaranteed; therefore, the phase relation of the multi-channel data work clock after each synchronous resetting is determined.

The invention discloses a clock synchronous device and a system for Field Programmable Gate Array (FPGA) prototype test plate piling, wherein the clock synchronous device for FPGA prototype test plate piling comprises a clock chip, a master control chip, at least one slave FPGA chip and at least one high-speed connector, wherein the main control chip further comprises a first data selector, a second data selector, a clock management unit and a global clock buffer. The master chip comprises a local clock input pin, a piling clock input pin, a selective signal input pin, a selective signal input pin, a feedback clock input pin, a slave FPGA clock synchronization clock signal output pin, a feedback clock synchronization clock signal output pin and a high-speed connector synchronization clock signal output pin. The clock synchronous device and the system for FPGA prototype test plate piling utilize a master control chip inner lock phrase loop to feed back, the time delay of a master control chip inner routing is equal to the corresponding routing time delay of an outer PCB plate, and the clocks which are output to all slave FPGA chip are enabled to achieve synchronization.

The invention discloses a mobile terminal communication processor with environment perception and reconfigurable ability, comprising a reconfigurable physical layer unit, a clock manager, a time control unit, a microcontroller, a storage unit, a protocol and perception processing unit, a bus bridge contact, a boundary scan interface, an oscillator, a power management circuit, a high-speed interface for multiple architectures and a bus bridge contact. Datum from exterior are received and self-adaptive transceived by the reconfigurable physical layer unit based on oscillation frequency providedby the oscillator and delivered to the external bus after modulated. The processed datum are delivered to the external bus and sent out from the unit. The invention has the advantages that external environment can be sensed and self-adaptive adjustment of a modulation and demodulation technique and a radio frequency amplifier can be realized; the communication between a non heterogeneous and a heterogeneous network is supported; seamless communication with chips of other protocols in a wide area network can be carried out, and the cost of realization is reduced on basis of improved integral performance of the processor.

The invention discloses a method for transmitting image data of a multi-channel high-speed line-frequency-variable linear array CCD (charge coupled device), and relates to the field of transmission of image data of aerospace and aviation CCD cameras. The method includes steps that a digital phase-locked loop clock management unit creates a relation between frequency of a pixel transfer clock and frequency of a TLK2711 transmission clock according to the quantity of transmission channels of the CCD, the pixel transfer clock and the quantity of transmission channels of TLK2711 devices; the TLK2711 devices create a reliable and stable transmission link for transmitting and receiving the image data; and multi-channel image data fusion transmission and line signal and image data fusion transmission units start to fuse the multi-channel data into one channel of data and transmit the channel of data to the TLK2711 devices after the transmission link is stable, and the TLK2711 deserializer transmits the channel of data to a receiving FPGA (field programmable gate array) processor. The method has the advantage that cables of an aerospace and aviation remote-sensing camera data transmission system are greatly reduced.

The invention discloses a SoC (system on chip) dynamic voltage frequency scaling method with foresight and belongs to the field of chip design and application. The invention aims to solves the delay problem of dynamic voltage frequency scaling in a master control chip of a mobile device, realize the reduction of power consumption whiling guaranteeing the CPU (central processing unit) performance and improve the user experience. Compared with a traditional scaling method, the CPU dynamic voltage frequency scaling of a SoC is with foresight and is realized on the basis of the following principle: a capacitive screen controller is integrated to the SoC; the capacitive screen controller adopts the digital-analog mixed signal design, not only has the functions of digital-analog conversion, coordinate output and multipoint touch control of a traditional capacitive screen controller, but also has the functions of touch strength detection, touch frequency statistical and touch length statistical; then a DVFS (dynamic voltage frequency scaling) module outputs a CPU voltage and frequency with foresight through judgment according to the parameters and the load situation of the operating system, and the CPU voltage and frequency are also output to a power management unit and a clock management unit of the SoC for appropriate scaling.

A method of performing a dynamic voltage and frequency scaling operation comprises controlling a clock management unit (CMU) to predict an operating state of a central processing unit (CPU) and to provide operating frequency information to a power management integrated circuit (PMIC) based on the predicted operating state of the CPU, the operating frequency information indicating a change of an operating frequency of an application processor, and controlling the PMIC to change an operating voltage of the application processor based on the operating frequency information provided from the clock management unit.

The purpose of the invention is to provide a base-band device based on software radio. The technical scheme of the invention includes two paths of 70M uplink sending channels, two paths of 70M downlink reception channels, two paths of PSK reception channels, two paths of PSK sending channels, LVTTL level input and output interfaces for test, a clock management unit, a data processing module, a PCI interface module, a CPLD logic module, an expanding RAM module, digital up conversion/down conversion modules, a FLASH module and a power supply module. The base-band device is connected to a CPCI computer through an PCI interface chip. A PCI bus protocol is converted to a local bus protocol. Address decoding is carried out on local bus signals output by the PCI interface chip through CPLD. A PCI bus finishes accessing the interface through the CPLD, and finishes downloading programs, so that the computer can update firmware programs through the PCI interface. The multifunctional communication of multi-band frequency, multi-mode, multi-channel, multi-speed, and multi-protocol is realized, and thus a good and flexible software radio system platform is constructed.

The invention discloses a system for collecting the motion information of a lift car. The system for collecting the motion information of the lift car comprises an acceleration module, a Flash chip, a real-time clock management unit and a single-chip microcomputer MCU, wherein the acceleration module completes collection of original data once within a certain time and sum and average the data of a specified number of points, and the average is used as a sample point; the Flash chip stores the statistics data of a lift; the real-time clock management unit provides a clock interface for the system; and the single-chip microcomputer MCU analyzes the motion information of the lift car according to acceleration information. According to analysis of the single-chip microcomputer MCU, during upward (downward) movement, when the negative (positive) amplitude value of the sample point exceeds the upward (downward) movement threshold, negative (positive) acceleration gradual increase is determined, and the lift moves upwards (downwards) and accelerates at the moment; then, whether the negative (positive) amplitude value of the sample point exceeds the upward (downward) movement threshold or not is judged, if yes, positive (negative) acceleration gradual change is determined, and the lift moves upward (downward) and decelerates at the moment; and finally, whether the lift meets a stopping condition or not is judged, and if yes, one upward (downward) movement process is ended.

The application discloses a waveform generating device and method. The waveform generating device comprises a waveform generating management module based on a FPGA (Field Programmable Gate Array) and a peripheral circuit expansion module. The waveform generating management module comprises a core management unit, a data transmission control unit, a storage control unit, a system clock management unit and a data rate acceleration unit, wherein the data transmission control unit is connected to the core management unit; the storage control unit is connected to the core management unit; the system clock management unit is connected to the core management unit; and the data rate acceleration unit is used for outputting waveform data at an accelerated output rate. The peripheral circuit expansion module comprises a data transmission bus control unit, a storage unit, a digital-analog conversion unit and an output clock management unit. The invention is high in flexibility and can achieve a high-speed digital waveform generation and control function.

The embodiment of the invention discloses a time synchronization method, a time synchronization device and a time synchronization system. The time synchronization method comprises the following stepsthat: a client acquires clock information; and the client realizes time synchronization with a server according to the clock information. The client comprises a clock information acquisition unit anda clock management unit, wherein the clock information acquisition unit is used for acquiring the clock information, and the clock management unit is used for realizing the time synchronization with the server according to the clock information acquired by the clock information acquisition unit. In the embodiment of the invention, the client acquires the clock information and realizes the time synchronization with the server according to the clock information, so the time of the client and the time of the server can be kept synchronous so as to keep the time of a user and the time of the server synchronous and further strengthen the experience of the user.

The invention relates to a communication bus experimental facility; for solving the defect that the current IIC bus is complex in debugging and cannot ensure safety and accuracy when in data transmission, the invention provides an IIC bus experimental facility debugged by a serial port, which can visually check through a command editing window of an upper computer or modifying data of a register of external equipment, and visually display the obtained return value at a PC end. According to the communication bus experimental facility, the original advantages of IIC is ensured, and furthermore, operators can more conveniently and clearly use an IIC protocol to debug a test chip. Therefore, the technical scheme adopted by the invention includes that the IIC bus experimental facility debugged by the serial port includes an upper computer UART interface controller, a protocol converting unit, an IIC bus interface controller and a clock management unit. The IIC bus experimental facility debugged by the serial port is mainly applied to bus tests.

The invention discloses an FPGA clock signal output circuit, comprising a clock management unit and a global buffer, wherein a clock signal generated by the clock management unit is distributed by the global buffer; moreover, the FPGA clock signal output circuit also comprises a trigger unit and a selector, the end of the clock signal of the trigger unit is connected with the output end of the global buffer, a data input signal of the trigger unit is a constant logic signal, the trigger unit provides a positive output signal and a negative output signal to the end of the input signal of the selector, the control input end of the selector is connected with the end of the clock signal outputted by the clock management unit, and the selector outputs the clock signal to an output pin of the FPGA. The FPGA clock signal outputted by the circuit reduces the delay, and lowers the negative influence of the external load on an internal clock tree of the FPGA.

The invention discloses a clock synchronization method for a multiport synchronization Ethernet device, which comprises the following steps: slave ports and master ports are determined according to the clock resumed from each port and real time clock (RTC) of boards is used for synchronizing the RTC of each master port on the boards after using the clock of the slave ports to synchronize the clock of the boards; slave boards and master boards are determined according to the RTC of each board and the clock of the slave boards is used for synchronizing the RTC of the device and the RTC of the device is transmitted to the boards; the boards synchronize the RTC of the boards according to the RTC of the device and the RTC of the boards after the synchronization is used for synchronizing the clock of each port on the boards. Meanwhile, the invention discloses a clock synchronization system of the multiport synchronization Ethernet device, which comprises a port clock resuming unit, a board level CPU, a board level clock management unit, a device level CPU and a device level clock management unit. The utilization of the invention can realize the synchronization of all clocks of the multiport synchronization Ethernet device.

The invention provides a SOC chip bus dynamic multi-level frequency adjustment circuit and method. The circuit comprises a clock generation unit, a clock management unit, a bus frequency mapping tablestorage unit, master device monitoring control units, bus request blocking units and a bus transmission state monitoring unit. The bus frequency mapping table storage unit stores a multi-level bus frequency mapping table which presets the bus frequency corresponding to working scenes of the master devices. The clock management unit receives a working state of each master device sent from each master device monitoring control unit and an idle state of the entire bus sent from the bus transmission state monitoring unit, and controls relevant units such as the clock generation unit to complete abus dynamic frequency conversion process according to the working state of the master device, or controls the clock generation unit to turn off the clock of the entire bus according to the idle stateof the entire bus. Thus, the frequency of the bus can be adjusted dynamically in time to adapt to the current bus load, and the best energy efficiency ratio can be obtained.

The invention discloses a clock management unit of a RFID (radio frequency identification) tag chip which can reduce power consumption and peak power consumption of the RFID tag chip. The clock management unit of the RFID tag chip comprises a main state machine, a counter and a plurality of gating clock units, wherein the main state machine analyzes the state of each functional unit of the tag chip, judges moments when a plurality of functional units are woken at the same time and a plurality of operations are executed at the same time, and further judges which functional units are still unnecessary, sets a clock enable signal of the functional units which can be stopped to zero, and separates the operations of the plurality of functional units which are independent to each other and enable registers to turn over synchronously; the counter is used for helping control on the input signal, and helping the main state machine to move up some operations of the functional units which are independent to each other and enable registers to turn over synchronously for several clocks and delay some operations of the same for several clocks; the gating clock units are used for instantiating the enable signals and system clock signals of each functional unit, and taking the instantiated output clock as a control clock for controlling the action of each functional unit.

The invention provides an online monitoring and positioning system for local discharge of a high-voltage cable. The online monitoring and positioning system comprises a plurality of sensors used for collecting discharge signals in different positions of the high-voltage cable, a plurality of monitoring terminals connected with the sensors, a network switch connected with the monitoring terminals and a discharge monitoring concentrator connected with the network switch. The monitoring terminals comprise a data acquisition unit connected with the sensors, a clock management unit, a plurality of network interfaces connected with the clock management unit, and a control processing unit connected with the data acquisition unit and the clock management unit. The control processing unit is connected with the network switch, and the monitoring terminals are connected via the network interfaces. The control processing unit is used for controlling the clock management unit by synchronizing a clock of the connected monitoring terminals via high-precision clock synchronization based on the IEEE 1588 protocol on a hardware time stamp. Therefore, the precision of synchronization of the clock of the connected monitoring terminals is high. By adopting the online monitoring and positioning system for local discharge of the high-voltage cable, the precision of finally obtained discharge source location data is high.

The invention discloses a MicroTCA system and a clock synchronization method and solves the problem that the introduction of a clock source is limited in the prior art. The MicroTCA system at least includes an MCH and a plurality of AMC cards connected with the MCH through a back board. The MCH includes a clock unit which is used for outputting a system synchronized clock to a predetermined clock input port of an AMC card through a predetermined output port, and at least one clock card connected with the MCH through a back board. The clock card is provided with an extra clock output end, an extra clock input end is arranged on the AMC card, the extra clock output end of the clock card outputs an extra clock to the extra clock input end of the AMC card through an extra differential line on the back board, and the AMC card is provided with a clock management unit which selectively uses the predetermined clock output by the MCH and/or the extra clock output by the AMC clock card. A special clock distribution board card is arranged inside a cabinet to support the multi-standard system clock synchronization to be suitable for a multi-standard combined scene, and a switching board MCH and an AMC board card are not needed to be redesigned. Therefore, the reusability of hardware is improved, the product development period is shortened, and the cost is reduced. Clock configuration double redundancy is allowed to improve the system reliability.

The invention provides a clock management unit, which comprises a first trigger, a second trigger, a clock gate and an AND gate, wherein the first trigger comprises a first D terminal for receiving reset signals, a first clock terminal for receiving clock signals, and a first output terminal connected to a second D terminal of the second trigger; the second trigger comprises a second D terminal connected to a first output terminal of the first trigger, a second clock terminal for receiving clock signals and a second output terminal connected to an enable terminal of the clock gate; the clock gate comprises the enable terminal, a clock terminal for receiving clock signals, and an effective clock terminal connected to an external circuit; the clock gate provides the clock signals for the external circuit through the effective block terminal according to the output of the second output terminal of the second trigger; and the AND gate provides the reset signals for the first D terminal of the first trigger according to enable signals. Therefore, in at least two periods of the clock signals after the external circuit receives the reset signals, no clock signals are provided for the external circuit.

The invention discloses a digital receiver module, a signal processing method thereof, and a radio frequency card wiring method. The digital receiver module comprises a signal collection unit, a clock management unit, a synchronous speed reduction processing unit, and a signal processing unit. The clock management unit supplies a superspeed sampling clock for the signal collection unit, and provides a synchronous speed reduction processing clock for the synchronous speed reduction processing unit, wherein the synchronous speed reduction processing clock is coherent with the sampling clock. The signal collection unit achieves the sampling and single-bit quantification of a radio-frequency input signal, and outputs superspeed single-bit collection data. The synchronous speed reduction processing unit enables one-path superspeed serial data to be converted into 16-path high-speed parallel data through first level speed reduction processing. The signal processing unit provides an on-line adjustable time delay code value in the synchronous speed reduction processing unit, and completes the real-time processing of high-speed parallel data. The invention also discloses the signal processing module for the digital receiver module, and the radio frequency card wiring method for the digital receiver module.

The invention relates to a device for real-time image statistics with a histogram and a method for implementing the same. The device comprises a video decoding unit, a programmable logic gate array, aprogram storage, a clock management unit, a resetting management unit and a power supply management unit, wherein the video decoding unit receives, filters, amplifies and digitalizes an original image signal to generate video data; the programmable logic gate array receives video data output by the video decoding unit and performs the statistics of the video data with the histogram; the program storage stores the application programs of the programmable logic gate array; the clock management unit provides required clocks for the programmable logic gate array and the video decoding unit; the resetting management unit provides a resetting signal for the programmable logic gate array; and the power supply management unit provides required power supply for the programmable logic gate array and units. The method comprises that: the video decoding unit receives, filters, amplifies and digitalizes the original image signal to generate the video data; and the programmable logic gate array performs the statistics of the video data with the histogram to obtain a result. The device and the method have the advantages of quickness, high integration level, low cost, and the like.

The invention relates to a realization method of a double-passage real-time relevance machine on an FPGA (field programmable gate array) chip. According to the realization method, a PCI (peripheral component interconnect) local end interface core, a DMA (direct memory access) interface control logic unit, a 16K depth FIFO (first in first out) unit, a DSP (digital signal processor) core, an ADC (analog to digital converter) control logic unit and a clock management unit are adopted, wherein the DSP core comprises the following processing flow processes that ADC sampling data enters a double-passage FFT (fast fourier transform) core after delay compensation and enters a self relevance and mutual relevance operation unit through passage data separation and data cutting, and finally, the ADC sampling data enters an integrator for integration and enters the FIFO unit. Therefore, the signal to noise ratio of the mutual relevance can be improved, meanwhile, much chip resource space is saved, and the high-speed operation is realized.

The invention provides a low-power-consumption FPGA (Field Programmable Gate Array) partially reconfigurable method and a low-power-consumption FPGA partially reconfigurable device. According to the method and device provided by the scheme of the invention, the invalid power consumption of the FPGA static logic region is effectively reduced by combining the logic cutting and reconstruction switching technology of the FPGA static logic region and the clock frequency real-time adjustment mechanism of the memory control interface dormancy and dynamic clock management unit; and meanwhile, the problems of heat dissipation and stability caused by long-term working of the static logic region in a high-frequency state are further avoided.

The invention relates to a heterogeneous multi-core processor power consumption control device and method. The device comprises n CPUs and m IPs, and further comprises a clock management unit, a power source management unit and a clock control unit, wherein n and m are integers larger than 1. The power source management unit comprises m power source interfaces which control power sources of the connected IPs to be switched on or off respectively according to control commands of the clock management unit. The clock control unit comprises n+m clock gating modules, and each clock gating module is connected with one CPU or one IP, and the clock gating modules control clocks of the connected CPUs or the IPs to be switched on or off respectively according to control commands of the clock management unit. Each CPU can control the clock management unit to send the control commands to any power source interface or any clock gating clock module. By means of the scheme, power consumption of a chip and design difficulty of the chip can be reduced.