43 results about "Clock management unit" patented technology

A semiconductor device includes a retention circuit configured to retain a data value during a power gating operation, a non-retention circuit configured not to retain a data value during the power gating operation, a clock management unit (CMU) configured to provide a first operation clock to the retention circuit and provide a second operation clock to the non-retention circuit, and a power management unit (PMU) configured to provide a reference clock used to generate the first and second operation clocks to the CMU, generate a first isolation signal to permit a first signal to be output from the CMU, and generate a second isolation signal to permit a second signal to be output from the retention circuit and to permit a third signal to be output from the non-retention circuit.

A semiconductor device includes a retention circuit configured to retain a data value during a power gating operation, a non-retention circuit configured not to retain a data value during the power gating operation, a clock management unit (CMU) configured to provide a first operation clock to the retention circuit and provide a second operation clock to the non-retention circuit, and a power management unit (PMU) configured to provide a reference clock used to generate the first and second operation clocks to the CMU, generate a first isolation signal to permit a first signal to be output from the CMU, and generate a second isolation signal to permit a second signal to be output from the retention circuit and to permit a third signal to be output from the non-retention circuit.

The present invention discloses a physical construction method suitable for meeting triple modular redundancy. In the layout stage, a customized design is adopted for the clock management unit. The three registers in the same group are effectively controlled through scripts during implementation. Since the existing triple modular registers increase the clock delay and have the characteristic of large delay differences under different process corners in advanced processes, the difficulty of timing convergence is reduced, and the design efficiency is effectively accelerated. Finally, the triple modular clock phase difference check is completed by using the clock length comparison method. The present invention can ensure that the single event effect is effectively improved while ensuring that the triple modular design quickly meets the design specifications. The present invention has the advantages of simple process, strong operability, and fast timing convergence speed, and can meet other tape-out sign-off conditions.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronous circuits connected by a scan chain, a test data input (TDI) line, a test data output (TDO) line connected to the output terminal, a test access port (TAP) controller that controls operations of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal, and a test mode select (TMS) signal, a power management unit that controls power gating of the blocks, and a clock management unit that controls a clock signal supplied to the blocks. The TAP controller includes a first register that stores first data used to generate a first control signal that controls the power and clock management unit, the power and clock management unit controlling operations of the blocks based on the first control signal.

The invention relates to the technical field of electronic system time sequence control, in particular to a multi-system clock synchronization method based on a low-frequency calibration clock, which is characterized in that a main system adopts a high-stability clock source and simultaneously generates a high-frequency data clock and the low-frequency calibration clock of which the frequency is less than one thousandth of that of the data clock through a clock management unit; the characteristics of strong anti-interference and high transmission quality of the low-frequency clock are utilized, and the low-frequency clock is sent to each slave system through the optimized clock distribution network. Each slave system extracts a low-frequency calibration clock through a clock recovery circuit, a high-precision time interval measurement unit is adopted to measure the time difference between a local clock and the calibration clock, and the measurement precision and stability are improved through digital signal processing. And each slave system inputs the time difference as a control quantity into a digital regulation system, dynamically regulates the phase of a local clock, and judges a synchronous locking state through a locking state detection mechanism, thereby realizing high-precision, long-term and stable clock synchronization among multiple systems.

The present disclosure relates to a test mode control system capable of testing a clock component that configures a clock management unit and generating a test clock by driving the clock component that generates a functional clock and a system-on-chip including the same. The test mode control system according to an embodiment of the present disclosure includes: a test mode controller that transmits a clock control signal to a clock source that configures a high-speed domain of a clock management unit in a test mode; and a test multiplexer that transfers a clock control signal input from the test mode controller to the clock source in the test mode and transfers a clock control signal input from a clock control circuit corresponding to the clock source to the clock source in a functional mode.

The invention relates to a system and a method for designing a clock management unit in a code-free mode, which can be used for testing a clock component and generating a test clock based on a functional clock path. The system includes a memory to store instructions, and a processor to execute the instructions. The instructions include generating a clock instance including a clock source block, a clock control signal block, and a test multiplexer block; generating a test mode controller instance containing the test data register block; setting connection between the two; and instructions to generate hardware code.

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronization circuits connected by a scan-chain, a test data in (TDI) line, a test data out (TDO) line connected to the output terminal, a test access port (TAP) controller to control an operation of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal and a test mode select (TMS) signal, a power management unit to control power gating for the blocks, and a clock management unit to control a clock signal provided to the blocks. The TAP controller includes a first register that stores a first data for generating a first control signal controlling the power and clock management units, which control the operation of the blocks based on the first control signal.

The invention discloses a semiconductor system and a reset work clock control method thereof, which can input a reference clock slower than a functional clock to a clock work unit through a clock multiplexer when a reset work or a reset release work is performed, thereby easily capturing a reset timing. A semiconductor system according to an embodiment of the present invention comprises: a clock management unit that operates according to a functional clock and generates and outputs an output functional clock for operation of the semiconductor system; and a power management unit that performs power management of the semiconductor system including a reset operation or a reset release operation. The clock management unit comprises a clock working unit which works according to the function clock in a working mode and generates and outputs the output function clock; and the clock multiplexer performs different selections on input clocks input to the clock working unit and outputs the input clocks to the clock working unit in the working mode and the reset mode.

An electronic device includes a clock management unit configured to generate a clock signal, an intellectual property (IP) device configured to receive the clock signal and is configured to perform a task according to the clock signal in an active state, a first counter configured to count cycles of the clock signal while the IP device is in the active state, and is configured to generate a first count, and a frequency controller configured to control the clock management unit to change a frequency of the clock signal when the first count reaches a first reference count.

The invention relates to the technical field of vehicles, in particular to a method and a device for generating a controller of a multi-chip Flash memory and electronic equipment. The method comprises the following steps: acquiring a control parameter written based on a SpinalHDL programming language; wherein the control parameters comprise a first configuration parameter of a register bus, a second configuration parameter of a data reading bus, third configuration parameters of a register unit, a clock management unit, a control unit and a plurality of driving units in the controller, and fourth configuration parameters of at least one Flash memory controlled by the controller; generating a control circuit of the controller based on the control parameter; wherein the control circuit comprises a register bus, a data reading bus and a controller, the controller comprises a register unit, a clock management unit, a control unit and a plurality of driving units, and one driving unit corresponds to one Flash memory.

To provide an image sensor that minimizes the delay of a clock supply by reducing the electric power, and an operation method for the same.SOLUTION: An image sensor includes a plurality of clock consumers (CCs), a plurality of block clock management units (BCMUs), and a top clock management unit (TCMU). Each BCMU transmits a second clock demand signal to TCMU in response to a first clock demand signal received from at least one CC among the CCs. TCMU transmits each clock response signal in accordance with each second clock demand signal. TCMU transmits a second clock signal to each BCMU through a channel formed in transmission and reception of the second clock demand signal and the clock response signal. While the second clock signal is transmitted through the channel, each BCMU transmits the first clock signal corresponding to the first clock demand signal to the CC to which the first clock demand signal has been transmitted among the CCs, on the basis of the second clock signal.SELECTED DRAWING: Figure 1