Provided are an apparatus and a method for a low power AES cryptographic circuit for an embedded system. The apparatus and method allows each round operation to be performed in an order of an add round operation, a sub byte operation, a shift row operation, and a mix column operation in order to realize a small circuit area by making maximum reuse of designed element modules. When data is input, on the first place, operations are repeated in the above order from a first round to a round right before a last round. During a last round, only an add round key operation and a sub byte operation, and a shift row operation are performed, and then an add round key operation using a secret key is performed. At this point, each operation is performed on data by a 8-bit unit.