105results about "Pulse generation by active elements" patented technology

A designed waveform generator includes at least one first signal generator including a first switching device and generating a square wave having a constant voltage level during an on-period of the first switching device and at least one second signal generator including a second switching device and controlling a transition period of the second switching device to generate a variable waveform having a variable voltage level during the transition period of the second switching device. The at least one first signal generator and the at least one second signal generator are connected to each other in a cascade manner.

An oscillator includes a control circuit and a ring of symmetric load delay cells. Each delay cell includes two novel symmetric loads. Each load involves a level shift circuit and a diode-connected transistor coupled in parallel with a current source-connected transistor. The control circuit converts an oscillator input signal into bias control signals that in turn control the effective resistance of the symmetric loads such that delays through the delay cells are a function of the input signal. The control circuit uses a symmetric load replica in a control loop to control the level shift circuits of the delay cells such that the oscillating delay cell output signals have a constant amplitude. In a first advantageous aspect, due to the constant amplitude, the oscillator is operable over a wide frequency range. In a second advantageous aspect, the oscillator input signal to output signal oscillation frequency has a substantially linear relationship.

A solid-state high-voltage pulse generator based on a three-phase chopper capacitance charger is described. In a first phase, an intermediate capacitor is resonance-charged via a diode. In a second phase, the intermediate capacitor is discharged to the load through one or more solid-state switches. In a third phase, the energy remaining in the intermediate capacitor is returned to a power-supply filter capacitor. In one embodiment, the three-phase chopper includes an intermediate capacitor that is charged by first and fourth branches of a bridge and discharged by second and third branches of a bridge. In one embodiment, each branch of the bridge includes a diode in series with an inductor. In one embodiment, a composite solid-state switch connects the intermediate capacitor to a primary winding of an output transformer such that the intermediate capacitor discharges through the primary winding. In one embodiment, a secondary winding of the output transformer is provided to an output load. In one embodiment, the output load is a reactive load. In one embodiment, the output load is a capacitive load.

An integrated circuit including a first circuit, a second circuit, a third circuit, a first complementary pair of transistors, and a second complementary pair of transistors. The first circuit may be configured to generate a first input signal in response to a first control input signal. The second circuit may be configured to generate a first output signal and a second output signal in response to the first input signal and a bias signal. The third circuit may be configured to generate the bias signal in response to a bias input signal. The first complementary pair of transistors may be configured to drive a first series output of the integrated circuit in response to the first output signal. The second complementary pair of transistors may be configured to drive a first shunt output of the integrated circuit in response to the second output signal.

The invention relates to an accelerating device of a rising edge and a falling edge of a current pulse and an accelerating method thereof. The accelerating device is characterized in that: an anode of a controllable direct current source is connected with a voltage stabilization clamping circuit, a bipolar current pulser and an anode of an earth load through a switch K; a cathode of the controllable direct current source is connected with a cathode of the earth load through the bipolar current pulser; and a pulse control circuit is connected with the bipolar current pulser; therefore, the accelerating device is formed. Beneficial effects of the invention are as follows: first, the voltage stabilization clamping circuit can generate high voltages in a bootstrapped mode on a capacitor C of a clamping voltage source, and then a rising edge and a falling edge of a current pulse are accelerated by using the high voltages of the capacitor C; therefore, there is no need to improve a direct current source voltage or provide an auxiliary power source; second, the output of the controllable direct current source is connected with the bipolar current pulser through an inductor Li of the voltage stabilization clamping circuit and the inductor Li plays a role in current stabilization of a forward peak value segment and a negative peak value segment of a current pulse Io (t), so that the forward peak value segment and the negative peak value segment of the current pulse Io (t) are smooth.

The invention discloses an IGBT (insulated gate bipolar transistor) driver, a signal processing method, a motor control system and a vehicle. The IGBT driver comprises an IGBT driving signal input circuit, a driving signal isolating circuit and a multi-IGBT output circuit which are connected in sequence, wherein the IGBT driving signals generated by the IGBT driving signal input circuit are addedto the multi-IGBT output circuit via the driving signal isolating circuit so as to drive each IGBT in the multi-IGBT output circuit to output signals. The IGBT driver also comprises a power source isolating circuit, wherein the power source isolating circuit comprises isolated output circuits individually corresponding to the IGBTs and a common output circuit corresponding to the whole of multiple IGBTs. The invention has the beneficial effects of achieving whole drive of multiple IGBTs and reducing the PCB area of the drive and protection circuit.

A solid-state high-voltage pulse generator based on a three-phase chopper capacitance charger is described. In a first phase, an intermediate capacitor is resonance-charged via a diode. In a second phase, the intermediate capacitor is discharged to the load through one or more solid-state switches. In a third phase, the energy remaining in the intermediate capacitor is returned to a power-supply filter capacitor. In one embodiment, the three-phase chopper includes an intermediate capacitor that is charged by first and fourth branches of a bridge and discharged by second and third branches of a bridge. In one embodiment, each branch of the bridge includes a diode in series with an inductor. In one embodiment, a composite solid-state switch connects the intermediate capacitor to a primary winding of an output transformer such that the intermediate capacitor discharges through the primary winding. In one embodiment, a secondary winding of the output transformer is provided to an output load. In one embodiment, the output load is a reactive load. In one embodiment, the output load is a capacitive load.

The invention provides a flat top pulse magnetic field generation device and a terahertz electromagnetic wave generation system. A first power supply discharges to hollow magnet and a main magnetic field is generated. When the first power supply discharges to first preset time, an IGBT is controlled to be switched on and switched off discontinuously, a second power supply is enabled to discharge to a first compensation coil and a second compensation coil, and a compensation magnetic field is generated; at second preset time, the IGBT is switched off, and the IGBT stops discharging to the firstcompensation coil and the second compensation coil. The main magnetic field and the compensation magnetic field are overlapped to form a total magnetic field. A duty cycle for discontinuous switch-onand switch-off the IGBT is determined according to magnetic field strength of the total magnetic field in a preset time period, the magnetic fields of the total magnetic field in the preset time period are kept unchanged, and a flat top pulse magnetic field is formed. The preset time period is the time period from the first preset time to the second preset time. According to the device and the system, terahertz waves of which pulse width is above a millisecond level, frequency reaches a THz level, and power reaches a kW level can be output continuously and stably in flat top pulse duration.

A bipolar pulse generator includes a pair of two-conductor transmission lines coupled together with a load positioned between the two transmission lines. Two segments of one transmission line are charged and switchably coupled to two segments of the other transmission line to produce a bipolar pulse on the matched load. The generator may include two transmission line structures coupled together with a load positioned between each transmission line structures. The first transmission line structure may include a stepped transmission line and an embedded transmission line segment. A switch is coupled between the embedded transmission line segment and another segment of the transmission line structure. During operation, the first transmission line structure is charged to a potential with the switch in the open position and, when the switch is closed, the charge on the first transmission line structure together with the second transmission line structure generates a bipolar pulse on the matched load.

A driver circuit for driving, for example, ultrasonic transducers in medical equipment, such as ultrasound scanning equipment. The driver circuit includes first inputs receptive of a pulsed signal, second inputs receptive of an analog signal, an output for applying a pulsed drive signal or an analog drive signal to a load. A pair of output transistors of complementary polarities are positioned with their current paths in series between opposing supply lines with a connection point intermediate between the transistors of the pair of transistors. The connection point between output transistors is coupled to the output of the circuit. The control terminals of the output transistors, which are coupled together, may be coupled to the first inputs with the driver functioning as a pulser, or else coupled to the second inputs with the driver functioning as a linear driver.

The present invention provides a semiconductor device which makes it possible to reduce a disturbance noise generated to the gate or the gate drive circuit of the current-driven semiconductor device by the parasitic inductance, and to increase accuracy and stability of gate drive. The semiconductor device comprises: a semiconductor element which is current driven; a gate drive circuit which controls the semiconductor element and a connection terminal unit, wherein the semiconductor element includes: a gate electrode pad formed on a stacked structure of a nitride semiconductor layer; ohmic electrodes; the said connection terminal unit includes: a first ohmic electrode terminal (6) connected to the first ohmic electrode pad; a second ohmic electrode terminal (7) connected to the second ohmic electrode pad; a gate drive terminal (7) connected to the first ohmic electrode pad; and a gate terminal (8) connected to the gate electrode pad, an input terminal of the gate drive circuit is connected to the gate drive terminal, an output terminal of the gate drive circuit is connected to the gate terminal, and a potential of the first ohmic electrode pad corresponds to a reference potential of the gate drive circuit.

The invention discloses broadband radio frequency sampling mixer, and belongs to the technical field of radio frequency. The mixer comprises a pulse generator, a microstrip line-trough line conversion Balun and a sampling gate diode circuit. The pulse generator in the mixer provided by the invention makes an input 50MHz local oscillator signal generate abundant harmonic components needed by sampling, harmonic frequency covers 2MHz-6GHz, the generated pulse signal is high in signal amplitude and good in phase noise, meanwhile the pulse signal can be prevented from returning back to the input end of an local oscillator, and isolation degrees of the local oscillator, radio frequency and intermediate frequency are improved; the microstrip line / trough line Balun adopts a microstrip line and trough line conversion structure, as the 1 / 4 wave length trough line forming circuit is used, the microstrip line / trough line Balun has an extremely small insertion loss and standing-wave coefficient, reflection of the microwave pulse signal is reduced, and transmission of the microwave pulse signal is more facilitated; an intermediate frequency signal generated by sampling and mixing is high in signal amplitude and good in signal purity; the whole circuit can be integrated onto a printed circuit board, so that the volume is small and the cost is low.

The invention discloses a driver for isolating an edge signal, which comprises a signal conversion unit, an isolated transmission unit, a signal recovery unit and a complementary level transformation power amplification unit, wherein the signal conversion unit is used for converting a drive input signal into two circuits of complementary signals; the isolated transmission unit is connected with the signal conversion unit and used for performing isolated transmission on the two circuits of the complementary signals; the signal recovery unit is connected with the isolated transmission unit and used for recovering the two circuit of the complementary signals transmitted by the isolated transmission unit into drive input signals; and the complementary level transformation power amplification unit is connected with the signal recovery unit and used for performing power amplification on the drive input signals acquired through recovery by the signal recovery unit. The driver substantially improves the driving performance of MOSFET and IGBT and has short drive delay; typical opening delay is less than or equal to 150 ns; the closing delay is less than or equal to 120 ns; and the driver has the capacity of long-term operation and at least 20A transient drive and has high rising and falling edge, no duty cycle limit and low static electricity consumption.

The invention discloses a digitalized control method for a pulse power source, wherein the digitalized control method is used for controlling a main power supply loop which comprises n units connected in parallel, and each unit comprises an IGBT (Insulated Gate Bipolar Transistor) topological structure formed by connecting m IGBT H (Half) bridges in series. The method comprises the steps of: setting a carrier with a given waveform and the frequency F2 in a programmable logic device; inputting a given clock signal into the programmable logic device; calling the given waveform once every a given waveform period; calling the carrier once every 1 / (F2*m) and 1 / (F2*n) in a given waveform bottom width duration, wherein the carrier is not called beyond the given waveform bottom width duration; and scaling a difference value obtained by subtracting an output current value of the main power source loop from the called given waveform, adding a scaled product to the output current value of the main power supply loop, subtracting the output value from n equalized currents, comparing an obtained current-equalization difference value and an obtained reverse-phase difference value with the called carrier respectively to obtain 2*m*m PWM (Pulse-Width Modulation) signals which are used for controlling the main power source loop. The invention further provides a device for realizing the method.

A low power high-speed design for integrated circuits using BiCMOS processes is disclosed. The design uses a first stage including bipolar transistor pairs configured as inputs and drivers for an output. A second CMOS stage is coupled to the first stage in a series-gated configuration and receives clock or data inputs. A third stage is coupled to the second stage and is configured as a current source. The combination results in circuits that can operate at conventional supply voltages of 1.8 volts.

The invention discloses a multi-channel onboard microsecond pulse plasma flowing control power supply. The multi-channel onboard microsecond pulse plasma flowing control power supply comprises a high-voltage module and a control module, wherein the high-voltage module comprises a first onboard battery DC inversion module, a voltage multiplication charging module, a channel selection module and a pulse formation module, and the control module comprises a remote controller, a receiving antenna, a receiver, a first fiber isolation plate until an N(th) fiber isolation plate, a first signal outputend until an N(th) signal output end and a second onboard battery. The power supply is provided with a plurality of output channels and can independently work, the various functions such as unmanned aerial vehicle plasma flowing control suppression separation, delayed speed reduction and rolling moment control can be achieved by combined application of multiple channels. The power supply also hasthe characteristics of small size and light weight, and remote control can be performed by the remote controller.

The invention relates to a low power consumption double-edge trigger based on dual mode redundancy comprising a clock network, a first latch, a second latch, a C unit and a keeper, wherein the first latch and the second latch are latch circuit structures controlled by a clock signal, the first latch comprises a signal input terminal IN1 and a signal output terminal OUT1; the second latch comprisesa signal input terminal IN2 and a signal output terminal OUT2; the C unit comprises a first signal input terminal IN3, a second signal input terminal IN4 and a signal output terminal OUT3; and the keeper comprises a signal input terminal IN5 and a signal output terminal OUT4. The low power consumption double-edge trigger provided by the invention has lower power consumption in the case that the input signal has glitch, as the low power consumption double-edge trigger adopts the C unit, the load of the clock network is reduced, thereby effectively reducing the power consumption on the clock network, the invalid hop in the circuit is inhibited by using the clock control technology, and the additional power consumed by the invalid hop in the circuit is reduced.

A low power high-speed design for integrated circuits using BiCMOS processes is disclosed. The design uses a first stage including bipolar transistor pairs configured as inputs and drivers for an output. A second CMOS stage is coupled to the first stage in a series-gated configuration and receives clock or data inputs. A third stage is coupled to the second stage and is configured as a current source. The combination results in circuits that can operate at conventional supply voltages of 1.8 volts.

The invention relates to a feedback-winding-free inductance power oscillating circuit, which is characterized by comprising a resister R1, a resister Rb, a resister Rf, a resister Rp, a resister Re, a resister Re, a capacitor Cf, a high-speed switching diode D, an audion Q1, an audion Q2, an audion Q3, an inductance coil or an ordinary induction transformer T. Compared with the prior art, the invention has the advantages of ideal working condition of the oscillating circuit, ensured stable power output of the drive circuit and no generation of overexcitation which causes a excitation-driven transistor to be burnt due to drastic changes of loading.

The invention provides a pulse signal generator, the pulse signal generator comprises a signal generation part, a signal processing part and a signal output part; the signal generation part comprisesa signal generation circuit, the signal generation circuit is used for generating pulse signals and sending the pulse signals to the signal processing part; the signal processing part comprises a power amplification circuit, the signal output part comprises an electrical signal output circuit and an optical signal output circuit; the power amplification circuit is used for receiving the pulse signals, performing power amplification for the pulse signals and then sending the pulse signals to the signal output part; the optical signal output circuit is used for receiving the pulse signals subjected to power amplification, converting the pulse signals into optical signals and outputting the converted signals; and the electrical signal output circuit is used for receiving the pulse signals which are not subjected to or subjected to power amplification, and directly outputting and / or outputting the pulse signals after electric isolation. The technical scheme provided by the invention can output the optical signals and the electrical signals, and solves a problem of single type of the pulse signals of the pulse signal generator in the prior art.

The invention discloses a repetition frequency nanosecond pulse generation circuit based on a drift step recovery diode. The output end of a charging loop is connected with the input end of a primarypulse forming loop; the output end of the primary pulse forming loop is connected with a primary winding of a saturable pulse transformer; one end of a secondary winding in the saturable pulse transformer is connected with one end of a secondary energy storage capacitor; the other end of the secondary energy storage capacitor is connected with the positive electrode of a DSRD switch assembly and one end of a resistive load; and the other end of the secondary winding in the saturable pulse transformer, the negative electrode of the DSRD switch assembly and the other end of the resistive load are all grounded. The circuit can effectively solve the problems of high amplitude output and high repetition frequency work of a DSRD-based pulse generation circuit in the prior art.

Disclosed is a clock generating circuit including a filter and a ring oscillator. The filter receives an input signal and accordingly determines a first voltage signal and a second voltage signal that are outputted via a first node and a second node respectively. The filter includes a first filtering circuit and a second filtering circuit coupled in parallel between the first node and a reference voltage terminal; the second filtering circuit includes a switch and a capacitor connected in series, in which the second node is between the switch and the capacitor, and the switch is turned off in an analog clock data recovery (ACDR) mode and turned on in a clock multiplication unit (CMU) mode. The ring oscillator outputs at least one clock according to the first voltage signal in the ACDR mode and outputs at least one clock according to the second voltage signal in the CMU mode.

The invention provides a single pulse generation circuit and a level conversion circuit. The single pulse generation circuit is applied to a level conversion circuit comprising a first signal input end, a second signal input end and two pull-down tubes, and comprises a port detection module, a bidirectional detection trigger module, a single pulse generation module and a power supply voltage module; the method comprises the following steps: detecting whether any one of a first signal input end and a second signal input end of a level conversion circuit is overturned from a high level to a lowlevel; after the falling edge is detected by the single pulse generation circuit,generating a high-level pulse signal to open a pull-down tube of the level conversion circuit, and increasing the falling edge speed of an output port, so that in the signal transmission process, the discharge delay on a parasitic capacitor is shortened, the problem of signal transmission distortion is avoided, and the signal integrity is improved.

A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.

System and method for a clock driver. An input taking circuit is used for receiving small-signal logic inputs. A voltage follower circuit is coupled to the input taking circuit and used to generate a set of voltage follower outputs. An output circuit is coupled to the voltage follower circuit to receive the set of voltage follower outputs as inputs and generate output signals. The voltage follower circuit is coupled to a switching circuit, that is connected to the set of voltage follower outputs and is deployed for reducing the phase noise level of the output signals.

The invention discloses an ultrasonic front-end circuit and ophthalmological B-ultrasonic system, which comprise a circuit board and a probe, and a single chip microcomputer, an isolation protection circuit and the ultrasonic front-end circuit are arranged on the circuit board; the single-chip microcomputer outputs a first pulse emission signal, a second pulse emission signal and a third pulse emission signal, and outputs a first pulse emission control signal, a second pulse emission control signal and a third pulse emission control signal after being isolated by the isolation protection circuit. And the ultrasonic front-end circuit performs level conversion on the first pulse emission control signal, the second pulse emission control signal and the third pulse emission control signal, loads positive and negative excitation voltages to form a high-voltage excitation signal, and excites a transducer in the probe to generate a corresponding ultrasonic signal. The transducer is excited bypositive and negative excitation voltages, the excitation voltage is reduced by half, the universality and replaceability of device selection of a power supply and an ultrasonic front-end circuit aregreatly improved, and the problem that the device selection is limited due to the fact that the existing ophthalmological B-ultrasonic is only provided with positive high voltage can be solved.

The invention discloses a pulse width signal amplification circuit. After the input pulse width signal is isolated by a photoelectric isolation circuit, it enters a power amplification circuit to amplify voltage and current, and the pulse width signal after voltage and current amplification is output to a power tube through a current limiting resistor. The gate of the power tube is used to complete the driving of the power tube; the transient overvoltage protection circuit is connected between the grid and the source of the power tube to suppress the voltage spike interference signal between the grid and the source; the negative voltage generating circuit generates 5V, Provided to the photoelectric isolation circuit and power amplifier circuit. The circuit structure of the present invention is simple and reliable, simplifies the power supply, eliminates the peak pulse voltage appearing at both ends of the gate and source of the power tube, widens the frequency band of the pulse width signal adapted to the drive circuit, and not only can be applied to insulated gate bipolar transistors, And it can be applied to metal oxide field effect transistors with higher frequency.

The invention provides a drive circuit and a car. The drive circuit comprises a drive signal source; a first metal-oxide-semiconductor field-effect transistor, wherein the drive signal source is connected with the source and gate of the first metal-oxide-semiconductor field-effect transistor to form a closed circuit, and the drain of the first metal-oxide-semiconductor field-effect transistor is connected with a preset voltage end; and a voltage stabilizing circuit connected with the closed circuit in series, wherein when the first metal-oxide-semiconductor field-effect transistor is in a switch-off state, the voltage stabilizing circuit enables a voltage between the source and gate of the first metal-oxide-semiconductor field-effect transistor to be smaller than a preset value. According to the embodiment of the invention, under the interference condition, the voltage of the first metal-oxide-semiconductor field-effect transistor is not enabled to reach a switch-on threshold through utilization of the voltage stabilizing circuit.