12results about "Pulse generation by active elements" patented technology

A bipolar pulse source based on a novel magnetic isolation drive includes a half-bridge drive circuit module, a magnetic isolation drive circuit module, a bipolar Marx pulse source module and a load; the bipolar high-voltage pulse source based on the novel magnetic isolation drive is provided.The drive circuit topology is simple, the magnetic core stack and the anti-parallel mode of the secondary winding are utilized, only two control signals are needed to realize the separate control of four switches in the double Marx topology.The developed pulse source prototype has an output voltage of 0-20kV, a pulse width of 3-10us, a maximum repetition frequency of 200Hz, and a flexible interval between positive and negative polarity pulses.The pulse source adopts modular design, and higher output voltage can be realized by stacking the modules.

A differential signal input buffer (200) is disclosed. The differential signal input buffer (200) may receive a differential signal that includes a first signal and a second signal and may be divided into a first section (260) and a second section (261). The first section (260) may buffer and / or amplify the first signal based on a first level-shifted second signal. The second section (261) may buffer and / or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section (260) may buffer and / or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section (261) may buffer and / or amplify the second signal based on a second level-shifted first signal.

The invention aims to provide an asynchronous time sequence multiplexed output time domain superposition high-voltage pulse generator based on LC-Marx topology. The asynchronous time sequence multiplexed output time domain superposition high-voltage pulse generator comprises a main control switch Smain and at least two paths of pulse generation branches with the same circuit structure, the pulse generation branch comprises n pulse generation units which are cascaded in sequence; the input end of the main control switch Smain is connected to the direct-current power supply Uin, and the output end of the main control switch Smain is connected to the input end of the pulse generation unit; after the pulse generation units of each pulse generation branch are cascaded, the cathode cascade point of the first pulse generation unit is grounded through an inductor Ls, and the anode cascade point of the nth pulse generation unit is connected with the input end of a load Rload; the pulse generator can reduce the requirement for a direct-current power supply, has wide input voltage adaptability, can ensure that the pulse generator has approximate square wave output, has wide application scenarios, and is stable and reliable in work.

A defibrillator of the present disclosure includes a H-bridge type biphasic pulse generation circuit connected to the rear stage side of a high-voltage capacitor. The biphasic pulse generation circuit includes a first switch, a second switch connected in parallel to the first switch, a third switch connected in series and to the rear stage side of the first switch, and a fourth switch connected in series and to the rear stage side of the second switch. The biphasic pulse generation circuit outputs a biphasic pulse from a first output line connected to a connection intermediate point between the first and third switches and from a second output line connected to a connection intermediate point between the second and fourth switches. In at least one of the first switch to the fourth switch, a plurality of thyristors are connected in series, and a resistor is connected in parallel to each thyristor.

The invention discloses a high-speed data serialization circuit for high-speed and high-energy-efficiency wired interface application. The high-speed data serialization circuit comprises a plurality of edge enhanced unit interval pulse generation circuits and an all-in-one multiplexer circuit, each edge enhanced unit interval pulse generation circuit is used for generating a pulse signal with a unit interval width based on the states of an input data signal and a clock signal and a preset pre-charging and rapid discharging strategy; and each input end of the all-in-one multiplexer circuit is correspondingly connected with the output end of one edge enhanced unit interval pulse generation circuit, and is used for serializing all pulse signals through an active peaking technology and outputting the pulse signals to an output node. The high-speed data serialization circuit provided by the invention can expand the bandwidth of the output node so as to adapt to higher frequency requirements.

The utility model provides a novel digital composite signal generator, specifically related to data composite signal technical field, including single-chip microcomputer and digital synthesis circuit, single-chip microcomputer inside integrated DAC, and DAC generates fundamental wave sinusoidal signal, and digital synthesis circuit includes operational amplifier module and low pass filter module, and the fundamental wave sinusoidal signal of DAC generation, through operational amplifier module promotes fundamental wave amplitude, and low pass filter restrains high -frequency noise, ensures the output smooth pure sinusoidal wave. Buffer amplifier enhances signal drive ability and adapts 100 omega load, and adjustable gain module realizes output amplitude accurate control. The on -chip VDD monitor real -time monitoring power supply anomaly, watchdog timer prevents program failure, and JTAG debugging circuit supports non -invasive full -speed in system debugging. The scheme fuses signal processing, voltage monitoring and fault protection function, realizes the novel digital composite signal generator of frequency and amplitude programmable control, guarantees output stable and reliable in industrial environment and long -term unattended operation.

An integrated circuit (IC) device includes a first die including a first transmitting circuit, a first receiving circuit, and a first circuit. The first transmitting circuit transmits an output clock signal corresponding to a first clock signal. The first receiving circuit receives an input clock signal and an input signal, and outputs, based on the input clock signal, a first signal corresponding to the input signal. The first circuit outputs, based on the first clock signal, a second signal corresponding to the first signal. The first circuit, in response to a first value of a first selection signal, outputs the second signal in response to a first edge of the first clock signal. The first circuit, in response to a second value different from the first value of the first selection signal, outputs the second signal in response to a second edge of the first clock signal.

The utility model relates to an edge-triggered monopulse circuit, system and device. The circuit comprises a first resistor, a second resistor, a third resistor, a capacitor, a diode, a first MOS tube and a second MOS tube. One end of the first resistor is connected to a control signal input end, the other end of the first resistor is connected with a grid electrode of the first MOS tube, a drain electrode of the first MOS tube is connected with one end of the second resistor and one end of the third resistor, and the other end of the second resistor is connected to a first continuous power supply end; the other end of the third resistor is connected with one end of a capacitor, the other end of the capacitor is connected with the positive electrode of a diode, the negative electrode of the diode is connected with the grid electrode of a second MOS tube, and the drain electrode of the second MOS tube is connected to the low-pulse output end; source electrodes of the first MOS tube and the second MOS tube are grounded; the circuit is simple in design, low in development and manufacturing cost, capable of achieving effective signal control while meeting the function of generating low pulses, and beneficial to application and popularization.

A semiconductor device includes an input port, a pulse generation circuit, and a serial-parallel conversion circuit. The input port is connected to an input port of the pulse generation circuit and a data signal input port of the serial-parallel conversion circuit. A signal received at the input port is a start bit and a data signal. The pulse generation circuit includes a delay circuit. A clock signal output port of the pulse generation circuit is connected to a clock signal input port of the serial-parallel conversion circuit.

This invention discloses an ultra-high precision second pulse and 10MHz signal measurement circuit and method, relating to time unification technology and signal communication fields. The circuit includes a 10ps-level four-channel first and second TDC chip, a 10MHz high-stability reference clock module, a daisy-chain arrangement of the measurement signal input module, and a power supply ultra-clean module. The first TDC chip, second TDC chip, DC-DC circuit, first-stage clean circuit, and second-stage clean and filter circuit all utilize potted components. The test circuit achieves 10ps peak-to-peak measurement accuracy by selecting a 10ps-level measurement chip, employing power supply ultra-clean technology, high-stability reference clock technology, a daisy-chain arrangement of the measurement and reference clocks, and a device potting and temperature control method, thus improving upon the original device specifications. The method further improves measurement accuracy through measurement result fitting technology, optimizing the original 10ps peak-to-peak measurement accuracy to 6ps peak-to-peak measurement accuracy.

The invention provides a clock signal generating circuit and a clock signal generating method thereof. When the analog clock signal generator circuit does not provide the output clock signal, the control circuit controls the multiplexer circuit to select and output the oscillation signal provided by the oscillator circuit to the analog clock signal generator circuit, and controls the clock path circuit to stop transmitting the input clock signal.

To provide a defibrillator capable of using a component having a lower withstand voltage than a conventional one while satisfactorily maintaining an original operation as the defibrillator.SOLUTION: The defibrillator of the present disclosure is a defibrillator including an H-bridge type biphasic pulse forming circuit connected to a rear stage side of a high-voltage capacitor, the biphasic pulse forming circuit including a first switching unit, a second switching unit connected in parallel to the first switching unit, a third switching unit connected in series to a rear stage side of the first switching unit, and a fourth switching unit connected in series to a rear stage side of the second switching unit, A biphasic pulse is output from a first output line connected to a connection midpoint between the first switching unit and the third switching unit and a second output line connected to a connection midpoint between the second switching unit and the fourth switching unit. In at least one of the first to fourth switching units, a plurality of thyristors are connected in series, and a resistor is connected in parallel to each of the plurality of thyristors.SELECTED DRAWING: Figure 1