Low power consumption double-edge trigger based on dual mode redundancy

Abstract

The invention relates to a low power consumption double-edge trigger based on dual mode redundancy comprising a clock network, a first latch, a second latch, a C unit and a keeper, wherein the first latch and the second latch are latch circuit structures controlled by a clock signal, the first latch comprises a signal input terminal IN1 and a signal output terminal OUT1; the second latch comprisesa signal input terminal IN2 and a signal output terminal OUT2; the C unit comprises a first signal input terminal IN3, a second signal input terminal IN4 and a signal output terminal OUT3; and the keeper comprises a signal input terminal IN5 and a signal output terminal OUT4. The low power consumption double-edge trigger provided by the invention has lower power consumption in the case that the input signal has glitch, as the low power consumption double-edge trigger adopts the C unit, the load of the clock network is reduced, thereby effectively reducing the power consumption on the clock network, the invalid hop in the circuit is inhibited by using the clock control technology, and the additional power consumed by the invalid hop in the circuit is reduced.

Description

Technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a low power consumption double-edge trigger based on dual-mode redundancy. Background technique [0002] With the rapid development of integrated circuits, the process size of integrated circuits continues to shrink, and the number of integrated transistors and transistor clock frequencies are also increasing, resulting in an increasingly prominent power consumption problem for integrated circuit chips. In the design of synchronous digital very large-scale integrated circuits, the clock system is mainly composed of clock network circuits and sequential circuits, which account for about 30% to 60% of the total power consumption of the system. The sequential circuits include flip-flops and latches. It consumes about 90% of the total power consumption of the clock system, and the power consumption of the flip-flop accounts for a large proportion of the total power consumption...

AI Technical Summary

Problems solved by technology

Assuming that the first latch is in the transparent mode state, the states of the inverter 102 and the inverter 104 will be reversed with the inversion of the input signal, and the two inverters at this time will cause additional power consumption. That is, when there is a glitch in the input signal, the power consumption of the flip-flop circuit will increase significantly

Moreover, the traditional double-edge trigger uses more transmission gates, which increases the load on the clock network circuit, which is not conducive to reducing the power consumption of the clock network circuit, thus increasing the overall power consumption of the circuit to a certain extent.

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