7 results about "Bicmos process" patented technology

The present invention discloses an optimized integration method for high stress edge effect of analog BiCMOS process and a high linearity dual polycrystalline capacitor, the steps of which include: 1) depositing a polycrystalline film layer of a polycrystalline capacitor lower plate of P1 angstrom above a field oxide layer on the surface of an N-type well, and completing N-type photolithography implantation doping; 2) depositing a first dielectric layer of a dual polycrystalline capacitor of d1 angstrom, and completing the production of a protective film layer at the edge of the lower electrode of the dual polycrystalline capacitor by an exposure and etching process; 3) depositing a polycrystalline capacitor dielectric composite film layer of d2 angstroms, and completing the production of a capacitor dielectric layer structure by an exposure and etching process; the high linearity dual polycrystalline capacitor includes a substrate, an N-type buried layer, a P-type buried layer, an epitaxial layer, an N-type well, a self-aligned P-type well, etc. The present invention significantly improves the edge effect of the dual polycrystalline capacitor by integrating a high stress edge effect optimization technical solution of a high linearity dual polycrystalline capacitor in an analog integrated circuit.

The invention discloses a high-precision adjustable large-swing range integrated multi-channel driving circuit, on one hand, a pre-stage gain adjustable circuit is adopted to calibrate gain deviation and realize multi-channel integration, and on the other hand, a post-stage large-swing adjustable output stage circuit is adopted to realize multi-channel integration by combining digital coarse tuning and analog fine tuning functions. And the large-range high-precision adjustment of the output signal amplitude is realized. The driving circuit adopts a BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor Transistor) process, and a pre-stage gain adjustable circuit realizes gain deviation calibration through an improved Gilbert unit circuit structure and is compatible with a multi-channel integration function. Besides, a rear-stage large-swing adjustable output stage circuit controls the on-off of a tail current source through a switch, so that the swing range of an output signal reaches 3.0 V, and the tail current source of the current mode logic circuit is continuously adjusted within a certain range by integrating a 14-bit digital-to-analog converter circuit. And the fine adjustment resolution of the output signal amplitude is less than 0.2 mV.

The application belongs to the technical field of radio frequency integrated circuits, and particularly relates to an anti-radiation SiGe radio frequency front-end chip for a 128-beam phased array. The chip is integrated with 128 transceiving channels by using a SiGe BiCMOS process, each channel contains an LNA, a phase shifter, an attenuator, a PA and a T / R switch, and covers a Ku / Ka frequency band (10-30 GHz); a beam control interface, an oscillator distribution network and an anti-radiation reinforcement module are integrated, the anti-radiation reinforcement module bears a total dose of 100krad (Si) and a single particle effect of 75MeV·cm2 / mg through a three-mode redundant register, a ring oscillator monitoring and a charge sharing elimination layout. The chip is integrated with 128 channels in a single chip, simplifies the design of a satellite-borne phased array radio frequency front-end, has high integration, high performance and strong anti-radiation capacity, and is suitable for application requirements of a satellite communication payload.

The invention provides a method for integrating a bipolar transistor with a small-line-width complementary metal oxide semiconductor. The method comprises the following steps: depositing a first protective dielectric layer on a semiconductor substrate on which a CMOS device and a device isolation structure are formed; performing high-speed device ion implantation on the bipolar transistor region by taking the first protective dielectric layer as an implantation protective layer; and then, depositing a second protective dielectric layer on the first protective dielectric layer. According to the invention, the deposition of the protective dielectric layer is divided into two steps, and the thin layer deposited in the first step effectively solves the problems of ion implantation channel effect and photoresist pouring; and the layer deposited in the second step is overlapped with the first layer to form a thickened composite protection layer, so that the window of the subsequent etching process is obviously enlarged. According to the method, a low-temperature process is adopted, the thermal budget is controlled, and the stability and the yield of the small-line-width BiCMOS process are improved.

The invention discloses an analog multiplexer which comprises a plurality of data input buffers, a clock input buffer, a core multiplexer and a data output buffer, the input end of each data input buffer is electrically connected with the output end of a digital-to-analog conversion module, and the output end of each data input buffer is electrically connected with one data input end of the core multiplexer; the output end of the clock input buffer is electrically connected with the clock input end of the core multiplexer, and the output end of the core multiplexer is electrically connected with the input end of the data output buffer; wherein the analog multiplexer is manufactured based on a SiGe BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process, and the digital-to-analog conversion module is manufactured based on a CMOS process; each data input buffer is used for shifting and isolating a signal of the digital-to-analog conversion module to obtain a group of differential input signals, the clock input buffer is used for obtaining a clock input signal, and the core multiplexer is used for selecting a group of differential input signals to output according to the clock input signal. And the requirement of high transmission rate of the optical communication system is met.

The present invention proposes a common-source common-base amplifier based on SiGe-BiCMOS process, including an input matching unit, a first-stage differential common-source common-base unit, a second-stage differential common-source common-base unit, a third-stage differential common-source common-base unit, a fourth-stage differential common-source common-base unit, and an output impedance matching unit; compared with a low-noise amplifier with a four-stage single-ended structure, it has better anti-noise capability and can obtain higher gain at a lower frequency; compared with a low-noise amplifier with a five-stage differential structure, it has stronger stability. The present invention adopts MOS transistors at the input stage, which obtains a lower noise coefficient at a higher frequency compared with HBT transistors; the input stage adopts a composite transistor structure to improve the power gain of the circuit; the common-source common-base structure adopted by the present invention reduces the Miller effect of the device and effectively expands the working frequency band.

This invention discloses an interface treatment method for reducing the defect density of selective epitaxial growth in the germanium-silicon base region of an HBT (Hardware-to-Bit) device. The method includes: providing a patterned substrate; performing wet cleaning on the patterned substrate to remove intrinsic oxides, and drying the wet-cleaned patterned substrate; performing in-situ plasma cleaning on the patterned substrate; performing in-situ H2 baking on the patterned substrate; and forming a germanium-silicon base region in the base region growth window through selective germanium-silicon epitaxy. In this invention, due to the strict thermal budget constraints of the SiGe BiCMOS process, three surface pretreatment methods—wet cleaning, in-situ plasma cleaning, and in-situ H2 baking—are specifically combined to treat the growth interface before SiGe epitaxy, thereby obtaining a high-quality SiGe epitaxial layer and improving the electrical performance of the SiGe HBT device.