3 results about "Bicmos process" patented technology

The application belongs to the technical field of radio frequency integrated circuits, and particularly relates to an anti-radiation SiGe radio frequency front-end chip for a 128-beam phased array. The chip is integrated with 128 transceiving channels by using a SiGe BiCMOS process, each channel contains an LNA, a phase shifter, an attenuator, a PA and a T / R switch, and covers a Ku / Ka frequency band (10-30 GHz); a beam control interface, an oscillator distribution network and an anti-radiation reinforcement module are integrated, the anti-radiation reinforcement module bears a total dose of 100krad (Si) and a single particle effect of 75MeV·cm2 / mg through a three-mode redundant register, a ring oscillator monitoring and a charge sharing elimination layout. The chip is integrated with 128 channels in a single chip, simplifies the design of a satellite-borne phased array radio frequency front-end, has high integration, high performance and strong anti-radiation capacity, and is suitable for application requirements of a satellite communication payload.

The invention provides a method for integrating a bipolar transistor with a small-line-width complementary metal oxide semiconductor. The method comprises the following steps: depositing a first protective dielectric layer on a semiconductor substrate on which a CMOS device and a device isolation structure are formed; performing high-speed device ion implantation on the bipolar transistor region by taking the first protective dielectric layer as an implantation protective layer; and then, depositing a second protective dielectric layer on the first protective dielectric layer. According to the invention, the deposition of the protective dielectric layer is divided into two steps, and the thin layer deposited in the first step effectively solves the problems of ion implantation channel effect and photoresist pouring; and the layer deposited in the second step is overlapped with the first layer to form a thickened composite protection layer, so that the window of the subsequent etching process is obviously enlarged. According to the method, a low-temperature process is adopted, the thermal budget is controlled, and the stability and the yield of the small-line-width BiCMOS process are improved.

This invention discloses an interface treatment method for reducing the defect density of selective epitaxial growth in the germanium-silicon base region of an HBT (Hardware-to-Bit) device. The method includes: providing a patterned substrate; performing wet cleaning on the patterned substrate to remove intrinsic oxides, and drying the wet-cleaned patterned substrate; performing in-situ plasma cleaning on the patterned substrate; performing in-situ H2 baking on the patterned substrate; and forming a germanium-silicon base region in the base region growth window through selective germanium-silicon epitaxy. In this invention, due to the strict thermal budget constraints of the SiGe BiCMOS process, three surface pretreatment methods—wet cleaning, in-situ plasma cleaning, and in-situ H2 baking—are specifically combined to treat the growth interface before SiGe epitaxy, thereby obtaining a high-quality SiGe epitaxial layer and improving the electrical performance of the SiGe HBT device.