16 results about "Ballast resistor" patented technology

According to the present disclosure, a semiconductor device includes a semiconductor substrate of a first conductivity type, in which a cell region, a ballast resistor region, and a termination region surrounding the ballast resistor region are defined, a first insulating film arranged on a front surface of the semiconductor substrate, having a first opening in the cell region, and having at least one second opening in the ballast resistor region, a second insulating film filled in the at least one second opening, a first impurity layer of a second conductivity type arranged on the front surface of the semiconductor substrate below the first opening, and a second impurity layer of the second conductivity type arranged on the front surface of the semiconductor substrate below the at least one second opening, a conductive film arranged from the front surface of the first opening of the semiconductor substrate to the termination region.

Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a spark gap device includes first and second conductive layers formed over a substrate, where the first and second conductive layers are electrically connected to first and second voltage nodes, respectively. The first conductive layer includes a plurality of arcing tips configured to form arcing electrode pairs with the second conductive layer to form an arc discharge in response to an EOS voltage between the first and second voltage nodes. The spark gap device further includes a series ballast resistor electrically connected between the arcing tips and the first voltage node, where the ballast resistor in formed in a metallization layer over the substrate and a resistance of the series ballast resistor is substantially higher than a resistance of the second conductive layer.

The utility model relates to an electrostatic protection circuit suitable for a radio frequency port, and the circuit comprises a power clamping circuit which comprises a power voltage end and a grounding end; the primary electrostatic protection branch comprises a first diode and a second diode, the anode of the first diode is connected with the radio frequency port, the cathode of the first diode is connected with the power supply voltage end, the anode of the second diode is connected with the grounding end, and the cathode of the second diode is connected with the radio frequency port; the three-stage electrostatic protection branch comprises a first PMOS tube and a first NMOS tube, the source electrode of the first PMOS tube is connected with the power supply voltage end, the drain electrode of the first PMOS tube is connected with the protected device, the drain electrode of the first NMOS tube is connected with the protected device, and the source electrode of the first NMOS tube is connected with the grounding end VSS; and the secondary electrostatic protection branch is connected between the radio frequency port and the protected device. According to the utility model, reliable ESD protection for various protection standards and grades is provided, and the problems in the prior art that the cost is increased by adopting off-chip components, or the performance of a radio frequency port is influenced by adopting a ballast resistor and the like are solved.

The application discloses a metal-oxide semiconductor field effect transistor and a power device. The metal-oxide semiconductor field effect transistor comprises a substrate, an epitaxial layer, a drift region, a well region and a first active region arranged on a side of the epitaxial layer away from the substrate, the conductive type of the first active region is opposite to that of the well region, a ballast resistor region, the ballast resistor region is located on a side of the well region away from the drift region, the conductive type of the ballast resistor region is the same as that of the first active region, a low resistance region, the low resistance region is located on a side of the well region away from the drift region, the conductive type of the low resistance region is the same as that of the first active region, the doping concentration of the low resistance region is greater than that of the ballast resistor region, the doping concentration of the low resistance region is less than that of the first active region, and the ballast resistor region and the low resistance region are located on the same side of the first active region. The technical scheme provided by the embodiment of the application improves the ability of the device to bear transient large current and short circuit characteristics.

The present disclosure relates to a fin-based bipolar electrostatic discharge device. The present disclosure relates to semiconductor structures, and more specifically, to electrostatic discharge (ESD) devices and methods of manufacturing the same. The structure (ESD device) includes a bipolar transistor including a collector region, an emitter region, and a base region, and a lateral ballast resistance adjacent to the collector region including a semiconductor material.

The utility model relates to the technical field of power semiconductors, in particular to an IGBT (Insulated Gate Bipolar Transistor) device with a built-in ballast resistor, which comprises a trench region, N + type source regions, polycrystalline silicon regions and contact hole regions, a plurality of N + type source regions and polycrystalline silicon regions are alternately arranged at intervals along the length direction of the trench region, and the contact hole regions are positioned in the N + type source regions; along the thickness direction of the IGBT device, the IGBT device sequentially comprises a collector metal layer, a P + substrate and an N-substrate, and a deep groove is etched on the N-substrate corresponding to a groove region; first doped regions and second doped regions which are alternately distributed are formed on the N-substrate on the two opposite sides of the deep groove, the positions of the first doped regions correspond to the positions of the N + type source regions, and the positions of the second doped regions correspond to the positions of the polycrystalline silicon regions; the top end of the first doped region is provided with an N + well region, and the top end of the second doped region is provided with a second N-well region. The IGBT device provided by the utility model can obtain a larger positive temperature coefficient, and has little influence on the conduction voltage drop VCESAT of the IGBT device at normal temperature.

According to the non-uniform emitter structure optimization design method provided by the invention, collaborative optimization design is carried out on a non-uniform emitter contact structure based on the heat distribution characteristic in the preset working state, and differentiated configuration is carried out on the distance and length of emitter fingers and the resistance value of a ballast resistor according to high-temperature and low-temperature regions; under the action of electrothermal coupling, the current density of a high-temperature area of the device is effectively suppressed, and the conductivity of a low-temperature area is fully called, so that the current distribution and temperature field of the whole emitter junction surface are remarkably balanced, the hot spot effect and the positive feedback risk caused by the hot spot effect are fundamentally weakened, and the reliability of the device is improved. And the thermal stability, the reliability and the service life of the heterojunction bipolar transistor under a high-power working condition are greatly improved.

The invention provides a power amplification chip and a radio frequency front end module, the power amplification chip comprises a substrate and at least two stages of power amplification arrays arranged on the substrate, each stage of power amplification array comprises a plurality of transistors and a plurality of ballast resistors, and each transistor corresponds to one ballast resistor; in the power amplification array located at the rear stage in the at least two stages of power amplification arrays, all the ballast resistors are sequentially connected with the input ends of the power amplification arrays, the resistance values of the ballast resistors are sequentially decreased from the first ballast resistor to the nth ballast resistor, and n is an integer. According to the power amplification chip, the problem of junction temperature difference of different transistors can be solved, so that the overall performance of the power amplification chip is improved.

A semiconductor device is provided that includes a transistor located in a first device area and including a gate structure, a first source / drain region located on a first side of the gate structure and a second source / drain region located on a second side of the gate structure. The semiconductor device also includes a frontside source / drain contact structure contacting a topmost surface of the first source / drain region, a backside ballast resistor electrically contacting a bottommost surface of the second source / drain region, and a backside source / drain contact structure in contact with the backside ballast resistor.

The invention provides a semiconductor structure for electrostatic discharge protection and a manufacturing method thereof, and aims to solve the technical problem that local overheating failure is easily caused by non-uniform starting of electrostatic discharge current of an existing grid grounding NMOS (N-channel Metal Oxide Semiconductor) device. The semiconductor structure comprises a substrate, an active region, a grid, a source and a drain. The drain electrode comprises a first area where a refractory silicide layer is formed and a second area where no refractory silicide layer is formed in the width direction of the drain electrode. According to the manufacturing method, the structure is realized by selectively forming the refractory silicide barrier layer on the drain region and then carrying out a silicification process. According to the invention, the second region with high resistance is used as a ballast resistor, the current is forced to be uniformly distributed in an electrostatic discharge event, and the formation of local hot spots is effectively avoided, so that the electrostatic discharge endurance and reliability of the device are remarkably improved.

The application provides an arc heater ballast resistor fireproof fixing device. The arc heater ballast resistor fireproof fixing device comprises a metal frame and a ceramic fixing assembly for fixing the ballast resistor on the metal frame, the ceramic fixing assembly comprises a first ceramic fixing piece, a second ceramic fixing piece and a ceramic buckle, the ballast resistor has a bending part and a connecting part connected with the bending part, the metal frame has a hollow part corresponding to the bending part, the first ceramic fixing piece is fixed in the hollow part of the metal frame, the second ceramic fixing piece is fixed on the metal frame, and the bending part and the connecting part of the ballast resistor are fixed on the first ceramic fixing piece and the second ceramic fixing piece through the ceramic buckle respectively. The arc heater ballast resistor fireproof fixing device solves the fire risk caused by the sharp rise of the surface temperature of the ballast resistor under the abnormal condition of large current or cooling water supply, and has the advantages of simple structure, light weight and high reliability.

Semiconductor device comprising: - a semiconductor substrate (5) of a first conductivity type in which a cell region (1), a ballast resistance region (1a) being a region that is an outer edge of the cell region (1), and a termination region (2) surrounding the ballast resistance region (1a) are defined; - a first insulating film (9) arranged on a front surface of the semiconductor substrate (5), having a first opening (6a) in the cell region (1) and having at least a second opening (6b) in the ballast resistance region (1a); - a second insulating film (10) filled into the at least one second opening (6b); - a first impurity layer (7a) of a second conductivity type arranged on the front surface of the semiconductor substrate (5) below the first opening (6a);- a second defect layer (7b) of the second conductivity type, arranged on the front surface of the semiconductor substrate (5) below the at least one second opening (6b); and - a conductive film (11) arranged from the front surface of the first opening (6a) of the semiconductor substrate (5) to the termination region (2).

Structure comprehensive: a bipolar transistor comprising a collector region (24), an emitter region (28) and a base region (26); and a lateral ballast resistor comprising semiconductor material adjacent to the collector region (24), wherein the collector region (24) comprises a collector fin structure (25) of a first dopant type, the emitter region (28) comprises an emitter fin structure (29) of the first dopant type, the base region (26) comprises a base fin structure (27) of a second dopant type, and the lateral ballast resistor comprises lateral ballast fin structures (23) of the first dopant type adjacent to the collector fin structure (25).

IC structures including BPRs used for ESD ballasting are disclosed. An IC structure includes semiconductor structures of one or more transistors. A semiconductor structure may be a fin, nanowire, or nanoribbon of a semiconductor material. The IC structure also includes an electrically conductive layer coupled to the semiconductor structures, a power rail, and a support structure. The power rail is coupled to the electrically conductive layer by a via. The power rail is buried in a support structure. The combination of the power rail and the via constitutes a ESD ballasting resistor for the semiconductor structures. A resistance of the ESD ballasting resistor can be in a range from 5 to 20 ohms. The IC structure may include two or more power rails. A power rail may be arranged between two of the semiconductor structures. The power rails may form a meander structure with other components of the IC structure.

This invention relates to an IGBT device with latch-up resistance, belonging to the field of power semiconductor device technology. The invention proposes using a segmented N-type source region and segmented source contact vias, and controlling the magnitude of the introduced ballast resistor by adjusting the overlap area between the N-type source region and the source contact vias, thereby controlling the N-type source region potential during conduction and achieving latch-up resistance. The structure proposed in this invention, which reduces the latch-up risk of IGBT devices, employs a method of providing ballast resistance by controlling the electron flow path itself. This method is simple to implement, requires low equipment standards, eliminates the need for additional P-type injection, and effectively suppresses latch-up while improving short-circuit capability.