PD SOI (partially-depleted silicon on insulator) technology-based body grid coupling ESD (electro-static discharge) protection structure

Abstract

The invention discloses a PD SOI (partially-depleted silicon on insulator) technology-based body grid coupling NMOS ESD (n-channel metal oxide semiconductor electro-static discharge) protection structure, wherein a grid electrode in the structure adopts an H-shaped structure, the inner side and the outer side of an edge grid of an H-shaped grid adopt two body region P+ implantation, a drain region adopts N+ deep implantation, a silicon film on an SOI substrate is punched through, a source region adopts N+ shallow implantation, and some silicon film on the SOI substrate adopts the implantation, so that the body region P+ implantation is carried out at the outer side of the source region, and body region contact is led out, and some drain region baffles the silicide by an SAB (salicide block) layer, so that a ballast resistor can be formed. When the protection structure is used, the drain region is connected with a PAD, the body region at the outer side of the edge grid of the H-shaped grid is connected with the grid electrode, and the source region and the body region at the inner side of the H-shaped grid are grounded. According to the protection structure, the body region at the outer side of the edge grid of the H-shaped grid is connected with the grid electrode, so that a coupling circuit can be formed by sufficiently using a parasitic capacitor of a drain body and a parasitic resistor of a body region under the source region, and the grid electrode is coupled with a certain voltage, so that the starting voltage of the ESD protection structure can be reduced, the even conduction of the plurality of structures can be guaranteed, and the ESD protection capability can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to the field of electrostatic discharge (ESD) protection circuits based on PD SOI CMOS technology. Background technique [0002] With the continuous improvement of the integrated circuit manufacturing process, the length of the polysilicon gate is getting smaller and smaller, the thickness of the gate oxide is getting thinner, and the junction depth is getting shallower and shallower. The gate oxide breakdown, PN junction thermal breakdown, The problems of interconnection burning and potential damage are becoming more and more serious. ESD has become an urgent reliability problem in the field of integrated circuits. Therefore, ESD protection circuits have become the focus of research on the reliability of CMOS integrated circuits. Because SOI CMOS devices have the advantages of low power consumption, strong anti-interference ability, high integration, fast speed, str...

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Problems solved by technology

[0009] The technical problem solved by the present invention is to solve the problem of non-uniform conduction of multi-finger parallel GGNMOS caused by the turn-on voltage Vt1 being greater than the secondary breakdown voltage Vt2, and improve the ESD protection capability of multiple parallel GGNMOS transistors

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