37results about How to "Increase voltage margin" patented technology

A phase change memory device having an improved performance that minimizes cell degradation is presented. The phase change memory device includes: a cell array, a sense amplifier, a write driving unit, and a reference level selecting unit. The cell array has a phase change resistor is configured to read/write data. The sense amplifier is configured to compare a reference voltage with a sensing voltage received from the cell array. The write driving unit is configured to supply a driving voltage corresponding to write data to the cell array. The reference level selecting unit is configured to select a read reference voltage in a read mode so as to output the reference voltage, and to select a reference voltage corresponding to input data in a write verifying mode so as to output the reference voltage.

A non-volatile ferroelectric memory device senses a cell data at high speed. Preferably, the non-volatile ferroelectric memory device includes a plurality of cell array blocks, a plurality of sense amplifier units, a plurality of sense amplifier units, a plurality of local data buses, a global data bus, and a plurality of data bus switch arrays. Each of the plurality of cell array blocks has a hierarchical bit line architecture including sub bit lines and a main bit line group corresponding to a plurality of unit cells for storing differential data. The plurality of sense amplifier units, corresponding one-by-one to the cell array blocks, sense and amplify the differential data induced on the main bit line group during a sensing operation. The plurality of local data buses, corresponding one-by-one to the sense amplifier units, transfer the differential data outputted from the sense amplifier units and differential data to be transferred to the sense amplifier units. The global data bus, shared by a plurality of the local data buses, transfers the differential data. The plurality of data bus switch arrays selectively couple the local data buses to the global data bus.

A transistor is formed with a source ballast resistor that regulates channel current. In an LDMOS transistor embodiment, the source ballast resistance may be formed using a high sheet resistance diffusion self aligned to the polysilicon gate, and/or by extending a depletion implant from under the polysilicon gate toward the source region. The teachings herein may be used to form effective ballast resistors for source and/or drain regions, and may be used in many types of transistors, including lateral and vertical transistors operating in a depletion or an enhancement mode, and BJT devices.

The invention provides a voltage control oscillating circuit, which comprises an amplifying circuit provided with a first node, an amplifying circuit end current source, of which one end is connected with the first node and the other end is connected with grounding voltage(VGN), a latch circuit provided with a second node, a latch circuit end current source, of which one end is connected with the second node and the other end is connected with the grounding voltage, a load resistance, of which one end is electrically connected with the amplifying circuit and the latch circuit and the other end is electrically connected with power supply voltage(Vdd) and a current modulation circuit comprising a first PMOS switch, a second PMOS switch and a modulation circuit end current source, wherein the first PMOS switch is connected with the first node, the second PMOS switch is connected with the second node, one end of the modulation circuit end current source is connected with the first PMOS switch and the second PMOS switch, and the other end of the modulation circuit end current source is connected with the power supply voltage.

A method for driving plasma display panels (PDPs) includes dividing a plasma display panel having stripe ribs into at least two scanning regions. Each of the scanning regions has a plurality of scan and common electrodes, and these electrodes are arranged in an interlaced fashion according to an electrode arrangement sequence. Then, the emitting cells in each scanning region are addressed, and a scanning direction of each scanning region corresponds to the electrode arrangement sequence of the same scanning region.

A semiconductor memory device includes memory modules which have memories and a data bus which transfers data to the memory modules, in which the data bus comprises a low frequency band data pass unit which removes the high frequency component of the data and sends the data to the memory modules. The low frequency band data pass unit comprises a plurality of stubs which are connected to the data bus in parallel and are formed as printed circuit board (PCB) patterns. The low frequency band data pass unit comprises a plurality of plates that are connected to the data bus in parallel and are formed as PCB patterns. The low frequency band data pass unit has a shape in which parts having a wide width and parts having a narrow width are alternately connected. Therefore, without adding a separate passive device, the semiconductor memory device reduces the high frequency noise of data transferred through a data bus such that the voltage margin of the data improves, the cost for passive devices such as capacitors, is reduced, and the process for attaching the passive devices is simplified.

The invention discloses a field weakening control method for a built-in permanent magnet synchronous motor based on a torque feedforward control technology, which mainly comprises a stator flux adjustment module, a current data table, a current regulator, a pulse width modulation module, dq-[alpha][beta] transformation, Park transformation, an uncontrolled rectifier bridge and an inverter, and ischaracterized in that the stator flux adjustment module calculates an appropriate stator flux set value to serve as the output according to an input torque set value, DC bus voltage, motor speed and amodulation factor; the stator flux adjustment module comprises seven modules I-VII, wherein the module I is a one-dimensional table and records the corresponding minimum stator flux at different given torques. The field weakening control method realizes the maximization of torque output of the motor in a field weakening area through introducing a proportionality factor into stator flux adjustment, and ensures the stability of the torque at the same time. The factor automatically changes in size according to operating conditions of the current motor, the voltage margin is improved when the speed is high and the torque is low, the torque output capacity is improved when the speed is high and the torque is large, and thus the maximum utilization ratio of the DC bus voltage is achieved.

The disclosure relates to a voltage conversion device comprising a primary side module, a transformer module and a secondary side module which are sequentially connected, wherein the primary side module comprises a primary side switching unit, a primary side transformer unit, a primary side voltage equalization resistance unit and a primary side control unit which are sequentially connected and isconfigured to convert the first DC voltage input to the voltage input side into a first AC voltage; the transformer module is connected to the primary side transformer unit for converting the first AC voltage into a second AC voltage; the secondary side module comprises a secondary side transformer unit, a secondary side switching unit and a secondary side control unit which are sequentially connected and is configured to convert the second AC voltage into a second DC voltage and input the second DC voltage to the voltage output side. The device provided by the disclosure realizes DC-to-DC voltage conversion through mutual cooperation between three modules, and has the advantages such as high stability, high safety and high startup success rate.

A Plasma Display Panel (PDP) and its method of manufacture includes: a first substrate; a plurality of first discharge electrodes arranged on the first substrate; a second substrate arranged opposite to the first substrate and in parallel therewith; a plurality of second discharge electrodes arranged on the second substrate to cross the first discharge electrodes, the second discharge electrodes being adapted to be addressed with the first discharge electrodes and located on different levels; barrier ribs disposed between the first and second substrates to define discharge cells; and Red (R), Green (G), and Blue (B) phosphor layers coated on lateral sides of the barrier ribs. Address electrodes for discharge cells coated with R, G, and B phosphor layers are positioned on different levels, so that address voltages become more uniform regardless of the color of a phosphor layer.

Disclosed are novel methods and apparatus for efficiently providing equalization in single-ended chip-to-chip communication. In an embodiment, a method of adjusting signal levels to provide improved communication between a sender device and a receiver device is disclosed. The method includes providing a plurality of voltage dividers. The plurality of voltage dividers may be coupled to each other to provide a reference voltage to the receiver device. The method further includes providing a storage device to store previously received data by the receiver device and providing a controller to selectively activate the plurality of voltage dividers.

The invention provides a modulation driving output stage circuit. The modulation driving output stage circuit comprises a switch control circuit part and a current generation circuit part. The modulation driving output stage circuit receives a pair of difference input voltages and outputs a pair of difference output currents. The current generation circuit part comprises a first transistor, a second transistor, a first reference current source and a second reference current source. The switch control circuit part comprises a third transistor, a fourth transistor, a first phase inverter and a second inverter. The first difference voltage in the pair of difference input voltages is input into the grid electrode of the third transistor through the first phase inverter, the second difference voltage in the pair of difference input voltages is input into the grid electrode of the fourth transistor through the second phase inverter, the drain electrode of the second transistor outputs the first difference current in the pair of difference output currents, and the drain electrode of the first transistor outputs the second difference current in the pair of difference output currents. The modulation driving output stage circuit can increase the voltage margin of a driver.

The embodiment of the invention provides a random access memory bit cell, a random access memory and an electronic chip, belonging to the field of storages, and aiming at solving the problems of reliability and power consumption of the memory. The random access memory bit cell comprises at least one power supply, a first write-in wire, a second write-in wire, a write-in bit wire, a reading wire, a reading bit wire, a reading module, an asymmetrical storage module and a conduction module. The random access memory consists of the random access memory bit cells with preset number; the electronic chip comprises the random access memory. The reliability and the power consumption of the random access memory can be optimized.

The invention provides a silicon carbide power semiconductor module device integrated with a buffer circuit. An active buffer circuit is integrated in a single-phase half-bridge, single-phase full-bridge or three-phase bridge type silicon carbide power semiconductor module, so that the switching loss of the silicon carbide power semiconductor module can be reduced, the oscillation and damping loss can be reduced, the voltage peak can be reduced, the silicon carbide power semiconductor module can work at a higher voltage, or a low-voltage-grade chip is selected to reduce the conduction loss, and the efficiency of the silicon carbide power electronic system is improved.