A non-volatile ferroelectric memory device senses a
cell data at high speed. Preferably, the non-volatile ferroelectric memory device includes a plurality of
cell array blocks, a plurality of
sense amplifier units, a plurality of
sense amplifier units, a plurality of local data buses, a global data
bus, and a plurality of data
bus switch arrays. Each of the plurality of
cell array blocks has a hierarchical
bit line architecture including sub bit lines and a main
bit line group corresponding to a plurality of unit cells for storing differential data. The plurality of
sense amplifier units, corresponding one-by-one to the cell array blocks, sense and amplify the differential data induced on the main
bit line group during a sensing operation. The plurality of local data buses, corresponding one-by-one to the sense
amplifier units, transfer the differential data outputted from the sense
amplifier units and differential data to be transferred to the sense
amplifier units. The global data
bus, shared by a plurality of the local data buses, transfers the differential data. The plurality of data bus switch arrays selectively couple the local data buses to the global data bus.