The application provides a power device, which comprises an active region, and the active region has a plurality of
cell structures arranged in parallel. A single
cell structure comprises a P-type substrate, an epitaxial layer, three trenches, a
gate oxide layer, a polysilicon column, an N-type emitter region, an emitter
metal layer and an insulating layer. The epitaxial layer is formed on the P-type substrate, and the epitaxial layer comprises an N-type epitaxial layer and a P-type
body region formed on the top of the N-type epitaxial layer. The three trenches extend downward from the surface of the epitaxial layer into the N-type epitaxial layer, and the
gate oxide layer is formed on the surface of the epitaxial layer and the wall surface of the trenches. The polysilicon filled in the three trenches forms three polysilicon columns, the middle polysilicon column is a real gate, and the two sides are false gates. The N-type emitter region is formed in the P-type
body region and located on both sides of the top of the real gate, and the emitter
metal layer is formed above the epitaxial layer, electrically connected with the N-type emitter region and the false gate, and insulated and separated from the real gate. The power device of the application can strengthen the charge balance effect, relieve the local
electric field concentration, and reduce the
conduction loss and on-state
voltage.