988 results about "Conduction loss" patented technology

An LC parallel resonance circuit is connected in series with the power supply side of the antenna conductor portion. The antenna conductor portion is configured so as to resonate at a frequency slightly lower than the center frequency in the higher frequency band of two frequency bands for transmitting and receiving radio waves. The LC parallel resonance circuit is configured so as to resonate substantially at the center frequency in the lower frequency band for transmitting and receiving a radio wave and be capable of providing to the antenna conductor portion a capacitance for causing the antenna conductor portion to resonate at the center frequency in the higher frequency band. Thus, a circuit for changing the upper and lower frequency bands is not needed. Such a change-over circuit, which is complicated, causes problems in that the conduction loss increases, and the antenna sensitivity deteriorates. Without need of the change-over circuit, the conduction loss can be reduced, the antenna sensitivity can be enhanced and costs can be reduced.

A resonant switched power converter having switching frequency controlled in response to an output voltage thereof achieves over-current protection such as at start-up or under short circuit conditions using a resonant tank circuit which provides a notch filter in addition to a band pass filter. A additional band pass filter provided in the resonant tank circuit achieves increased power transfer to a load and reduced circulating resonant currents and conduction losses. The inductances of the preferred LCLCL tank circuit or other tank circuit with two pass band filters and a notch filter may be integrated into a single electrical component.

A single-stage input-current-shaping (S<2>ICS) flyback converter achieves substantially reduced conduction losses in the primary side of the S<2>ICS flyback converter by connecting a bypass diode between the positive terminal of a full-bridge rectifier and the positive terminal of an energy-storage capacitor. An effective current interleaving between an energy-storage inductor and the bypass diode is thus obtained in the S<2>ICS flyback converter around the peak of the rectified line voltage, resulting in a significantly reduced input-current ripple and reduced current stress on the switch. Further, by rearranging the rectifiers in the ICS part of the S<2>ICS flyback converter in such a way that the energy-storage capacitor and the ICS inductor are connected to the ac line voltage through only two rectifiers, one diode forward-voltage drop is eliminated, which results in a substantially reduced conduction loss in the primary-side rectifiers.

The invention relates to a high power factor DCM Boost PFC converter comprising a main power circuit and a control circuit. The main power circuit comprises an input voltage source vin, an EMI filter, a diode rectification circuit RB, a Boost inductor Lb, a switch tube Qb, a diode Db, an output capacitor Co and a load RLd. The high power factor DCM Boost PFC converter is characterized in that the control circuit adopts an output signal which adopts duty ratio as changing rule to drive the switch tube Qb. Adopting the varying duty ratio control, the high power factor DCM Boost PFC converter can improve the PF value to about 1 in the AC input voltage range of 90-265 V, increase the inductance capacity, obviously decrease the inductive current ripple, obviously reduce the effective value of the inductive current and correspondingly reduce the effective value of the current of the switch tube, has high input power factor and small output voltage ripple and contains less input current harmonic waves. The conduction loss of the high power factor DCM Boost PFC converter is reduced, and the efficiency is improved.

A hybrid switch comprising two semiconductor switches connected in parallel but having different voltage drop characteristics as a function of current facilitates attainment of zero voltage switching and reduces conduction losses to complement reduction of switching losses achieved through zero voltage switching in power converters such as high-current inverters.

The invention relates to a digital control device and method for an LLC (logical link control) synchronously-rectified resonant converter. The device comprises a digital signal processor, a primary high-frequency driving circuit, a current sampling detection circuit, a voltage sampling detection circuit and a secondary high-frequency driving circuit, wherein the digital signal processor judges an operation area of a circuit according to an output voltage fed back by the voltage sampling detection circuit, after the circuit performs three-pole two-zero compensation, the values of an on-chip period register are respectively changed so as to generate high-frequency driving signals which are then output to the primary and secondary high-frequency driving circuits by the digital signal processor; the current sampling detection circuit detects a secondary output current which is then output to the digital signal processor, then the digital signal processor judges whether an overloading or overcurrent phenomenon (generated in the process of area switching) occurs according to the size of the current so as to cut off the primary and secondary high-frequency driving circuits in time. In the invention, the LLC resonant converter is subjected to the following digital control by a digital signal processing chip-peripheral timer combined circuit: the advanced conduction of secondary synchronous rectifying tubes is realized by the design of software/hardware auxiliary circuits, and the control on secondary driving signals is performed by adding a 555 timer, so the application of a timer in a DSP (digital signal processing) chip is reduced, thereby effectively solving the problem of conduction loss of synchronous rectifying tubes introduced in the process of underloading in the traditional control strategy; and the application of a PWM (pulse-width modulation) port of the digital signal processing chip is reduced, thereby improving the reliability of the whole device.

The invention relates to a silicon-carbon composite negative pole material preparation method and a lithium ion battery. The preparation method comprises putting nanometer silicon and graphite micro-powder into a ball mill, carrying out ball milling uniform dispersion in an organic solvent environment, carrying out vacuum drying, putting the dried mixture and asphalt into a cone-type mixer, carrying out coarse mixing, putting the mixed powder subjected to coarse mixing into a mechanical fusion machine, carrying out mechanical fusion, carrying out heat treatment in an inert gas protective atmosphere and carrying out cooling to obtain the silicon-carbon composite negative pole material. The preparation method carries out asphalt softening coating on nanometer silicon so that silicon particle and electrolyte direct contact is avoided, a capacity reduction rate is delayed, a lithium ion diffusion path is shortened, an electrode material electron conduction loss is avoided, and first charge-discharge efficiency, a charge-discharge electric capacity and cycle performances are improved. Before coating, nanometer silicon is dispersed through graphite micro-powder so that it is avoided that in asphalt coating, nanometer silicon aggregation causes local capacity excess and nanometer silicon is uniformly dispersed.

The invention relates to a junction termination structure of a transverse high-pressure power semiconductor device, belonging to the technical field of semiconductor power devices. An N-type drift region at a curvature termination of the transverse high-pressure power semiconductor device is shortened in length to ensure that the N-type drift region is spaced with a P-well region by a certain displace, wherein the spaced part is replaced by a P-type substrate, which is equivalent that additional electric charges of the P-type substrate are introduced so that the peak value of an electric field at a pn junction formed the original P-well region and the N-type drift region is reduced, meanwhile, a new peak value of the electric field is introduced at a pn junction formed by the P-type substrate and the N-type drift region, the radius of curvature of the curvature terminal is increased, the excessive concentration of a power line is avoided, and the puncture voltage of the device is increased, wherein the surface of the N-type drift region also can be combined with a surface RESURF structure or an ultra-junction structure. The junction termination structure has the advantages of being capable of decreasing the width of the curvature terminal of the device, saving the layout area of the device and being compatible with a CMOS (Complementary Metal-Oxide-semiconductor Transistor) process, and can be used for manufacturing the transverse high-pressure power device with the advantages of excellent performance, high voltage, high speed and low conduction loss.

In accordance with the present invention, a switching converter includes two transistors Q1 and Q2 parallel-connected between two terminals. Transistor Q1 is optimized to reduce the dynamic loss and transistor Q2 is optimized to reduce the conduction loss. Q1 and Q2 are configured and operated such that the dynamic loss of the converter is dictated substantially by Q1 and the conduction loss of the converter is dictated substantially by Q2. Thus, the tradeoff between these two types of losses present in conventional techniques is eliminated, allowing the dynamic and conduction losses to be independently reduced. Further, the particular configuration and manner of operation of Q1 and Q2 enable reduction of the gate capacitance switching loss when operating under low load current conditions.

The invention relates to an integrated circuit technology, in particular to the application of a load adaptive sectional driving circuit in a buck voltage stabilizing circuit (also called BUCK circuit). The invention discloses an adaptive sectional driving direct current to direct current (DC-DC) converter. According to the adaptive sectional driving DC-DC converter, m p-channel metal oxide semiconductor (PMOS) power tubes and N-channel metal oxide semiconductor (NMOS) power tubes which are connected in parallel, form a switching circuit to drive different amount of power tubes to switch according to different load current magnitudes; less power tubes are driven under a light load condition, equivalently, the power of the power tubes is lowered, so that the driving loss and switching loss are reduced under the light load condition. Furthermore, the driving way of the power tubes is changed; and the switch-on amount of the power tubes is changed by detecting the change of load current, so that the sum of the conduction loss and driving loss of the power tubes is minimized; and therefore, the efficiency of the DC-DC converter is increased, in particular the efficiency under light load. The adaptive sectional driving DC-DC converter is particularly suitable for the buck voltage stabilizing circuit.

A voltage source inverter generating a poly phase AC signal is provided that includes an SVPWM controller. The controller is adapted to modify the switching pattern at low sine-wave frequencies creating a more even distribution of the conduction losses. The switching pattern periodically changes the sequence (or rotational sense) of the space vector components from clock-wise to counter-clock-wise direction, and vice-versa.

The invention discloses an online loss calculation method for a modular multilevel converter (MMC), and belongs to the field of power transmission and distribution. The method comprises the following steps of: 1) calculating the conduction loss of two insulated gate bipolar transistors (LGBT) and two flywheel diodes in each sub-module (SM); 2) calculating the switching loss of the two IGBTs and the reverse recovery loss of the two flywheel diodes in each SM; and 3) calculating related loss by using a loss calculation module. The method has the advantages that: 1, the complexity of manual measurement and calculation is effectively avoided when the MMC has a great number of modules, workload is greatly reduced, and the method is fast and convenient; 2, the online calculation of the loss of the MMC is realized, and the method is wide in application range, and can be applied to the loss calculation of an MMC system in any operating state; and 3, modular packaging is facilitated, a floor area is saved, the utilization rate of resources is increased, and the output of a platform comprises various kinds of loss and loss ratios, so that the method is direct and clear, and staff can conveniently observe the running state of the system at any time.

The invention discloses an SOI-LIGBT (silicon on insulator-lateral insulated gate bipolar transistor) device with a split anode structure, belonging to the technical field of semiconductor power devices. The SOI-LIBGT device comprises a substrate layer, a buried oxide layer, an N-base region, a cathode region, an anode region and a gate region, wherein the cathode region and the anode region area are positioned on the two sides of the N-base region; and the gate region is positioned on the cathode region. The anode region is split into a first anode region and a second anode region by an isolation groove, but the first anode region and the second anode region are still kept in electric connection. The first anode region ensures high hole injection efficiency when the device works; and the second anode region has a function of eliminating the negative differential resistance (NDR) area when the device is opened and provides an electron extraction channel at the turn-off transient state of the device. Through the invention, the NDR area introduced into positive characteristics in the anode short-circuit structure is eliminated on one hand, and on the other hand, the on resistance is increased while the turn-off speed is increased, and a good eclectic relationship between the conduction loss and the turn-off loss is obtained; and moreover, the manufacturing process of the device is compatible with a conventional power integrated circuit process, and additional steps or cost is not increased.

A power converter having a two stage boost circuit and a small boost converter. The main power flow for the power converter is via the two stage booster circuit having a single switch. The voltage spike of the switch is clamped by a diode and a capacitor. The energy at the capacitor is transferred to the power converter's output terminals by the small boost converter. The two stage boost converter topology enables the use of much lower voltage and Rdson MOSFET switches so as to reduce cost, switch conduction loss and turn on loss.

The invention relates to an optimal current waveform controlling method for a current type two-way DC-DC convertor, and belongs to the power electronics field of the high frequency switch power source direction. According to the method, by simultaneously adjusting the duty ratio of a low voltage side and the conductive logic of two bridge arm switching tubes of a high voltage side, so that when the voltage of the low voltage side of a transformer reaches zero, a leakage inductance current of the transformer maintains the cocurrent change, the dynamic change of the leakage inductance current is completed so that the maximum peak value can be reached, when the voltage of the low voltage side of a transformer does not reach zero, the peak value of the leakage inductance current is guaranteed to be minimum under the condition of transmitting the same power. Therefore, the current-circulation loss and the conduction loss of circuits and the switching tubes and the current stress of power devices are greatly reduced, and the efficiency and performance of the circuits are improved. Meanwhile, although conducting logics of secondary side switching tubes during a boost mode and a buck mode are slightly different, the seamless switching can be achieved between the boost mode and the buck mode, so that a closed loop real-time control on the system can be easily achieved.