498 results about "Conduction loss" patented technology

The invention provides an intelligent calculation method and system for the loss of a semiconductor device, and the method comprises the steps: firstly collecting the operation electrical parameters of the semiconductor device and the temperature parameters of a plurality of temperature measurement points of a surrounding environment in real time, and forming a synchronous operation data set with a timestamp; a parameterized body loss model is established based on a semiconductor physical principle, and a relationship between conduction loss and switching loss along with changes of electrical parameters and junction temperature is described. A parameterized thermal coupling effect model is established according to the physical layout and the heat transfer path of the control cabinet, and a thermal resistance parameter to be identified is used to describe the heat transfer relationship between the device and other heat sources. And identifying and updating model parameters by adopting a parameter identification algorithm and utilizing the synchronous operation data set to obtain a self-adaptive model parameter set reflecting the current working condition and the coupling state. And in combination with the synchronous operation data set and the adaptive model parameter set, a real-time loss value of the semiconductor device is calculated through the body loss model and the thermal coupling effect model, and accurate loss evaluation under the actual working condition is realized.

The invention provides an electric field enhancement type shield gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which comprises a substrate, an epitaxial layer formed on the substrate, a gate trench formed on a cellular region on the epitaxial layer, and a first gate dielectric layer formed at the bottom of the gate trench and a first polycrystalline silicon layer located in the first gate dielectric layer, a P-type epitaxial layer is formed on the first gate dielectric layer and the first polycrystalline silicon layer, and an isolation dielectric layer is formed on the P-type epitaxial layer; a second gate dielectric layer is formed on the side wall of the residual gate trench, and a second polycrystalline silicon layer is formed in the residual gate trench; a well region and a source region of a cellular region are formed on the epitaxial layer, and a contact hole dielectric layer is formed on the epitaxial layer; and contact holes communicated with the well region are formed on the contact hole dielectric layer and the epitaxial layer below the contact hole dielectric layer. By adding the shield grid P-type epitaxial layer, the electric field intensity in the middle of the drift region is effectively improved, the breakdown voltage is improved, and meanwhile, the conduction loss can be further reduced by adjusting epitaxy.

The invention provides an asymmetric trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the silicon carbide substrate to form a drift layer; performing ion implantation to form a freewheeling region; forming a barrier layer, etching, carrying out ion implantation, and forming a masking layer, a P-type well region and an N-type source region; re-forming a barrier layer, etching, etching the drift layer and the masking layer to form a groove, and oxidizing to form an insulating dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, the drift layer is etched to the upper side face of the follow current region, metal is deposited, and a source electrode metal layer is formed; according to the invention, the body diode conduction loss of the device can be effectively reduced, the reverse recovery speed of the device can be improved, and the gate reliability and the source large current impact reliability of the device can be improved.

The invention discloses an efficient anti-freezing and anti-blocking integrated induction heating system and method for an oil and gas pipeline, belongs to the technical field of anti-freezing and anti-blocking of oil and gas pipelines, and aims at solving the problems that in the prior art, heating efficiency is low, energy consumption is huge, heating uniformity and adaptability are poor, the system integration degree is low, and the intelligent degree is insufficient. Comprising the steps of S1, induction heating unit arrangement and power management; s2, real-time temperature monitoring and data acquisition; s3, intelligent data analysis and precise heat management; the electromagnetic induction heating principle is adopted, the induction coil directly heats the pipeline and the internal medium, heat conduction loss and heat energy radiation loss of heating modes such as traditional resistance wires and heat tracing bands are reduced, the intelligent power management module can optimize power supply and power adjustment, and the self-adaptive environment and load adjustment strategy is combined, so that the self-adaptive load adjustment is achieved. The heating power can be automatically adjusted according to the environment temperature and the pipeline load, the anti-freezing and anti-blocking effect is guaranteed, meanwhile, energy consumption is remarkably reduced, and the burden of an electric power supply system is relieved.

The invention relates to the technical field of semiconductors, in particular to a source heterojunction contact semiconductor structure and device and a manufacturing method, the semiconductor structure comprises a gate structure, a body region structure, a source structure and a drain structure, and the source structure comprises a polycrystalline silicon source contact layer; the semiconductor structure comprises a body region structure and a polycrystalline silicon source contact layer, the body region structure is surrounded by the gate structure, a source contact region is arranged in the body region structure, the polycrystalline silicon source contact layer is in contact with the source structure through the source contact region so as to form a heterojunction diode with the source structure, and the heterojunction diode is a freewheeling diode of the semiconductor structure. The drain electrode structure is located on one side, back to the gate electrode structure, of the body region structure; the semiconductor structure can be a SiC MOSFET structure, reverse conduction voltage drop during follow current of the SiC MOSFET can be greatly reduced, and conduction loss and loss caused during switching are reduced.

The invention provides a switching power supply device comprising a transformer which comprises a primary winding and a secondary winding and is used for converting an input voltage into an output voltage; the primary switching tube is connected with the primary winding and controls the on-off of the primary winding; the rectifying unit is connected with the secondary winding and rectifies the output of the secondary winding, and the rectifying unit comprises a semiconductor field effect transistor; the control unit is connected with the rectification unit and generates a control signal so as to control the switch of the semiconductor field effect transistor through the control signal; the current detection unit detects the output current and generates a current detection signal; the control unit receives the current detection signal and adjusts the control signal according to the current detection signal. According to the device, the COOLMOS with small internal resistance and high switching speed is adopted, the switching loss is reduced, the switching signal is dynamically adjusted by the control unit according to the real-time output current, the rectification conduction loss and the switching noise are reduced, the power supply conversion efficiency is improved, and the electromagnetic interference is reduced.

The invention discloses a fan speed regulation circuit, including a feedback circuit for obtaining the motor temperature and adjusting the fan enable signal and then outputting it; a compensation circuit 1 for obtaining the fan enable signal and the fan speed and then outputting a level signal after comparison; and a compensation circuit 2 for obtaining the level signal and adjusting the fan speed. The invention realizes dynamic regulation, does not occupy DSP resources, uses a PWM control chip to adjust the fan PWM control signal, and then achieves the purpose of speed regulation, has a simple circuit, and requires fewer power devices; has a high switching frequency, is easy to be continuous in current, has fewer harmonics, and has relatively small losses and heat generation; has good low-speed performance, high steady-speed accuracy, and a wide speed regulation range; the power switch device works in a switching state, has a small conduction loss, and when the switching frequency is appropriate, the switching loss is also small, so the efficiency is high.

The utility model provides a trench gate silicon carbide VDMOS with low on-resistance. The trench gate silicon carbide VDMOS is characterized in that the lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate; the lower side of the P-type source region is connected to the upper side of the drift layer; the freewheeling region is connected to the drift layer, and the freewheeling region is connected to the P-type source region; a groove is formed in the follow current area, and a masking layer is arranged at the bottom of the groove; a P-type well region and an N-type source region are arranged in the follow current region, and the upper side surface of the P-type well region is connected to the lower side surface of the N-type source region; the lower portion of the gate dielectric layer is arranged in the groove, the outer side of the gate dielectric layer is connected with the N-type source region and the P-type well region, and the lower side face of the gate dielectric layer is connected to the upper side face of the masking layer; a groove is formed in the gate dielectric layer; the gate metal layer is arranged in the groove; the source electrode metal layer is respectively connected with the P-type source region, the follow current region and the N-type source region; the drain metal layer is connected to the lower side surface of the silicon carbide substrate; the on-resistance of the device can be effectively reduced, the body diode conduction loss of the device is reduced, and the switching speed of the device is improved.

The invention discloses a fractional order second harmonic current suppression method for a single-phase dual-mode boost inverter, and the method comprises the steps: regulating and controlling the bus voltage of the single-phase inverter into a partial sine waveform and a constant direct waveform through dual-mode control, and enabling a front-stage Boost circuit to work at a high frequency and a rear-stage inverter to work at a low frequency in a partial sine waveform interval of the bus; and in a bus constant direct waveform interval, the front-stage Boost circuit works at low frequency, and the rear-stage inverter works at high frequency. The dual-mode control does not need to maintain the bus voltage at a relatively high constant value, so that the required bus capacitance is greatly reduced, the size of the device is reduced, and meanwhile, the switching and conduction loss is reduced. In addition, the fractional order second harmonic current suppression branch circuit is formed by connecting virtual capacitors Cfoc and C1 in series, the virtual capacitor Cfoc is composed of an inductor Lb, a capacitor C2 and half-bridge switching tubes Sb and Sc, and when the instantaneous power of the fractional order suppression branch circuit and the secondary pulsating power output by the inverter are equal in amplitude and complementary in phase, the inverter is switched on. And the complete suppression of the input second harmonic current can be realized.

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device includes a semiconductor body including a first surface, a second surface, a first device region, and a second device region; the first device region comprises a well region, a first region and a channel layer, and the first region is in contact with the channel layer; a gate trench; a first insulating layer; a first trench located in the second device region; the second device region further comprises a second insulating layer and a filling layer; a trench gate; an interlayer insulating layer; a Schottky metal layer; a drain electrode; and a source electrode. According to the technical scheme of the embodiment of the invention, the depletion type semiconductor device is formed and is in a conducting state and a cut-off state in a normal state, negative voltage needs to be applied between the grid electrode and the source electrode to cut off the channel, the response can be faster, the current circulation can be controlled, and the conducting loss is smaller. And a Schottky structure is integrated, so that the forward conduction voltage drop of the device is reduced, and the energy loss of the device in a reverse follow current state is reduced.

The invention relates to a low-channel-resistance SiC VDMOSFET device and a manufacturing method thereof, a conducting channel of the low-channel-resistance SiC VDMOSFET device comprises a laminated channel region, the laminated channel region is composed of n groups of P-type channel layers and N-type channel layers which are sequentially laminated, and n is larger than or equal to 1. According to the structure, accurate regulation and control of channel doping concentration and distribution can be realized. Moreover, the effective conductive depth of the channel is obviously increased by the multilayer conductive channel formed by the laminated channel region structure. The characteristic effectively weakens the interference of coulomb scattering, surface roughness scattering and other main scattering mechanisms on the channel carrier transport process, and further significantly improves the mobility of the carriers in the channel. According to the invention, the on-resistance is effectively reduced while the low leakage current of the device is ensured, so that the conduction loss is reduced, and the energy conversion efficiency is improved.

The embodiment of the invention relates to the technical field of electronic equipment, and provides an anti-interference structure, a shell assembly and electronic equipment, the anti-interference structure comprises an antenna, a camera module and a conductive part, and the conductive part is located in a space between the antenna and the camera module. Electromagnetic waves radiated by the antenna can excite a first standing wave propagating along a first direction on the conductive part, the first standing wave comprises a first electric field, the first electric field can enable the conductive part to generate a first current conducted along the first direction towards one side of the first standing wave, and the anti-interference structure comprises a first conduction loss part; the first conduction loss part is located on the side, facing the first standing wave, of the conductive part, and the first conduction loss part is made of a current loss material; or the material of the part, facing one side of the first standing wave, of the conductive part is a current loss material. According to the anti-interference structure, the shell assembly and the electronic equipment provided by the embodiment of the invention, the problem of interference of the first standing wave on the camera module is effectively improved.

The invention discloses a planar gate dual-control electrode 4H-SiC composite transistor structure which comprises a plurality of cell structures connected in parallel, each cell structure comprises an n buffer layer on a 4H-SiC n + substrate, an n-drift region, an n carrier expansion layer and p body regions in the two sides of the n carrier expansion layer, each p body region is of a mesa structure, an n + source region and a p + region are arranged in the upper part and the lower part, and a gap is formed between the n + source region and the p + region; gate oxide layers and polycrystalline silicon layers are arranged on the surfaces of the n carrier expansion layer, the p body regions on the two sides and part of the n + source region; a plane grid G is arranged on the surface of the polycrystalline silicon layer; a source S is arranged on the surface of the n + source region; a base B is arranged on the surface of the p + region; a drain electrode D is arranged on the back surface of the 4H-SiC n + substrate; the cellular structure is in bilateral symmetry with the planar grid G as the axis, equivalently, the VDMOS and the BJT are connected in parallel, the VDMOS is located in the center, and the BJT is located on the outer side. According to the invention, the conduction loss of the device can be reduced, the anti-short-circuit capability is improved, and the influence of a body diode is eliminated.

The invention relates to a contacting device for connecting a plurality of battery cells (1), the contacting device having two current paths, which are electrically isolated from one another, and having receptacles (2) for battery cell end portions, wherein a first conductor (3a, 3b, 3c) for electrically contacting the positive terminals of the battery cells (1) in parallel forms the first current path and a second conductor (4a, 4b, 4c) for electrically contacting the negative terminals in parallel forms the second current path. In order to allow, despite a simple structure and a compact design, reliable parallel and series interconnection of the battery cells with the least possible conduction losses, an electrically insulating carrier plate (7) is arranged between the two conductors (3a, 3b, 3c, 4a, 4b, 4c), through which carrier plate, at least in part, a plurality of electrical connectors (8) in a distributed arrangement extend for the purposes of contacting, in series, the conductors (3a, 3b, 3c, 4a, 4b, 4c) opposite the carrier plate (7).

The utility model provides a silicon carbide VDMOS with high drain voltage impact resistance. A drift layer is connected to a silicon carbide substrate; a current sharing layer and a plurality of masking layers are arranged in the drift layer, the masking layers are located above the current sharing layer, and the multiple masking layers are uniformly arranged at intervals; the N-type region is connected to the drift layer; the P-type well region is connected to the N-type region, the P-type well region is connected to the drift layer, and an N-type source region is arranged in the P-type well region; the insulating dielectric layer is connected with the drift layer, and is connected to the P-type well region and the N-type source region; a groove is formed in the insulating medium layer; the gate metal layer is arranged in the groove; the source metal layer is respectively connected with the N-type region, the P-type well region and the N-type source region; the drain metal layer is connected to the silicon carbide substrate; the drain voltage impact resistance of the device is improved, the gate-source capacitance of the device is reduced, the switching speed of the device is improved, the switching loss of the device is reduced, the body diode conduction loss of the device can be reduced, and the reverse recovery speed of the device is improved.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a super junction metal oxide semiconductor field effect transistor, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, and is characterized in that the semiconductor epitaxial layer specifically comprises two P well layers, two P + layers, two N well layers, an N substrate layer and an N drift layer; a beam waist N-layer is formed in the N drift layer through ion implantation; the girdling N-layer is composed of an upper half area and a lower half area, and the profile of the section of the girdling N-layer is in the shape that the upper end and the lower end are thick and the middle is thin. The gradient doped N-layer with the waist-shaped cross section is formed in the N drift layer, electric field distribution is optimized, the longitudinal electric field supporting capacity is enhanced in the middle thin and narrow area, and the breakdown voltage is improved; a transverse conduction path is expanded in thick areas at the two ends, so that the specific on-resistance is remarkably reduced, and high-voltage tolerance and low conduction loss are synchronously realized.

The invention relates to the technical field of converter control, and provides a loss optimization control method for a modular multilevel converter and related equipment, and the method comprises the steps: solving an expression of the average conduction loss and an expression of the average switching loss of a target modular multilevel converter; according to the expression, the positive correlation between the loss and the absolute average value of the bridge arm current is obtained through analysis, and the expression of the absolute average value of the bridge arm current is obtained; according to the positive correlation, loss optimization is equivalent to optimization of the absolute average value of the bridge arm current, and the optimal value range of the initial phase angle when the absolute average value of the bridge arm current is minimized is analyzed; according to the optimal value range of the initial phase angle, calculating an optimal initial phase angle and an optimal double frequency circulation component when the absolute average value of the bridge arm current is minimized; and controlling the target modular multi-level converter according to the optimal double-frequency circulation component and the optimal initial phase angle. According to the method, the optimization precision can be improved while loss optimization is realized.

The SiC JFET structure comprises a drain electrode metallization layer, an N + substrate layer, an N-drift region, a P first gate region, an N current expansion region, a P second gate region, an N + source region, a gate electrode metallization layer, an insulating dielectric layer, a source electrode ohmic contact layer, a source electrode Schottky contact layer and a source electrode metallization layer. The P first gate regions are embedded in the upper surface of the N-drift region, the gap between the two P first gate regions forms a vertical conductive channel structure, and the source Schottky contact layer is located right above a channel to form a Schottky diode structure, so that the conduction loss during follow current of the device can be effectively reduced; meanwhile, the gate metallization layer is located at the bottom of the gate trench and directly connected with the P first gate region, the gate metallization layer is isolated from the source metallization layer through the insulating dielectric layer in the gate trench, and the device has the advantages of being small in reverse blocking leakage current, high in reliability and the like.

The invention belongs to the technical field of power semiconductors, and relates to a 1200V SiC trench-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with a super junction and shield gate technology, which comprises an N + substrate layer, a drift region positioned above the N + substrate layer, and a trench gate structure and a source structure positioned above the drift region, compared with a conventional SiC trench type MOSFET with a P-type shielding layer, the SiC trench type MOSFET with the P-type shielding layer has the advantages that the peak electric field of the gate oxide layer is reduced, and the reliability of the device is ensured; the drift region adopts a super-junction structure, so that the electric field distribution is optimized, the blocking capability of the device is improved, the high doping concentration of the drift region can be adopted while the high breakdown voltage is maintained, the specific on-resistance of the device is remarkably reduced, and the conduction loss of the device is reduced; a shield gate structure is adopted, and the overlapping area of the gate and the drain is reduced, so that the gate-drain capacitance and the gate-drain charge are reduced, the switching speed of the device is improved, and the dynamic loss of the device is reduced. The performance is excellent in the high-voltage and high-frequency field.

The invention provides an anti-surge-voltage planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer on the drift layer, and performing etching and ion implantation to form a protection region, a current sharing region, a second P-type well region, a Schottky region, a first P-type well region and a lug boss; a barrier layer is formed again, etching and ion implantation are carried out, and an N-type source region is formed; forming a barrier layer again, etching and depositing to form an insulating medium layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; the method comprises the following steps: preparing a source electrode metal layer, re-forming a barrier layer, etching, depositing metal, forming a source electrode metal layer, removing the barrier layer, and completing preparation. The reliability of the device is improved, the conduction loss of the device is reduced, and the surge voltage resistance is improved.

The invention belongs to the technical field of power electronics, and relates to a high-side-ratio non-isolated hybrid switched capacitor converter which is used for direct 48V-1V power conversion of a data center and comprises switching tubes S1 to S38, flying capacitors C1 to C15, inductors L1 to L8, an input end Vin, an output end Vout and a grounding end. The switch tubes S1-S6 and the flying capacitors C1-C3 form a 4: 1 switched capacitor buck converter part; the switch tubes S7-S38, the flying capacitors C4-C15 and the inductors L1-L8 form a voltage-adjustable multi-channel mixed buck converter; mixing of the pre-buck converter and the voltage-adjustable buck converter is achieved through the exchange bus, the advantages of the pre-buck converter and the voltage-adjustable buck converter can be well fused, the defects of the pre-buck converter and the voltage-adjustable buck converter can be overcome, a bus decoupling capacitor is not needed, and the number of switches can be reduced. According to the multi-channel mixed buck converter, a capacitance channel is added, the conduction loss of an inductance channel is reduced, ripples are reduced, the duty ratio is increased, and the voltage stress of a switching tube is reduced; the hybrid switched capacitor converter has the advantages of being large in transformation ratio, high in power density and small in device stress.

The invention provides a grid driving improvement circuit and a motor driving system. The grid driving improvement circuit comprises a driving circuit, a first resistor, a second resistor, a diode, a third resistor, a first capacitor, a first inductor and an IGBT tube. The input end of the driving circuit is connected with a power supply, the output end of the driving circuit is connected with the first end of the first resistor and the first end of the second resistor, the second end of the first resistor is connected with the anode of the diode, and the second end of the second resistor is connected with the cathode of the diode, the first end of the first inductor and the first end of the third resistor. The second end of the third resistor is connected with the first end of the first capacitor, the second end of the first capacitor is connected with the emitting electrode of the IGBT and is grounded, the second end of the first inductor is connected with the grid electrode of the IGBT, and the collector electrode of the IGBT is used for being connected with a signal output end. According to the invention, the conduction state of the IGBT is improved, di / dt and du / dt are reduced, and meanwhile, the conduction loss is reduced.

The utility model relates to a crosstalk suppression driving circuit of a silicon carbide MOSFET bridge circuit and power supply equipment. The crosstalk suppression driving circuit comprises an upper bridge driving module, an upper bridge crosstalk suppression module, a lower bridge driving module and a lower bridge crosstalk suppression module. The upper bridge driving module is respectively connected with the upper bridge crosstalk suppression module and the upper bridge arm, and the upper bridge crosstalk suppression module is also connected with the upper bridge arm; the lower bridge driving module is connected with the lower bridge crosstalk suppression module and the lower bridge arm, and the lower bridge crosstalk suppression module is further connected with the lower bridge arm. Each crosstalk suppression module and the corresponding bridge arm share a turn-off signal and a turn-on signal, and there is no need to additionally add a detection or control circuit to control the crosstalk suppression module. Each crosstalk suppression module is connected with the corresponding bridge arm in the turn-off process of the corresponding bridge arm, so that the forward driving crosstalk and the negative driving crosstalk of the silicon carbide MOSFET can be suppressed; and each crosstalk suppression module is automatically disconnected with the corresponding bridge arm before the corresponding bridge arm is conducted, so that the conduction loss of the bridge arm can be reduced, and the circuit efficiency is prevented from being reduced.

The invention discloses a Si / SiC hybrid parallel device driving circuit with a variable switching time sequence. The Si / SiC hybrid parallel device driving circuit comprises a time sequence switching signal generating circuit, a time delay switch and time sequence switching circuit and a push-pull output circuit. A driving signal is sent by a main control chip, two different driving signals are respectively generated through calculation of a time delay circuit and a plurality of logic gates, and a conventional driving time sequence of normal switching on and off of a SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor), delayed switching-on of a Si IGBT (Insulated Gate Bipolar Transistor) and switching-off in advance can be adapted. And meanwhile, a timing sequence switching signal generation circuit detects and compares the conduction current of the SiC MOSFET so as to generate a timing sequence switching signal. And when the conduction current of the SiC MOSFET is in different regions, switching the switching time sequence of the Si / SiC hybrid parallel device. According to the invention, within the whole operation range of the Si / SiC hybrid parallel device, the lowest switching loss and conduction loss are ensured, and the reliability of the SiC MOSFET is greatly improved.

The invention provides a resistor and capacitor measuring circuit and method, and relates to the technical field of resistor and capacitor measurement, and the resistor and capacitor measuring circuit comprises a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6, a reference capacitor CREF, a capacitor CTEST to be measured, a reference resistor RREF, a resistor RTEST to be measured, a Schmitt trigger u1, a time-to-digital converter TDC and a microprocessor muC. And the Schmitt trigger u1, the time-to-digital converter TDC and the microprocessor muC are sequentially connected in series. According to the resistor-capacitor measuring circuit and method, the discharge time of the reference resistor-capacitor and the discharge time of the resistor-capacitor to be measured are respectively measured through the time-to-digital converter, the time proportion is calculated, and the parameters of the resistor-capacitor to be measured and the resistor-capacitor to be measured are calculated and reversely deduced by combining the known reference capacitor and the resistor. The correction compensation amount is obtained through an additional measurement state, and then the measurement result is corrected, so that the influence of the conduction loss of the switch on the measurement result is greatly reduced.

The invention discloses a gallium oxide-based Schottky barrier diode and a preparation method thereof. The method comprises the following steps: preparing a gallium oxide substrate; performing oxygen plasma treatment in a reactive ion etching system; feeding the sample into a tubular furnace, and annealing in an air atmosphere; then sending the annealed sample into electron beam evaporation equipment for back metal silver electrode growth; next, the sample is sent into rapid thermal annealing equipment to be annealed in the N2 atmosphere, and ohmic contact is formed; then, under the conditions that the growth speed is 0.01-0.1 nm / s and the vacuum degree is lower than 1 * 10 <-4 > Pa, field plate oxide Al2O3 grows on the surface treatment acting layer of the substrate through electron beam evaporation; and finally growing a metal anode at the top of the device by electron beam evaporation equipment. According to the technical scheme provided by the invention, the problem of preparing the gallium oxide-based Schottky barrier diode with low forward conduction loss under the condition of maintaining high breakdown voltage of the device is solved.

The invention relates to a feedback-based self-adaptive grid voltage regulation synchronous rectification method and a chip, which are executed in a synchronous rectification chip of a power supply circuit. A voltage signal VKA between the drain electrode and the source electrode of the synchronous rectification MOS tube is detected, a feedback signal V 'KA is formed through adaptive filtering, and the driving module dynamically adjusts the grid voltage Vgs according to the V' KA. When the V 'KA is lower than a conduction detection threshold VON, the MOS tube is completely conducted; when the V 'KA rises to be close to a pre-turn-off trigger threshold value VREADY-OFF, the Vgs is dynamically reduced to increase the on resistance, so that the MOS tube is kept in an incomplete conduction state; in the state, the V 'KA is continuously monitored, when the V' KA is lower than the VON again, complete conduction is recovered, only when the V 'KA continuously rises and reaches a turn-off threshold VOFF, the MOS tube is completely turned off, and if the above conditions are not met, the MOS tube is maintained in an incomplete conduction state. According to the adaptive closed-loop adjustment method, the conduction loss and the grid driving loss can be effectively reduced, and the power supply conversion efficiency and the system reliability are improved.

The invention discloses a discontinuous current type variable duty ratio output resonant gate drive circuit, and belongs to the field of power electronics. The resonant gate drive circuit comprises a PMOS (P-channel Metal Oxide Semiconductor) tube, two NMOS (N-channel Metal Oxide Semiconductor) tubes, an inductor L and a voltage stabilizing capacitor, the on-off states of the PMOS tube and the NMOS tubes are controlled by controlling the time sequence of gate drive signals of the PMOS tube and the NMOS tubes, and inductive current flowing through the inductor is in a discontinuous state. The resonant state of the inductor and the gate capacitor of the driven circuit and the duty ratio of the driving output voltage are further controlled. The inductive current of the circuit is discontinuous, the conduction loss of the circuit is greatly reduced, the grid driving energy recovery ratio is improved, and the duty ratio conversion of the driving signal can be realized by controlling the duty ratio of the driving signal. Therefore, the technical problems that the energy recovery rate is low, the number of control signals is large, signal matching is difficult, the occupied area is large, miniaturization is not facilitated, and the duty ratio cannot be adjusted in the driving technology are solved.

The invention discloses a multi-path power source redundant power supply control method and system, and belongs to the technical field of power electronics, the system comprises a dynamic priority decision module, a zero-voltage-drop switching circuit and a fault safety framework, the dynamic priority decision module supports a user to customize a power source use priority rule through an MCU, and the zero-voltage-drop switching circuit is used for switching the zero-voltage-drop switching circuit to the fault safety framework. The MCU can autonomously carry out an automatic degradation and upgrading mechanism through voltage quality; according to the zero-voltage-drop switching circuit, when the MCU detects a fault of the main power supply, a target power supply pre-charging path is started, and when the target power supply is pre-charged until the voltage difference between the target power supply and the source voltage is smaller than or equal to 0.1 V, the target power supply GaNFET can be synchronously triggered to be switched on, and the pre-charging circuit and the original power supply GaNFET can be synchronously triggered to be switched off. The multi-path power supply input automatic switching circuit solves the problems of power-off risk, easy conduction loss and relatively high failure rate in the prior art, is suitable for a multi-path power supply input automatic switching system of a decoder and industrial control equipment, and is particularly suitable for a long-time uninterrupted power supply condition.

The invention relates to the technical field of control boxes, and discloses a main control box based on industrial control, which comprises a box body, an aviation socket arranged on one side of the box body, jacks annularly formed in the aviation socket, contacts arranged in the jacks, mounting seats arranged in the jacks, contacts arranged at the top of the mounting seats, and plugs arranged on the aviation socket, the plug is arranged in the box body, the contact pins are arranged on the plug, the devices are arranged in the box body, and the cleaning component is arranged in the jack. When the cleaning part works, extra power is not needed, the contact pin cleaning part is driven to rotate along the spiral hole through mechanical thrust generated when the plug is plugged in and pulled out, linear motion is converted into rotary scraping, cleaning while plugging is achieved, and the problems of energy consumption and structure complexity of a traditional active cleaning scheme are solved. By scraping dust and an oxide layer in real time, the fluctuation of contact resistance can be effectively controlled, and compared with a traditional aviation socket, the electric conduction loss and the heating risk are remarkably reduced.