29 results about "Pole frequency" patented technology

The invention discloses a transformer type differential series resonant cavity, a differential series resonant oscillator, a chip and equipment, the resonant cavity comprises a two-port transformer and a variable capacitance module, the two-port transformer comprises an inductor LP1, an inductor LP2, an inductor LS1 and an inductor LS2 which are mutually coupled, and the variable capacitance module comprises a variable capacitor CP and a variable capacitor CS; one end of the inductor LP1 is connected with the first port, and the other end is connected with the variable capacitor CP; one end of the inductor LP2 is connected with the second port, and the other end is connected with the variable capacitor CP; one end of the inductor LS1 and one end of the inductor LS2 are connected with the third port and the fourth port respectively, and the other end of the inductor LS1 and the other end of the inductor LS2 are connected with each other; two ends of the variable capacitor CS are respectively connected with the third port and the fourth port; a plurality of pole frequencies of the voltage gain function AV are set to be equal such that AV at the zero phase increases. According to the invention, the problem that a series resonant oscillator cannot realize pure differential output in the current pure CMOS process is solved.

The invention relates to the technical field of analog integrated circuits, and discloses an LDO (Low Dropout Regulator) frequency compensation circuit based on a voltage-controlled current source, which comprises an input differential amplification module, a power regulation module, a frequency compensation module and a feedback voltage division module, and is characterized in that the output end of the input differential amplification module is electrically connected with the input end of the frequency compensation module; the frequency compensation module comprises a voltage-controlled current source and a compensation capacitor C1, the compensation capacitor C1 is matched with the voltage-controlled current source to adjust the loop frequency response, through a multi-stage current mirror and a Miller compensation network, pole distribution is optimized in a targeted mode, the Miller effect of the compensation capacitor C1 is matched, the dominant pole frequency can be actively lowered, a dominant pole is made to be away from a high-frequency area, and the loop phase margin is guaranteed; the self-excited oscillation is fundamentally suppressed, and the output voltage is stable and free of fluctuation.

A low dropout regulator (LDO) comprising an amplifier, a buffer circuit, an output circuit, a first compensation capacitor and a second compensation capacitor is provided. The buffer circuit comprises an input terminal coupled to an output terminal of the amplifier. The output circuit comprises an input terminal coupled to an output terminal of the buffer circuit, and comprises an output terminal for outputting a voltage. The first compensation capacitor is coupled between the output terminal of the output circuit and an internal cascade node of the amplifier, and configured to separate a first pole frequency of a Bode plot of the LDO from a power supply rejection ratio corner frequency. The second compensation capacitor is coupled between the input terminal of the buffer circuit and an input power source, and configured to separate a second pole frequency and a third pole frequency of the Bode plot of the LDO.

An integrated circuit system includes voltage regulator circuitry that is coupled to and drives an integrated circuit device. The voltage regulator circuitry includes source follower circuitry, trans-impedance amplifier circuitry, and tracking circuitry. The source follower circuitry receives a first signal and generates a second signal by applying a first gain to the first signal. The trans-impedance amplifier circuitry receives the second signal from the source follower circuitry and outputs a third signal based on the second signal. The tracking circuitry receives the third signal from the trans-impedance amplifier circuitry and an output signal of the voltage regulator circuitry, and tracks a load current of the output signal using the third signal.

An apparatus includes an amplifier. The amplifier has two inputs, and an output. The amplifier has a pole in its transfer function. The frequency of the pole depends on the output current of the amplifier. The amplifier further includes a pole frequency tracking (PFT) circuit. The PFT circuit includes a source follower circuit.

The invention discloses an amplifying circuit and a current buffer therein. The current buffer includes: a current copy circuit generating a first relay current at a first node and a second relay current at a second node according to an input current; a first impedance bias circuit coupled to the first node to provide a first input impedance at the first node and generate an output current according to a current flowing through the first node; a second impedance bias circuit coupled to the second node for providing a second input impedance at the second node; the feed-forward capacitor is coupled between the first node and the second node; wherein the first input impedance is smaller than the second input impedance, so that the current gain between the output current and the input current has a zero point and a pole point, the zero point frequency of the zero point is smaller than the pole point frequency of the pole point, and the zero point frequency and / or the pole point frequency are / is related to the capacitance value of the feed-forward capacitor and the impedance value of the second input impedance.

A voltage regulator includes a first circuit to generate a difference signal based on an input reference voltage, a regulated output voltage, and a signal on a feedback node. The voltage regulator includes a second circuit to provide the regulated output voltage on the output node based on the difference signal. The second circuit includes a first transistor coupled to receive the difference signal, a first feedback circuit to provide a first feedback signal to the feedback node, and a second feedback circuit to provide a second feedback signal to the feedback node. An open loop frequency response of the voltage regulator has a first pole and a second pole and the first feedback signal may adjust the frequency of the second pole based on a load current. The second feedback signal may adjust loop gain based on the load current.

To suppress the occurrence of parallel oscillation when a plurality of switching elements are simultaneously operated.SOLUTION: The first lower arm transistor 11L and the second lower arm transistor 12L are connected in parallel to each other. The parallel resonance circuit of the first lower arm transistor 11L and the second lower arm transistor 12L has a first pole frequency ω p1, a second pole frequency ω p1 higher than the first pole frequency ω p2, and a zero point frequency ω z. The absolute values of the phase delay at the second pole frequency ω p2 and the zero point frequency ω z are set to be smaller than 180 °.SELECTED DRAWING: Figure 1

The present invention discloses a transformer-type differential series resonant cavity, a differential series resonant oscillator, a chip and a device, wherein the resonant cavity comprises: a two-port transformer and a variable capacitance module, the two-port transformer comprises mutually coupled inductors L P1 、Inductor L P2 and inductor L S1 、Inductor L S2 , the variable capacitor module includes a variable capacitor C P and variable capacitor C S Inductance L P1 One end is connected to the first port, and the other end is connected to the variable capacitor C P Inductance L P2 One end is connected to the second port, and the other end is connected to the variable capacitor C P Inductance L S1 and inductor L S2 One end of the inductor L is connected to the third port and the fourth port respectively. S1 and inductor L S2 The other ends of the variable capacitor C S The two ends of are connected to the third port and the fourth port respectively; the voltage gain function A V The multiple pole frequencies of the CMOS are set equal so that the A V The present invention solves the problem that a series resonant oscillator in a current pure CMOS process cannot achieve pure differential output.

The invention discloses a non-inductive FOC ripple characteristic rotor positioning method and system, and the method comprises the steps: injecting a multi-direction detection voltage vector with the amplitude increasing gradually into a stator winding at a zero-speed starting stage of a motor, and enabling the multi-direction detection voltage vector to comprise at least three non-collinear space directions; synchronously acquiring three-phase current transient response under the action of each voltage vector, and extracting a current ripple characteristic component matched with the rotor salient pole frequency through band-pass filtering; based on the spatial distribution anisotropy of the current ripple characteristic component, a position sensitive factor set corresponding to the voltage direction is constructed, and each position sensitive factor in the position sensitive factor set represents the distribution weight of ripple energy under excitation in the voltage direction. According to the invention, all-condition robust control is realized through a multi-dimensional cooperative detection mechanism and a dynamic feature compensation architecture.

There are provided methods and apparatuses for removing a DC offset from an input signal, comprising: receiving the input signal having a first phase and a second phase; applying a high pass filter to the input signal, wherein a transfer function of the high pass filter has a pole coefficient that determines a pole frequency of the high pass filter, comprising: selecting a first pole coefficient of the high pass filter for the first phase, estimating DC offset of the input signal during the first phase, and selecting a second pole coefficient of the high pass filter for the second phase, wherein the first pole coefficient and the second pole coefficient are selected such that the first pole frequency is higher than the second pole frequency; and removing the DC offset from the input signal.

A semiconductor module includes: a first transistor and a second transistor connected in parallel to each other, wherein a parallel resonant circuit of the first transistor and the second transistor has a first pole frequency (ωp1), a second pole frequency (ωp2) higher than the first pole frequency (ωp1), and a zero frequency (ωz), and wherein an absolute value of a phase lag between the second pole frequency (ωp2) and the zero frequency (ωz) is set to be smaller than 180 degrees.

The present disclosure relates to a phase-locked loop circuit and a signal processing device. The phase-locked loop circuit includes: a charge pump configured with a charge pump current; and a loop filter connected to the charge pump and configured with a first resistance value, a first capacitance value, and a second capacitance value, wherein a zero frequency of the phase-locked loop circuit is configured to be determined by the first resistance value and the first capacitance value, and a pole frequency of the phase-locked loop circuit is configured to be determined by the first resistance value and the second capacitance value; wherein at least two of the charge pump current, the first resistance value, the first capacitance value, and the second capacitance value are adjustable, to change a loop bandwidth of the phase-locked loop circuit, to maintain a first ratio between the zero frequency and the loop bandwidth unchanged, and to maintain a second ratio between the pole frequency and the loop bandwidth unchanged.

The utility model provides a constant current module and a circuit structure. The constant current module comprises a high electron mobility field effect transistor based on III-V compounds and a source feedback resistor. The source feedback resistor comprises a built-in source resistor of the transistor or the built-in source resistor of the transistor and an external source resistor connected to the source. According to the utility model, the source feedback resistor is arranged in the constant current module, so that the gain is reduced, the stability is improved, the high-frequency performance is improved, the phenomena of ringing and the like are avoided, the transient response is not too slow, the pole frequency is more controllable, the occurrence probability of self-oscillation is reduced, and the service life of the constant current module is prolonged. The power density of the transistor can be controlled, the working temperature of the transistor can be reduced, the service life of the transistor can be prolonged, the knee-point voltage of the transistor can be obviously reduced, the influence caused by transistor production process errors can be reduced or eliminated, and the yield of the transistor can be improved.

The present application relates to the technical field of LDO circuit, especially to a dynamic pole compensation LDO circuit, which eliminates the channel length modulation effect by dynamically mirroring the current of PM0 through PM1 and combining the current mirror structure composed of PM2, PM3, NM0 and NM1, adopts the super source follower composed of NM5, NM6 and NM7 to push the secondary pole of the LDO to the outside of the bandwidth, greatly improves the phase margin, mirrors the dynamic load current to PM9 (diode connection) through NM9, combines the capacitor C1 to form a dynamic zero point, compensates the secondary pole in real time following the load change, avoids the problem that the primary and secondary poles are too close in the traditional Muller compensation, introduces NM2 to break the degenerate point of the current mirror, ensures the normal starting and stable work of the circuit, adjusts the gm value of the super source follower through the dynamic current mirroring of PM5 and PM7, automatically adjusts the secondary pole frequency with the change of the load current, realizes the adaptive optimization of the pole in the full load range, and improves the stability consistency under light load and heavy load.

The application discloses a non-inductive FOC ripple feature rotor positioning method and system, and the method comprises the following steps: in the motor zero-speed starting stage, a multi-directional detection voltage vector with gradually increasing amplitude is injected into the stator winding, and the multi-directional detection voltage vector contains at least three non-collinear spatial directions; the three-phase current transient response under the action of each voltage vector is synchronously collected, and the current ripple characteristic component matched with the rotor salient pole frequency is extracted through band-pass filtering; based on the spatial distribution anisotropy of the current ripple characteristic component, a position sensitive factor set corresponding to the voltage direction is constructed, and each position sensitive factor in the position sensitive factor set represents the distribution weight of the ripple energy under the excitation of the voltage direction. Through the multi-dimensional collaborative detection mechanism and the dynamic feature compensation architecture, the application realizes robust control in all working conditions.

Provided is a low-dropout regulator circuit with high loop stability based on a load-dependent zero mobile compensation and a method thereof. The LDO circuit with high loop stability comprises a LDO circuit body, the LDO circuit body includes a PMOS transistor; the LDO circuit with high loop stability comprises a dynamic-resistance-boosting-circuit adaptively connected with the PMOS transistor, a dynamically variable resistor in parallel with PMOS transistor is generated according to the state of the load by the dynamic-resistance-boosting-circuit; the dynamically variable resistor is connected in parallel with PMOS transistor following the load variations to form a load equivalent resistor, a value for the formed load equivalent resistor is less than an equivalent resistance maximum value for PMOS transistor in a stable loop state, so that a high frequency pole frequency of the LDO circuit body is greater than a unit gain frequency of the LDO circuit body.

The utility model discloses a circuit structure for improving the stability of LDO, including low dropout linear regulator circuit and low dropout linear regulator circuit connected negative capacitance generation circuit, low dropout linear regulator circuit includes adjusting tube and first amplifier, the output end of first amplifier is connected with the gate of adjusting tube, the output end of first amplifier is connected with the gate of adjusting tube, the output end of first amplifier is connected with the gate of adjusting tube, and the negative capacitance generation circuit is connected with the negative capacitance generation circuit in the low dropout linear regulator circuit. The first amplifier is an error amplifier; according to the technical scheme provided by the utility model, besides a known method for increasing the pole frequency of an internal node by adding source follower isolation, a new method is provided for increasing the pole frequency of the internal node, and by utilizing the Miller principle, a negative capacitance generation circuit in the low-dropout linear voltage regulator circuit is adopted, so that the high-voltage linear voltage regulator can be used for increasing the pole frequency of the internal node. Therefore, an equivalent capacitor with a reduced capacitance value is formed, so that the time constant of a node at the joint of the error amplifier and the adjusting tube is reduced, the pole frequency is increased, an output port can be changed into a dominant pole, the phase margin of the LDO is improved, and the stability of the LDO is ensured.

The low dropout regulator comprises an amplifier, a buffer circuit, an output circuit, a first compensation capacitor and a second compensation capacitor. The amplifier comprises a non-inverting input end, an inverting input end, an internal cascade node and an output end. The buffer circuit comprises an input end and an output end, and the input end of the buffer circuit is coupled to the output end of the amplifier. The output circuit includes an input terminal coupled to the output terminal of the buffer circuit and an output terminal for outputting an output voltage. The first compensation capacitor is coupled between the output end of the output circuit and an internal cascade node of the amplifier, and is used for separating a first pole frequency of a Baut diagram of the low dropout regulator from a power supply voltage rejection ratio turning point frequency. The second compensation capacitor is coupled between the input end of the buffer circuit and the input power supply and is used for separating a second pole frequency and a third pole frequency of the Bode diagram.

The invention discloses a power supply conversion device with wide load adaptability and capable of parallel operation of multiple devices and a control method of the power supply conversion device. The power supply conversion device comprises an input LCL filtering unit, a three-phase Vienna conversion unit, an LLC isolation conversion unit, an H-bridge inversion output unit and an output LCL filtering unit which are connected in sequence. The three-phase Vienna conversion unit, the LLC isolation conversion unit and the H-bridge inversion output unit are respectively connected with a control unit; the H-bridge inverter output unit can measure the resistance-inductance value of an output load, so that a loop suitable for the load is selected for control, and the wide-range load adaptability is met by using an interleaving parallel control strategy with a current-sharing ring, a front-back voltage-sharing voltage loop parallel operation strategy and a single-pole frequency doubling driving method; flexible parallel operation is realized, the output efficiency is improved, the output current ripple is greatly reduced, and the use scene of the power supply conversion device is greatly expanded.

The invention particularly relates to an asymmetric response superconducting resonator loaded with vertical through holes and interdigital capacitors and a superconducting filter based on the resonator, and belongs to the technical field of high-temperature superconducting circuits and microwave communication. The filter comprises a dielectric substrate, a high-temperature superconducting thin film layer and a circuit constructed on the high-temperature superconducting thin film layer, the circuit comprises four single-ended grounding folded microstrip structures, an interdigital capacitor, a rectangular microstrip block grounding structure, a feeder auxiliary line, an input / output microstrip feeder and a grounding through hole, and four grounding multimode resonators are formed to provide eight pole frequencies. By adjusting the width of the rectangular microstrip block grounding structure and the length and position of the interdigital capacitor, independent regulation and control of odd-even mode frequency and flexible control of a transmission zero point are realized. An additional topological structure is not needed, selectivity and out-of-band rejection performance of the filter are remarkably improved while the size of a device is reduced and low insertion loss is kept, the filter is compatible with an existing thin film process, the miniaturization and batch requirements are met, and the industrialization potential is outstanding.

Methods and apparatus are provided for removing a DC offset from an input signal, comprising: receiving the input signal having a first phase and a second phase; applying a high-pass filter to the input signal, wherein a transfer function of the high-pass filter has a pole coefficient that determines a pole frequency of the high-pass filter, comprising: selecting a first pole coefficient of the high-pass filter for the first phase, estimating a DC offset of the input signal during the first phase, and selecting a second pole coefficient of the high-pass filter for the second phase, wherein the first pole coefficient and the second pole coefficient are selected such that the first pole frequency is higher than the second pole frequency; and removing the DC offset from the input signal.

The invention provides a buck-boost DC / DC converter feedback loop parameter design method. The method comprises the following steps: establishing a feedback loop model; the feedback loop model is divided into a voltage reference unit feedback link, a photoelectric coupler primary part feedback link, a photoelectric coupler feedback link and a photoelectric coupler secondary part feedback link; constructing a transfer function of a feedback loop model based on the transfer function of the feedback link of the voltage reference unit, the transfer function of the feedback link of the primary part of the photoelectric coupler, the transfer function of the feedback link of the photoelectric coupler and the transfer function of the feedback link of the secondary part of the photoelectric coupler; obtaining expressions of zero pole cutoff frequency, pole frequency and zero point frequency of the feedback loop model based on the transfer function of the feedback loop model; and obtaining the resistance values of a first resistor, a second resistor and a third resistor and the capacitance values of a first capacitor and a second capacitor of the feedback loop model based on the expressions of the zero pole cutoff frequency, the pole frequency and the zero point frequency of the feedback loop model.

Disclosed in the present invention are a transformer-type differential series resonant cavity, a differential series resonant oscillator, a chip and a device. The resonant cavity comprises: a two-port transformer and a variable capacitor module, wherein the two-port transformer contains an inductor LP1, an inductor LP2, an inductor LS1 and an inductor LS2 which are coupled to each other; the variable capacitor module comprises a variable capacitor CP and a variable capacitor CS; one end of the inductor LP1 is connected to a first port, and the other end thereof is connected to the variable capacitor CP; one end of the inductor LP2 is connected to a second port, and the other end thereof is connected to the variable capacitor CP; one end of the inductor LS1 and one end of the inductor LS2 are respectively connected to a third port and a fourth port, and the other end of the inductor LS1 and the other end of the inductor LS2 are connected to each other; two ends of the variable capacitor CS are respectively connected to the third port and the fourth port; and the frequencies of a plurality of poles of a voltage gain function AV are set to be equal, such that AV at a zero phase is increased. The present invention solves the problem of it being impossible for a series resonant oscillator to realize a pure differential output in a current pure CMOS process.

The invention relates to the field of integrated circuits, in particular to a low-phase-noise differential oscillator, a self-adaptive biasing circuit and application of the low-phase-noise differential oscillator and the self-adaptive biasing circuit. The oscillator adopts a Class-C architecture, and a self-adaptive bias circuit composed of two bias copy transistors, an integrating capacitor and a bias resistor is introduced. The self-adaptive biasing circuit and the Class-C oscillator can form a feedback loop, so that the differential crystal oscillator can reliably start oscillation in a C-type working mode; and the conduction angle of the cross coupling pair is limited in a relatively small range, so that extra noise is prevented from being introduced by an overlarge conduction angle. The adaptive biasing circuit can further reduce the pole frequency corresponding to a low-frequency additional resonance point introduced by the Class-C structure. Therefore, the problem that the differential crystal oscillator is difficult to give consideration to reliable oscillation starting and parasitic oscillation suppression is solved.

The application provides a constant current module and application thereof. The constant current module comprises a high electron mobility field effect transistor based on a III-V compound and a source feedback resistor; the source feedback resistor comprises a built-in source resistor of the transistor or the built-in source resistor of the transistor and an external source resistor connected to the source. In the application, the source feedback resistor is arranged in the constant current module, so that the gain of the constant current module is reduced, the stability is improved, the high-frequency performance is improved, the ringing phenomenon is avoided, the transient response is not too slow, the pole frequency is more controllable, the probability of self-oscillation is reduced, the power density is controlled, the working temperature is reduced, the service life is prolonged, the knee voltage is obviously reduced, the influence caused by the production process error of the transistor is reduced or eliminated, and the yield is improved.

The present invention relates to the field of analog integrated circuit technology, and discloses an LDO frequency compensation circuit based on a voltage-controlled current source. The circuit includes an input differential amplifier module, a power regulation module, a frequency compensation module, and a feedback voltage divider module. The output end of the input differential amplifier module is electrically connected to the input end of the frequency compensation module. The frequency compensation module includes a voltage-controlled current source and a compensation capacitor C1. The compensation capacitor C1 cooperates with the voltage-controlled current source to adjust the loop frequency response. Through a multi-stage current mirror plus Miller compensation network, the pole distribution is targetedly optimized. In conjunction with the Miller effect of the compensation capacitor C1, the main pole frequency can be actively lowered, the main pole is kept away from the high frequency region, the loop phase margin is guaranteed, and self-oscillation is fundamentally suppressed, so that the output voltage is stable and without fluctuations.

The invention relates to the technical field of LDO (Low Dropout Regulator) circuits, in particular to a dynamic pole compensation LDO (Low Dropout Regulator) circuit, which is characterized in that the current of PM0 is dynamically mirrored through PM1, a channel length modulation effect is eliminated by combining a current mirror structure formed by PM2, PM3, NM0 and NM1, a super source follower formed by NM5, NM6 and NM7 is adopted, secondary poles of the LDO are pushed out of a bandwidth, the phase margin is greatly improved, and the performance of the LDO circuit is improved. Dynamic load current is mirrored to PM9 (diode connection) through NM9, a dynamic zero point is formed in combination with a capacitor C1, a secondary pole is compensated along with load change in real time, the problem that a primary pole and a secondary pole are too close in traditional Miller compensation is avoided, NM2 is introduced to break a degeneracy point of a current mirror, normal starting and stable working of a circuit are ensured, and the circuit is stable in performance. The gm value of the super source follower is adjusted through the dynamic current mirror images of PM5 and PM7, so that the secondary pole frequency is automatically adjusted along with the change of the load current, the adaptive optimization of the pole in the full-load range is realized, and the stability consistency under the light load and the heavy load is improved.

The present application discloses an LDO regulation circuit, a power management chip, and an LDO regulation method. The LDO regulation circuit includes a power tube module, an error amplification module, a buffer, and a compensation module. The buffer is connected between the power supply terminal and the ground terminal. The input terminal of the buffer is connected to the amplified output terminal of the error amplification module, and the output terminal of the buffer is connected to the power tube module. The buffer is used to separate the main pole and the secondary pole. The main pole is set at the voltage output terminal, and the secondary pole is set at the amplified output terminal of the error amplification module. The compensation module is connected to the amplified output terminal of the error amplification module. The compensation module is used to adjust the pole frequency of the secondary pole according to the magnitude of the load current when the load current flowing through the power tube module is less than the current limiting threshold. In this design, the compensation module adjusts the pole frequency of the secondary pole according to the magnitude of the load current to keep the pole frequency of the secondary pole away from the pole frequency of the main pole, thereby improving the stability of the LDO loop.