1210results about "Amplifier details" patented technology

A logarithmic amplifier includes programmable gain amplifiers each having a different gain, wherein an input of each of the programmable gain amplifiers is coupled to an input of the logarithmic amplifier; and a summing circuit having inputs coupled to a corresponding output of each of the programmable gain amplifiers and an output coupled to an output of the logarithmic amplifier, wherein the summing circuit generates a logarithmic transfer function having piecewise linear segments.

A packaged RF transistor amplifier includes an RF transistor amplifier die having a first terminal, a first lead, an integrated passive device that includes a first series microstrip transmission line, a first bond wire coupled between the first terminal and the first series microstrip transmission line, and a second bond wire coupled between the first series microstrip transmission line and the first lead.

This application relates to methods and apparatus for driving a transducer. A transducer driver has a switch network is operable to selectively connect a driver output to any of a first set of at least three different switching voltages. which are, in use, maintained throughout a switching cycle of the driver apparatus. The switch network is also operable to selectively connect the driver output to flying capacitor driver. A controller is configured to control the switch network and flying capacitor driver to generate a drive signal at the driver output based on an input signal, wherein in one mode of operation the driver output is switched between two of the first set of switching voltages with a controlled duty cycle and in another mode of operation the driver output is connected to the flying capacitor driver which is switched between first and second states with a controlled duty cycle.

An adaptable, generalized digital predistortion system that can increase the accuracy of the distortion applied to a power amplifier input signal is disclosed. Further, the digital predistortion system can be implemented using a reduced circuit area by reducing a number of coefficients used by the models applied to generate the distortion compensation signal. Further, the system can implement an improved digital predistortion adaptation engine that can improve one or more of the following metrics of a complete radio frequency (RF) analog front-end radio signal chain: error vector magnitude (EVM), adjacent channel leakage ratio (ACLR), spectrum emission mask (SEM), and power consumption of the circuits and systems. An example of circuits and systems is a radio frequency power amplifier (PA).

A radio-frequency (RF) circuit including: a multi-tone generation circuit configured to generate a multi-tone signal including a plurality of tones; a predistortion circuit configured to predistort the multi-tone signal or a modulation signal and output a predistortion signal; a power amplifier configured to amplify the predistortion signal and output an output signal; and a predistortion modeling circuit configured to model a predistortion model corresponding to the predistortion circuit based on the predistortion signal corresponding to the multi-tone signal and the output signal.

A multi-voltage power management integrated circuit (PMIC) is disclosed. More specifically, the multi-voltage generation circuit includes multiple voltage modulation circuits each configured to generate and maintain a respective one of multiple modulated voltages based on a battery voltage and a respective one of multiple reference voltages. Contrary to using multiple voltage-current modulation circuits, such as direct-current-direct-current (DC-DC) converters, to generate the multiple reference voltages, the multi-voltage PMIC is configured to share a single voltage-current modulation circuit among the multiple voltage modulation circuits. As such, the multi-voltage PMIC can concurrently support multiple load circuits (e.g., power amplifier circuits) with a significantly reduced footprint.

A class D amplifier circuit receives an analog audio signal with a first reference voltage as its center level, and outputs an output pulse signal having a duty cycle that corresponds to the analog audio signal. A bias circuit generates a second reference voltage having a voltage level obtained as a division of the first reference voltage and the power supply voltage. A periodic voltage generating circuit of the class D amplifier circuit generates a periodic voltage having a triangle waveform or otherwise a sawtooth waveform having an amplitude that corresponds to the second reference voltage.

Low noise amplifiers (LNAs) are disclosed herein. In certain embodiments, an LNA includes an input balun configured to convert a single-ended radio frequency (RF) receive signal to a differential RF receive signal, an amplifier chain configured to amplify the differential RF receive signal to generate a differential amplified RF receive signal, and an output balun configured to convert the differential amplified RF receive signal into a single-ended amplified RF receive signal. The LNA's amplifier chain is operable in multiple gain modes, and includes a first differential amplification stage, a second differential amplification stage, and a third differential amplification stage.

An artificial intelligence (AI) driven linearizer for a transmitter, comprising an input interface for inputting linearizer signals comprising information carrying signals, and operating conditions parameter signals, other than the information carrying signal, wherein the operating conditions parameter signals represent metrics affecting transfer characteristics of the transmitter, over a selected operating range of the transmitter, and a predistortion actuator circuit configured with an AI predistortion model for predistorting at least part of the information carrying signal to produce predistorted signals, the predistortion model being configured to be operable for adaptation to said characteristics of the transmitter using a single set of model coefficients that are unchanged over said entirety of said selected operating range.

A power management integrated circuit (PMIC) is disclosed. The PMIC is configured to generate multiple voltages during a voltage generation period(s). In embodiments disclosed herein, the voltage generation period(s) is divided into multiple voltage generation intervals. A voltage generation circuit is configured to generate and maintain a respective one of the voltages during a respective one of the voltage generation intervals based on a reference voltage modulated for the respective one of the voltage generation intervals to thereby make the voltages concurrently available during the voltage generation period(s). Moreover, a voltage modulation circuit is configured to modulate the reference voltage in each of the voltage generation intervals based on a single direct-current to direct-current (DC-DC) power inductor. As a result, the PMIC can concurrently support multiple load circuits (e.g., power amplifiers) with significantly reduced footprint.

In some embodiments, in a radio frequency (RF) transceiver system having an RF amplifier and a digital pre-distorter (DPD), a control unit includes: one or more inputs, one of which is connected to receive a first signal corresponding to a signal desired to be transmitted via the RF amplifier or a modified version thereof; circuitry configured to generate a control signal for controlling a bias of the RF amplifier; and an output connected to provide the control signal to the DPD and to a bias modulation circuit for varying the bias of the RF amplifier based in part the control signal, wherein the DPD is configured to apply digital predistortion to the signal to be transmitted based in part on combining the first signal with a second signal corresponding to the control signal or a translated version thereof, and to provide a resulting pre-distorted signal to the RF amplifier.

Digital pre-distorter (DPD) coefficients can be used to compensate for non-linearity of a power amplifier (PA). A system can receive a defined waveform from transmit hardware. The system can transmit an output waveform with a defined modulation from the PA. The system can capture samples of the output waveform. The system can submit the samples to a processing system temporarily connected to a transmitter system. The system can compute a PA model using the defined waveform and the samples. The system can determine a plurality of Digital Pre-Distorter (DPD) coefficients for a plurality of power levels, frequencies, and temperatures based on the PA model. The system can store the plurality of DPD coefficients to a memory of the transmitter system. Additionally, the system can add predistortions using the plurality of DPD coefficients to a plurality of input waveforms to correct for impairments introduced by the PA.

The embodiment of the invention provides a radio frequency power assembly and electronic equipment, and relates to the technical field of communication equipment. The radio frequency power assembly comprises a substrate, a first chip, a second chip, an insulating layer, at least three conductive blocks, a first connecting part and a second connecting part. At least part of the insulating layer is arranged on the sides, away from the substrate, of the first chip and the second chip. The at least three conductive blocks are arranged on one side, far away from the substrate, of the insulating layer; the at least three conductive blocks are arranged at intervals along the second direction. One end of the first connecting part penetrates through the insulating layer and is connected with the first chip, and the other end is connected with one end of the conductive block; one end of the second connecting part penetrates through the insulating layer and is electrically connected with the second chip, and the other end is electrically connected with the other end of the conductive block. Among the at least three conductive blocks, the areas of the surfaces, away from the substrate, of at least two conductive blocks are different. According to the structural design of the radio frequency power assembly, a three-dimensional binding wire group structure is avoided, so that the preparation difficulty of the radio frequency power assembly can be effectively reduced.

In some source degeneration-based cascode LNAs, a cascode transistor may contribute a large portion of noise at mmWave frequencies due to lower output impedance from a bottom transistor (e.g., amplifying transistor or transconductance transistor) of the cascode. The cascode noise may negatively impact performance of the LNA. A first inductor (e.g., cascode inductor) may be coupled to the source of the cascode transistor and a second inductor (e.g., notch inductor) may be coupled to the gate of the bottom transistor such that the cascode inductor and a notch inductor inductively couple to each other, introducing a reverse-transmission zero in-band to reduce or eliminate cascode noise contribution and neutralize gate-drain capacitance of the bottom transistor with minimal area consumption.

Disclosed is a transmitter. The transmitter includes a plurality of power amplifiers, each of the plurality of power amplifiers being configured to receive an RF input signal, a parallel power combiner configured to combine outputs of the plurality of power amplifiers to generate an RF output signal, a supply voltage switch configured to provide one supply voltage to the plurality of power amplifiers, the one supply voltage being selected from among a plurality of supply voltages of different voltage levels, and a controller configured to control an output power of the RF output signal by selecting the one supply voltage from among the plurality of supply voltages, and controlling whether to activate each of the plurality of power amplifiers.

In an example, a system includes an amplifier having an output stage configured to provide an output voltage, where the output stage includes a p-channel transistor and an n-channel transistor. The system includes a sense transistor having a gate coupled to a gate of the p-channel transistor, where the sense transistor is configured to sense a current of the p-channel transistor and produce a sense current. The system includes a current mirror coupled to the sense transistor and configured to provide the sense current to a gate of a control transistor, the control transistor having a source coupled to the gate of the p-channel transistor. The system includes a reference current source coupled to the control transistor and configured to provide a reference current. The control transistor is configured to adjust a gate current provided to the p-channel transistor based on comparing the sense current to the reference current.

Methods and apparatus for amplifying a signal for transmission via an amplifier circuit are described. An example amplifier circuit generally includes an amplifier configured to amplify a signal for wireless transmission and including a first transistor and a second transistor. The amplifier circuit also includes: a transformer coupled to an output of the amplifier; a first coil coupled to the first transistor and inductively coupled to the transformer; and a second coil coupled to the second transistor and inductively coupled to the transformer.

A power amplifier includes a main switched capacitor power amplifier (SCPA), a peak SCPA, and a shunt inductor. The main SCPA is electrically coupled to a load. The peak SCPA is in parallel with the main SCPA and electrically coupled to the load. The shunt inductor is electrically coupled between the peak SCPA and the load.

An electronic device may include a transmitter coupled to an antenna over a signal path that runs through a front end module. The front end module may include a power amplifier disposed on the signal path. The front end module may include first, second, and / or third signal attenuators disposed on the signal path between an input of the amplifier and the transmitter. The front end module may include a voltage sensor that measures a bias voltage of the amplifier, a temperature that measures a temperature of the amplifier, and / or an impedance sensor that measures an impedance of the antenna. The first signal attenuator may be adjusted based on the measured bias voltage, the second signal attenuator may be adjusted based on the measured temperature, and the third signal attenuator may be adjusted based on the measured impedance to mitigate changes in the amplifier as operating conditions change over time.

The present application relates to the technical field of data processing. Disclosed are a multi-nuclear imaging radio frequency power amplifier and a multi-nuclear magnetic resonance imaging hardware system. The multi-nuclear imaging radio frequency power amplifier comprises: a radio frequency signal input end, a radio frequency switch, a pre-compensation circuit, a voltage-controlled attenuator, a voltage-controlled phase shifter, a broadband radio frequency power amplifier, a broadband directional coupler and a radio frequency signal output end; a first output abnormality protection control circuit; a second output abnormality protection control circuit; an amplitude control circuit; and a phase control circuit. By means of the multi-nuclear imaging radio frequency power amplifier in the present invention, nonlinear correction can be performed on the amplitude and phase of a broadband radio frequency power amplifier, such that the broadband radio frequency power amplifier keeps meeting the requirements for high linearity and high power at an operating frequency point of a corresponding nuclide, so as to ensure the linear relationship between input and output signals of a radio frequency power amplifier and adequate signal strength, thereby avoiding the generation of artifacts due to signal distortion, and ensuring the accuracy and clarity of magnetic resonance imaging.

A low-noise amplifier (LNA) includes a first transistor, a second transistor, and a load coupled to a drain of the first transistor and a drain of the second transistor. The LNA also includes a first reactive impedance matching network including a first inductor and a second inductor inductively coupled with the first inductor, wherein the first inductor is coupled to a source of the first transistor, and the second inductor is coupled to a gate of the first transistor. The LNA also includes a second reactive impedance matching network including a third inductor and a fourth inductor inductively coupled with the third inductor, wherein the third inductor is coupled to a source of the second transistor, and the fourth inductor is coupled to a gate of the second transistor. The LNA also includes a switching circuit configured to enable or disable each of the reactive impedance matching networks.

A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a plurality of sensors, each sensor configured to sense a current associated with a respective one of the first high-side switch, second high-side switch, first low-side switch, and second low-side switch. The system may also include short-circuit detection circuitry configured to determine a presence and a location of a short circuit in the Class-D stage based on the sensed currents.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, an apparatus may receive an indication of a selected digital pre-distortion (DPD) kernel from multiple DPD kernels. The apparatus may store multiple envelope values associated of with samples of an in-phase / quadrature (I / Q) signal and select a subset of envelope values based at least in part on the selected DPD kernel. The apparatus may generate, using the subset of envelope values and a look-up-table (LUT) component, an envelope computation value. The apparatus may store multiple computational values associated with the samples and select, based at least in part on the selected DPD kernel, at least one subset of computational values. The apparatus may generate an output sample that includes DPD based at least in part on combining the envelope computation value with the at least one subset of computational values. Numerous other aspects are described.

An apparatus includes a first power amplifier having a negative output terminal coupled to a first primary winding of a distributed transformer and a positive output terminal coupled to a second primary winding of the distributed transformer, a second power amplifier having a negative output terminal coupled to a third primary winding of the distributed transformer and a positive output terminal coupled to a fourth primary winding of the distributed transformer, a first conductive element connected between the negative output terminal of the first power amplifier and the negative output terminal of the second power amplifier, and a second conductive element connected between the positive output terminal of the first power amplifier and the positive output terminal of the second power amplifier.

Systems and techniques are provided for power amplifier gain error compensation for a Digital Power Amplifier (DPA). In some aspects, a compensation method includes obtaining in-phase (I) and quadrature-phase (Q) components of a baseband sample corresponding to in-phase input amplitude codes and quadrature-phase input amplitude codes. The in-phase input amplitude codes can be distorted based on first gain pre-compensation information corresponding to an in-phase signal branch of the DPA, to generate pre-distorted output amplitude codes of the I component. The quadrature-phase input amplitude codes can be distorted based on second gain pre-compensation information corresponding to a quadrature-phase signal branch of the DPA, to generate pre-distorted output amplitude codes of the Q component. The DPA can be driven using the pre-distorted output amplitude codes of the I and Q components to generate a Radio Frequency (RF) output.

An impedance matching network for a radio frequency (RF) transmission system can include first port for coupling to a first transistor differential pair. The network can further include a second port for coupling to a second transistor differential pair. The network can further include a matching network connected to the first port and the second port, the matching network comprised of a pair of coupled lines. Other aspects are described.

Disclosed are methods and apparatus for optimizing digital pre-distortion associated with a network device. The digital signal processing apparatus in a communication network may comprise at least one processor and at least one memory having computer program code stored thereon and configured, with the at least one processor, cause the digital signal processing apparatus as a network device to perform: splitting an input signal into two or more split signals with different frequencies, the frequency of each of said split signals being different from other said split signals; separating each of the two or more split signals into two or more component signals with different phases; and performing pre-distortion computation by using the component signals to get a pre-distorted signal to be transmitted to a power amplifier.

An electronic device and a method for wireless communication are provided. The electronic device includes a wireless communication circuit, a plurality of power amplification circuits, a first power modulator and a second power modulator configured to adjust a voltage output to at least one power amplification circuit connected among the plurality of power amplification circuits, a power switch configured to connect a first power amplification circuit among the plurality of power amplification circuits to the first power modulator or the second power modulator, memory storing one or more computer programs, and one or more processors communicatively coupled to the wireless communication circuit and the memory, wherein the one or more computer programs include computer-executable instructions that, when executed by the one or more processors individually or collectively, cause the electronic device to identify power amplification circuits for amplifying, respectively, transmission signals input to the wireless communication circuit, based on the identified power amplification circuits being connected to the first power modulator, control the power switch to connect the first power amplification circuit among the identified power amplification circuits to the second power modulator to simultaneously transmit the transmission signals using the identified power amplification circuits, and based on the identified power amplification circuits being connected to the first power modulator and second modulator, respectively, control the power switch to connect the first power amplification circuit among the identified power amplification circuits to the first power modulator to simultaneously transmit the transmission signals using the identified power amplification circuits.

A signal nonlinear distortion compensation method, a model, and a communication system, relating to the technical field of wireless communications. In the present disclosure, on the basis of a preset nonlinear compensation fusion model, DPD processing, CFR processing, and error compensation processing are respectively performed on an initial OFDM signal, so as to obtain the initial OFDM signal that has been subjected to nonlinear distortion compensation; in this way, by connecting in parallel a BL-DPD module, a BL-CFR module, and an error compensation module in the nonlinear compensation fusion model, the technical disadvantages in the prior art of relatively high requirements on the sampling rate of ADC / DAC, increased requirements on hardware and algorithm convergence speed, and increased system implementation difficulty and cost caused by a DPD module being applied after a CFR module are avoided. Therefore, the requirements on the sampling rate of the ADC / DAC are reduced, the nonlinear compensation performance of DPD for a power amplifier is improved, and the communication performance and the sensing performance of an OFDM system are also improved.

1. High-frequency amplifier arrangement (1) suitable for generating output powers ≥ 1kW at frequencies ≥ 2MHz for plasma excitation, comprising: a. a multi-layered conductor board (2), b. two transistors (S1, S2) which are each connected at their first power terminal to a common connection point, in particular a ground connection point (5), wherein the transistors (S1, S2) are of the same design and are arranged on the multilayer circuit board (2), c. a power transformer (7) whose primary winding (6) is connected to the second power terminal of the transistors (S1, S2), wherein the primary winding (6) and the secondary winding (4) of the power transformer (7) are each designed as planar conductor tracks arranged in different layers (61, 62) of the multilayer printed circuit board (2), d. a heat distributor (50), e. a thermally conductive leveling layer (52) which is firmly connected with its first surface to the first surface of the circuit board (2), and f. a connecting layer (53) which is firmly connected with its first surface to the second surface of the heat-conducting leveling layer (52) and with its second surface is firmly connected to the heat distributor (50).