40 results about "Transmission-line pulse" patented technology

Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P₁-N₂-P₂-N₁//N₁-P₃-N₃-P₁ lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC). The ESD protection cells are tested using the TLP (Transmission Line Pulse) technique, and ESD standards including HBM (Human Body Model), MM (Machine Model), and IEC (International Electrotechnical Commission) IEC 1000-4-2 standard for ESD immunity. ESD protection performance is demonstrated also at high temperature (140° C.). The unique high ratio of dual-polarity ESD protection level per unit area, allows for integration of fast-response and compact protection cells optimized for the current tendency of the semiconductor industry toward low cost and high density-oriented IC design. Symmetric/asymmetric dual polarity ESD protection performance is demonstrated for over 15 kV HBM, 2 kV MM, and 16.5 kV IEC for sub-micron technology.

Methods and apparatus are provided for fabricating and constructing solid dielectric “Coiled Transmission Line” pulse generators in radial or axial coiled geometries. The pour and cure fabrication process enables a wide variety of geometries and form factors. The volume between the conductors is filled with liquid blends of polymers and dielectric powders; and then cured to form high field strength and high dielectric constant solid dielectric transmission lines that intrinsically produce ideal rectangular high voltage pulses. Voltage levels may be increased by Marx and/or Blumlein principles incorporating spark gap or, preferentially, solid state switches (such as optically triggered thyristors) which produce reliable, high repetition rate operation. Moreover, these pulse generators can be DC charged and do not require additional pulse forming circuitry, pulse forming lines, transformers, or an output switch. The apparatus accommodates a wide range of voltages, impedances, pulse durations, pulse repetition rates, and duty cycles. The resulting mobile or flight platform friendly cylindrical geometric configuration is much more compact, light-weight, and robust than conventional linear geometries, or pulse generators constructed from conventional components. Installing additional circuitry may accommodate optional pulse shape improvements. The Coiled Transmission Lines can also be connected in parallel to decrease the impedance, or in series to increase the pulse length.

Disclosed are embodiments of a semiconductor chip structure and a method that incorporate a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.

A Transmission Line Pulse (TLP) testing system is disclosed that has a negative pulse inverter circuit that prevents large negative reflections which typically occur after the initial TLP pulse is applied to a low impedance device under test (DUT). Avoiding repetitive reflections, which naturally occur in TLP systems, prevents inducing DUT damage and confusing testing results. The pulse inverter circuit reduces reflections to lower levels than prior art TLP configurations, and can also be combined with known techniques to further reduce reflections for different impedance DUTs.

The invention relates to a method and a system for monitoring pulse electrostatic discharging testing response of a transmission line. A light emission microscope acquires light emission images of the pulse discharging process of each transmission line while a TLP testing system applies transmission line pulse under different pulse voltage to an electronic element, and each light emission image can be overlapped with optical reflecting images when the test is ended, so as to accurately position an electrostatic discharging channel and a damage point of the electronic element. With the adoption of the method and system, the electroluminescence phenomenon in the pulse electrostatic discharging testing process of the transmission line can be monitored in real time, thus the electrostatic discharging channel in the electronic element under the electrostatic discharging testing process can be clear, the damage point of electrostatic discharging can be timely found out and accurately positioned, and as a result, the weak link of electrostatic resistance of a product can be determined; in addition, the test information can be fully utilized, the test is simple, and good technological support is provided for the study on electrostatic damp of the electronic device and the improvement of ESD design; good engineering application values are achieved.

The invention discloses a method and a device for message transmission. Based on the method and the device for message transmission, a logic chip at a sending end is used for receiving a data message to be sent from a CPU (Central Processing Unit) at a home terminal through a non-PCIE (non-Peripheral Component Interface Express) bus, byte filling for expressing the data loading length of the data message is increased for the received data message, then the byte filling of the data message and the data loading are packaged into a loading field of a TLP (Transmission Line Pulse) fragment and are sent to a receiving end through a PCIE bus; correspondingly, the logic chip at the receiving end is used for receiving the TLP fragment from the sending end through the PCIE bus, the data loading of corresponding length in the loading field of the TLP fragment is determined to be the data loading of the data message of the byte filling according to the byte filling for expressing the data loading length of the data message in the loading field of the TLP fragment, and then the data loading of the corresponding length determined according to the byte filling is recovered into corresponding data message and sent to the CPU at the home terminal through the non-PCIE bus. However, the bandwidth availability ratio of the PCIE bus can be improved based on the method and the device for message transmission.

The invention provides a double-cable transmission line pulse testing system. Through developing a TLP (Transmission Line Pulse) test system, a target of quantitatively evaluating the performance characteristic of an electro-static discharge (ESD) protecting circuit is realized in a manner of simulating a real electrostatic discharging manner by means of a short-pulse square wave, thereby increasing a testing energy which is applied to two ends of a tested device, and improving testing result accuracy. The transmission line pulse testing system comprises a voltage transmission line part for charging and discharging, an attenuating filtering circuit structure which is used for matching a system impedance and attenuating the waveform of a reflecting pulse, and a leakage current testing part which is used for evaluating inner damage of the tested device, wherein a different resistance type attenuator design method is adopted for an attenuator part for matching an impedance change after matching. A Basel wave filter is used as a filter for realizing waveform edge shaping and realizing rare overshoot.

An automatic transmission line pulse testing system is characterized in that a transmission line, a first switch device, a high voltage source meter, an attenuator, a rise time filter, a voltage and current collecting device, a second switch device and a processor are included; the transmission line is connected with the attenuator and the high voltage source meter through the first switch device, the attenuator is connected with the rise time filter, the rise time filter, the voltage and current collecting device and the high voltage source meter are connected with a device to be tested through the second switch device, and the processor is connected with the high voltage source meter, the voltage and current collecting device, the first switch device and the second switch device. The cost of the system is lowered, and the system is easy to implement and high in reliability.

A tunable frequency transmission line pulse forming network circuit for forming a waveform having a spectral content. The pulse forming network circuit comprises a dielectric material; a ground section; a stepped shaped charged section, with the charged section having a plurality of stages including a first stage; a power supply coupled to the pulse forming network circuit for charging the pulse forming network circuit; a switch coupled to the pulse forming network circuit for periodically discharging the pulse forming network circuit; and an antenna coupled to the pulse forming network circuit for propagating a high-power microwave signal from the pulse forming network circuit into the environment. At least the first stage of pulse forming network circuit has one of a tunable magnetic material and a nonlinear magnetic which facilitates adjusting the waveform and the spectral content of the waveform emitted by the pulse forming network circuit into the surrounding environment.

The invention provides an LED leakage current test method under different wavelength conditions. The method comprises the following steps of: accessing an LED to be tested to a TLP (Transmission Line Pulse) test system under the condition of constant temperature, and testing the leakage current of the LED through the action of rectangular short pulses with continuous adjustable amplitude. In one embodiment of the invention, an integrating sphere is introduced in order to increase testing accuracy and eliminate the influence of light sources with different shapes in different positions. When light beams enter the integrating sphere, an ideal diffusing source is formed through multiple times of diffuse reflection. Thus, the interference brought by the light sources can be eliminated, and the influence brought by the nonuniformity of the illuminated face of the LED to be tested can be eliminated.

An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider.

The invention discloses a method for evaluating the heat dissipation characteristic of a radio frequency power LDMOS device. The method comprises the following steps: testing the LDMOS device to be tested by using a transmission line pulse testing device to obtain an IV testing curve; carrying out linear fitting on the rising section part in the IV testing curve to obtain a parasitic resistance value of the LDMOS device to be tested; obtaining a parasitic resistance change factor of the LDMOS device to be tested through the parasitic resistance value of the LDMOS device to be tested; and comparing the parasitic resistance change factor with a preset threshold, and judging the heat dissipation characteristic of the LDMOS device to be tested according to a comparison result. According to theinvention, the convenience and conciseness of evaluating the heat dissipation characteristic of the LDMOS device to be tested are improved.