1235results about How to "Improve bandwidth utilization" patented technology

A transmitter subsystem generates an optical signal which contains multiple subbands of information. The subbands have different polarizations. For example, in one approach, two or more optical transmitters generate optical signals which have different polarizations. An optical combiner optically combines the optical signals into a composite optical signal for transmission across an optical fiber. In another aspect, each optical transmitter generates an optical signal containing both a lower optical sideband and an upper optical sideband (i.e., a double sideband optical signal). An optical filter selects the upper optical sideband of one optical signal and the lower optical sideband of another optical signal to produce a composite optical signal.

The invention provides a DRAM (dynamic random access memory)-NVM (non-volatile memory) hierarchical heterogeneous memory system adopting software and hardware collaborative management. According to the system, an NVM is taken as a large-capacity NVM for use while DRAM is taken as a cache of the NVM. Hardware overhead of a hierarchical heterogeneous memory architecture in traditional hardware management is eliminated through effective use of certain reserved bits in a TLB (translation lookaside buffer) and a page table structure, a cache management problem of the heterogeneous memory system is transferred to the software hierarchy, and meanwhile, the memory access delay after missing of final-stage cache is reduced. In view of the problems that many applications in a big data application environment have poorer data locality and cache pollution can be aggravated with adoption of a traditional demand-based data prefetching strategy in the DRAM cache, a Utility-Based data prefetching mechanism is adopted in the DRAM-NVM hierarchical heterogeneous memory system, whether data in the NVM are cached into the DRAM is determined according to the current memory pressure and memory access characteristics of the applications, so that the use efficiency of the DRAM cache and the use efficiency of the bandwidth from the NVM main memory to the DRAM cache are increased.