19 results about "Cache pollution" patented technology

The invention discloses a cache partition dynamic allocation method and device, equipment and a storage medium, and relates to the technical field of storage, and the method comprises the following steps: obtaining an initial cache hit rate and an initial data transmission bandwidth of each I / O data stream; adjusting cache resources corresponding to the I / O data stream for multiple times according to a preset cache step length adjustment rule, and obtaining an adjusted cache hit rate and a data transmission bandwidth; according to the initial cache hit rate, the initial data transmission bandwidth, the adjusted cache hit rate, the adjusted data transmission bandwidth and the cache resource adjustment vector, generating cache sensitivity; after all the cache sensitivities are obtained, sorting all the cache sensitivities; and according to the sorting result and a pre-configured cache resource adjustment rule, determining to dynamically adjust the cache resources of part or all of the I / O data streams. According to the method, performance reduction caused by cache pollution and resource competition is effectively reduced, and cache resources are utilized more efficiently.

The invention relates to the technical field of computers, in particular to a data pre-reading method and electronic equipment, and the method comprises the steps: taking a current input / output access request as a center, and backtracking a historical input / output access request in a preset sliding time window, generating an original input / output sequence according to the current input / output access request and the historical input / output access request, performing feature extraction to obtain an input / output feature vector, performing standardization processing to obtain a standardized input / output feature vector, and inputting the standardized input / output feature vector into a pre-trained support vector machine model; and if the prediction probability value is greater than or equal to a preset trigger threshold value, executing a pre-reading operation on the target associated data block. Therefore, probabilistic prediction is carried out through the machine learning model based on the multi-dimensional features, and a self-adaptive pre-reading execution strategy is combined, so that the problems that the recognition capability of a complex access mode is poor, and cache pollution or insufficient pre-reading is easily caused in related technologies are solved.

The invention provides a security risk quantitative evaluation device for a DNS recursive resolution system, the evaluation device is used for detecting parameters of the DNS recursive resolution system through preset five dimensions to evaluate a security risk index of the DNS recursive resolution system, the evaluation device comprises a client and an authoritative end, the client is connected with the authoritative end, and the authoritative end is connected with the DNS recursive resolution system. The client is used for sending a plurality of different DNS requests to the DNS recursive analysis system so as to deploy a plurality of automatic measurement probes in the DNS recursive analysis system, and five preset dimensions comprise a cache pollution dimension, a DNS hijacking dimension, a dimension of directly attacking a recursive server, a dimension of attacking other servers by utilizing recursion and a DNS service software vulnerability dimension; the authoritative end is used for analyzing to-be-tested parameters in the DNS recursive analysis system and returning an analysis result to the client; the client is further configured to evaluate the overall security risk index of the system based on the detected parameters of each dimension.

The application relates to the technical field of storage, and particularly provides a data query method and device, electronic equipment and a storage medium. The data query method comprises the following steps: determining an initial prefetch rule based on a data query instruction; the initial prefetch rule is whether to adopt a cache disabling strategy and whether to adopt a prefetch disabling strategy; determining a first comparison result between a current cache data amount and a cache disabling threshold value and a second comparison result between a memory locking data amount and a memory disabling threshold value; determining a target prefetch rule according to the initial prefetch rule, the first comparison result and the second comparison result; and performing a data query operation according to the target prefetch rule. In this way, the target prefetch rule of the data query is dynamically adjusted according to multiple dimensions of the query instruction, the current cache data amount and the memory locking data amount, so that the device memory occupied by prefetching can be reasonably controlled, and the problem of cache pollution can be reduced.

The invention relates to the technical field of memory allocation of a multi-core processor architecture, and relates to a memory allocation system, method and device based on a multi-core processor and a medium. The system comprises a main processing core used for executing a general-purpose computing task of a user application program; the special allocation processing unit is used for intensively processing all dynamic memory allocation and release requests initiated by the main processing core; the private metadata storage area is used for storing all metadata required by memory allocation, and the metadata are only accessed by the special allocation processing unit; the on-chip network bus is connected with the main processing core, the special distribution processing unit and the main memory DRAM, and is used for realizing data transmission and ensuring cache consistency; the DRAM, the common main memory of the processor and the main processing core apply for a memory area on the DRAM through the memory allocation core. Complete separation of metadata operation and a main core computing task is realized, and cache pollution and cross-core synchronization overhead are eliminated.

The embodiment of the invention provides a compiling optimization method and device and related equipment, and the method comprises the steps: in a program compiling process, based on a loop nested structure of a program, determining a write operation statement meeting a non-temporary storage condition, and marking non-temporary storage; aligning the write operation statements marked with non-temporary storage according to the vector width; cancelling the non-temporary storage mark of the write operation statement, traversing the intermediate representation of the program, determining the write operation statement meeting the non-temporary storage condition again, and marking the target non-temporary storage; and according to the write operation statement marked with the target non-temporary storage, a vector non-temporary storage instruction is generated, so that cache pollution is reduced, and the memory bandwidth utilization rate is improved.

The invention relates to a memory data management method, an unloading card and a memory data management system. According to the method, data needing to be unloaded in the computing equipment is identified by using an unloading card, and the identified data needing to be unloaded is unloaded to a target storage position. According to the memory data management method disclosed by the invention, the memory management function is unloaded to the unload card, so that frequent access of the CPU to the memory can be reduced, and the load of the CPU of the computing equipment is reduced. Meanwhile, the unloading card unloads the identified data to the target storage position, the CPU of the computing device does not need to access the memory of the computing device due to data unloading, the memory of the computing device is accessed only when the data needs to be used, and therefore cache pollution can be reduced. Moreover, the identified data needing to be unloaded can be directly unloaded from the memory of the computing device to the target storage position without passing through the CPU of the computing device, so that the data transmission efficiency can be improved.

The invention discloses a prefetching request processing method and device, equipment and a medium. The method comprises the following steps: firstly, initiating a prefetching request to an external memory according to a storage read pointer, distributing a first prefetching request identifier for the prefetching request in a prefetching request identifier resource pool, and updating state information of the prefetching request in response to a target event to represent validity of prefetching data requested by the prefetching request. And determining corresponding state information in the resource pool according to a second prefetching request identifier carried by the prefetching data. And finally, determining whether the prefetched data is valid or not according to the state information, and executing cache writing operation on the valid prefetched data. The state of each prefetch request is uniquely identified and tracked in the whole process through the prefetch request identifier, the state information and the unique identifier, and the cache writing operation is controlled according to the validity information when the prefetch data is returned, so that invalid data is identified and discarded, cache pollution is avoided, only valid data is saved in the cache, the invalid data is prevented from occupying the cache space, and the cache efficiency is improved. And the cache utilization rate is improved.

This invention discloses a data classification and processing method and system for parallel computing on multi-core processors, relating to the field of data classification and processing technology. This invention effectively addresses the challenge of abnormal disturbances in multi-core parallel data classification through a confidence-driven heterogeneous pipeline architecture; based on dynamic hierarchical processing of data block confidence, it ensures the complete processing chain for high-confidence data while implementing rapid classification and cache isolation for low-confidence data, preventing abnormal data from blocking the pipeline; an adaptive window segmentation mechanism links confidence fluctuations with computing resource allocation, mitigating inter-core load imbalance caused by sudden anomalies; and a dual closed-loop control strategy combines real-time queue status with historical load patterns, reducing the risk of cache pollution caused by thread migration.

A cache pollution attack detection and defense method based on deep reinforcement learning is presented. It includes steps such as constructing state data, constructing an online neural network and a target neural network, constructing and training the online neural network, and performing cache pollution attack detection and defense. The advantages of this invention are: by interacting with the environment and continuously updating the training, it can adapt well to the dynamic changes of the edge computing environment. Task requests and actions can cause fluctuations in edge caching. This invention improves the convergence of the method by virtually reapplying action data to the reward data of the original edge environment state. Furthermore, conventional cache pollution attack defense methods do not consider the impact of falsely rejecting normal task requests and forwarding suspected malicious requests. Therefore, this invention, based on the statistical characteristics of IoT devices, jointly restricts service content caching and restricts task request forwarding, improving performance indicators such as detection rate and edge cache hit rate while balancing false rejections and forwarding burden.

The invention discloses an adaptive cache replacement method based on a dual-state counter, which belongs to the technical field of data caching, and comprises the following steps: performing improvement based on an adaptive cache replacement algorithm ARC, and designing an improved algorithm structure which comprises a dynamic adjustment mechanism, an LRU replacement algorithm structure, an LFU replacement algorithm structure and a cache item table, the cache item table comprises a data pointer, a timestamp for LRU sorting, a 2-bit saturation counter and cache data, designing a timing attenuation mechanism for preventing cache items which are not accessed for a long time from continuously occupying a high active state, adding a global bias counter, dynamically adjusting a state transition threshold, and adaptively balancing LRU and LFU strategies, so that the implementation structure can be simplified, and the implementation efficiency is improved. The cache hit rate and the system performance are improved, the cache pollution and the bandwidth overhead are effectively reduced, the adaptive capacity of the cache to different access modes is enhanced, and the overall performance and the energy efficiency of a computer system are improved.

Systems and techniques for software-guided prefetch throttling based on memory region boundaries are described. In one example, a processor includes a cache system having a cache system and a hardware prefetcher associated with a cache level of the cache system. The hardware prefetcher receives a boundary hint from a workload of an execution unit that accesses the cache level. The hardware prefetcher throttles prefetch requests based on the memory hint being satisfied. The described techniques overcome cache pollution from conventional prefetchers without limiting a prefetcher's ability to identify and respond to stride access patterns.

This invention discloses a cache pollution attack defense system, method, and storage medium for information-centric networks based on a grey Markov model, belonging to the field of network security technology. This invention utilizes the results of cache pollution detection for efficient defense, preventing suspicious content from occupying cache space. It uses a grey Markov model to predict the popularity of suspicious content and continuously monitors it using the predicted popularity value, the uniformity of content request distribution across different paths, and the number of hops returned by data packets, returning normal content to the cache. This invention can use a blacklist for timely defense against attack content, and then filter the content in the blacklist, removing normal content, thereby improving upon the problems of existing methods being slow and prone to mistakenly attacking normal content, thus achieving timely and efficient defense.

The present disclosure relates to a memory data management method, an offload card, and a system. In the method, the offload card is used to identify data that needs to be offloaded from a computing device, and offload said identified data to a target storage location. In the memory data management method of the present disclosure, a memory management function is offloaded to the offload card, frequent access of a CPU to a memory can be reduced, and the load of the CPU of the computing device can be reduced. Additionally, the offload card offloads the identified data to the target storage location, enabling that the CPU of the computing device does not need to access the memory of the computing device because of the need to offload data, and accesses the memory only when the data is needed for usage, thereby reducing cache pollution. Moreover, the identified data that needs to be offloaded can be directly offloaded from the memory of the computing device to the target storage location without participation of the CPU of the computing device, improving data transmission efficiency.

The invention discloses a self-adaptive hardware data prefetcher switch control method and device, and the method comprises the steps: obtaining memory access information from a high-speed cache based on an index collector, calculating a prefetch validity index of each prefetcher in stages, and transmitting the prefetch validity index to a control center, the prefetch validity index is constructed based on three parts of an access delay reduction value brought by a useful prefetch request, an access delay increase value caused by cache pollution and a conventional memory access delay increase value caused by the prefetch request; and judging according to the prefetching validity index of each prefetching device based on the control center so as to adaptively control the switch of each prefetching device. According to the invention, the on-off state of the prefetcher can be adaptively adjusted according to the prefetch validity index, and hardware data prefetch on-off control with high performance and low storage overhead is realized.

Systems and techniques for low-power prefetching are described. In one example, a processor includes a cache system having a hierarchy of one or more cache levels and a prefetcher associated with a cache level of the cache system. The prefetcher determines a memory level from which data or instructions associated with a prefetch request is retrieved. In response to the data or instructions being retrieved from a level three cache, a lower cache level, or system memory, the prefetcher stores the data or instructions associated with the prefetch request in a level two cache. The described techniques reduce cache pollution in the level one cache without introducing additional storage overhead.

The invention relates to the technical field of distributed cache and memory computing, and discloses an SLRU page replacement algorithm optimization method based on Apache Ignite, and the method comprises the steps: constructing an improved SLRU data structure comprising a trial segment and a protection segment, and a page heat table based on an array index; the page access request is responded to update the popularity, access judgment based on a popularity threshold value is executed, and the page popularity is promoted to a protection section only when the page popularity of a trial section meets an access condition; monitoring the page view and the time interval, triggering dynamic heat attenuation, calculating an attenuation coefficient according to the hit rate of the protection section, and updating the total heat; monitoring the hit rate of the protection section, calculating the capacity expansion and contraction proportion, and dynamically adjusting the capacity proportion of the trial section and the protection section. Through the independent popularity model, the strict admission mechanism and the self-adaptive adjustment strategy, the cache pollution is effectively reduced, the problem of historical popularity lag is solved, and the cache hit rate and the resource utilization rate in a high-concurrency environment are improved.

The invention discloses a negotiation-based CNAME cache pollution problem prevention method, which comprises the following steps of: firstly, newly adding a strick pseudo resource record in a DNS (Domain Name Server) message, packaging the strick pseudo resource record in a query request by a client according to requirements, and endowing the query request with an integer value; after the recursion server detects the record, the CNAME record is ignored in a cache search stage, and recursion is initiated to an upstream authority to obtain a target type resource record and TTL thereof when the CNAME record is not hit; and then performing differentiation processing on the existing CNAME cache with the same name according to the string value, and finally writing a new record into the cache and returning a response. The strict record only acts between the client and the recursive server and is not transmitted to the upstream, so that the polluted cache can be weakened or cleared immediately without increasing extra memory overhead, and the method is compatible with the existing DNS protocol.

This invention belongs to the field of data prefetching technology, and particularly relates to a cache data prefetching processing method based on neural networks. This invention designs a perceptron and an evaluation mechanism. The perceptron uses a lightweight multilayer perceptron to learn from historical access records and quickly infers access patterns when access addresses are updated, thereby dynamically selecting a suitable prefetcher. The evaluation mechanism uses the average access state within a short window to predict the accuracy of the address and assigns a score, updating the prefetcher in a timely manner based on the score. This invention constructs a lightweight integrated prefetcher, unifying and dynamically scheduling multiple different prefetchers online, and quickly selecting the optimal prefetcher based on the current memory access behavior, thereby improving prefetch accuracy, cache hit rate, and processor execution efficiency, while reducing cache pollution caused by erroneous prefetching.