DRAM (dynamic random access memory)-NVM (non-volatile memory) hierarchical heterogeneous memory access method and system adopting software and hardware collaborative management

Abstract

The invention provides a DRAM (dynamic random access memory)-NVM (non-volatile memory) hierarchical heterogeneous memory system adopting software and hardware collaborative management. According to the system, an NVM is taken as a large-capacity NVM for use while DRAM is taken as a cache of the NVM. Hardware overhead of a hierarchical heterogeneous memory architecture in traditional hardware management is eliminated through effective use of certain reserved bits in a TLB (translation lookaside buffer) and a page table structure, a cache management problem of the heterogeneous memory system is transferred to the software hierarchy, and meanwhile, the memory access delay after missing of final-stage cache is reduced. In view of the problems that many applications in a big data application environment have poorer data locality and cache pollution can be aggravated with adoption of a traditional demand-based data prefetching strategy in the DRAM cache, a Utility-Based data prefetching mechanism is adopted in the DRAM-NVM hierarchical heterogeneous memory system, whether data in the NVM are cached into the DRAM is determined according to the current memory pressure and memory access characteristics of the applications, so that the use efficiency of the DRAM cache and the use efficiency of the bandwidth from the NVM main memory to the DRAM cache are increased.

Description

technical field [0001] The invention belongs to the field of caching performance optimization in a heterogeneous memory environment. Specifically, a DRAM-NVM layered heterogeneous memory access method and system for software and hardware cooperative management are designed, and a Utility-Based data is proposed on the basis of the system. prefetch mechanism. Background technique [0002] With the development of multi-core and multi-thread technology, dynamic random access memory (Dynamic Random Access Memory, DRAM) has been unable to meet the increasing memory requirements of applications due to power consumption and process limitations. New non-volatile memory (None-VolatileMemory, NVM), such as phase change memory (PhaseChangeMemory, PCM), spin transfer torque magnetic random access memory (SpinTransferTorqueMagnetoresistiveRandomAccessMemory, STT-MRAM), magnetic random access memory (MagneticRandomAccessMemory, MRAM), etc. Node addressable, read and write speeds are not m...

AI Technical Summary

Problems solved by technology

However, compared with DRAM, these new non-volatile memories still have many defects: (1) the reading and writing time is extended, the reading speed is an order of magnitude slower than DRAM, and the writing speed is two orders of magnitude slower than DRAM; (2) the power consumption of writing (3) The service life is limited, so it is not feasible to directly use them as computer main memory

After the last level of on-chip cache is missing, first look up the identification corresponding to the access address through the hardware circuit in the DRAM memory controller, judge whether the access is hit in the DRAM cache, and then perform data access. It can be seen from this that hierarchical heterogeneity The memory access latency of the memory system is relatively long when the DRAM cache is missing

In addition, the DRAM cache managed by hardware generally adopts the Demand-Based data prefetch mechanism, that is, after the data in the DRAM cache is missing, the corresponding NVM data block must be fetched into the DRAM before the data block can be accessed. Many applications have poor locality, and this data prefetching mechanism will exacerbate the cache pollution problem

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