108 results about "Cache capacity" patented technology

The invention discloses a matrix calculation adaptive optimization method and system based on an ARM architecture. The method comprises the following steps: preprocessing to-be-processed matrix data; performing local activeness calculation and hot spot region identification on the preprocessed matrix data, and determining long-tail distribution characteristics of the matrix; calculating the optimal block size range of the matrix based on the long tail distribution characteristics of the matrix and the multi-level cache capacity parameters in the processor information, and generating an asymmetric block scheme; based on an asymmetric partitioning scheme, establishing a mapping relation between matrix features and optimal partitioning parameters; calculating the calculation density and the memory access mode of each block based on the asymmetric block scheme and the mapping relation, and generating a task scheduling scheme; based on the task scheduling scheme, matrix calculation is executed on the processor, and a final calculation result is output. According to the method, self-adaptive blocking and heterogeneous core scheduling are realized by identifying the long tail distribution characteristics of the matrix, and the performance and energy efficiency of matrix calculation on ARM are improved.

The invention discloses a network-on-chip routing method and device, routing nodes, equipment, a medium and a product, and relates to the technical field of network-on-chip, and the method comprises the steps: firstly, screening the routing nodes through employing the input direction of a message, and limiting the selection range of the next-hop routing node; the relative position of the target routing node relative to the current routing node is determined, the routing nodes are further screened according to the relative position, and candidate routing nodes are determined; and determining a next-hop routing node according to the cache capacity and the input direction of the candidate routing node, and transmitting the message to be transmitted to the next-hop routing node to complete routing. The problem that the routing of the network-on-chip is easy to cause network message blockage or link failure of the network-on-chip can be solved. According to the method, an input direction is adopted to limit a selection range of a next-hop routing node, a relative position is adopted to determine candidate routing nodes, the next-hop routing node is determined in the candidate routing nodes based on cache capacity, and self-adaptive deadlock-free routing is realized.

The invention relates to the technical field of computing resource optimization, and discloses a joint resource allocation and task unloading optimization method and system, and the method comprises the steps: constructing a global resource view to sense the real-time residence state of each computing node cache line in a distributed system; a cache-aware task unloading and data prefetching combined optimization model is established, decision variables of the model include task unloading variables and data prefetching variables at the same time, and cache capacity constraints are constructed in an endogenous mode by means of a task unloading scheme so as to predict a cache line set to be expelled due to task execution; the joint optimization model is solved with the purpose of minimizing the total task completion time, a task unloading decision and a collaborative prefetching decision are synchronously generated, and the prefetching decision is determined according to the predicted expelling set and the task data dependency relationship. According to the method, task unloading and data prefetching are cooperatively decided in a unified optimization framework, so that the problem of mutual interference caused by independent optimization of task unloading and data prefetching is solved, and global active arrangement of calculation and cache resources is realized.

The invention discloses a high-speed multi-port cache arbiter with a variable word length. Along with the high-speed development of the modern network technology, storage management and scheduling take up most of time in the processing of data packets by network equipment, so that the low-speed caching capability of most memories becomes a bottleneck for limiting the further improvement of a network processor. Therefore, by managing the shared cache of not less than 32 blocks of 256Kbit SRAM units and supporting simultaneous cache writing of a plurality of ports through an arbitration mechanism, write scheduling and read scheduling can be realized without mutual influence, and concurrent read-write conflicts are avoided; meanwhile, each port supports eight priority queues, so that the data transmission bandwidth of each port can reach 1G bps; by processing a data packet, caching and data scheduling according to packets are supported, the length of the data packet is 64-1024 bytes variable, and the influence of the length of the data packet on memory resources can be avoided; and the purpose of storing resources can be achieved by dynamically adjusting space saving through memory recovery, and the data storage efficiency is improved.

The invention relates to a serial port instruction intelligent processing method and device based on multi-frame cache and a storage medium. The method comprises the steps that a system is initialized; starting serial port interruption to receive a serial port AT instruction; the received instruction is analyzed; after analysis is completed, the AT instructions are further classified; after instructions are classified and stored in corresponding queues, the system adopts a priority scheduling algorithm to determine which instruction is processed preferentially; and the system executes corresponding operation according to the specific content of the instruction. According to the method, a multi-level cache pool technology is adopted, a virtual cache queue is constructed on a software layer, the equivalent cache capacity is expanded, and the situation that a hardware buffer overflows or instructions are lost due to insufficient process processing capacity is avoided; a priority instruction scheduling algorithm is introduced, instruction grades are dynamically divided, key instructions are ensured to be processed preferentially, and the problem that a traditional single-frame mode cannot respond in time when the MCU is in a high load state is solved; and meanwhile, enhanced frame identification of the protocol is realized, and the problem of insufficient error correction capability of a traditional mode is solved.

This invention discloses a cache adjustment method, apparatus, device, and computer-readable storage medium, comprising: collecting access characteristic data from the client layer, object storage daemon layer, and device layer respectively; determining the object access mode of the system based on the access characteristic data; and adjusting the cache priority of each access task, the cache capacity ratio between the client layer and the object storage daemon layer, and the data residence time in the cache layer according to the object access mode; wherein the cache layer includes the client layer and the object storage daemon layer. This invention improves cache hit rate and overall read / write throughput performance, and reduces access latency.

This application provides a cache space management method and storage device. The method includes: acquiring indicators for adjusting the allocation of cache resources in the cache space, and calculating the cache urgency factor of the cache space; determining the caching strategy of the cache space based on the cache urgency factor and preset first and second thresholds; in response to the caching strategy of the cache space, adjusting the cache capacity of the cache space, and calculating the cache adjustment amount of the cache space based on the cache urgency factor; and adaptively adjusting the capacity allocation of the first cache area and the second cache area in the cache space based on the cache adjustment amount. The above method, by monitoring cache usage and access patterns in real time, adaptively adjusts the allocation of cache resources, optimizes cache resource utilization, and improves the overall performance of the storage device in scenarios such as random reads.

The invention discloses an online recharging service management system based on cloud edge cooperation. The system comprises a sudden change detection module, an implicit state judgment module, an adjustment factor construction module, a duration modeling module, a cloud updating module and a parameter cooperation adjustment module. The mutation detection module is used for monitoring delay, packet loss density and jitter amplitude and generating a mutation mark. And the implicit state judgment module is used for dividing network states into stable, jitter, weak network and interrupt categories. And the regulation factor construction module is used for extracting interval offset, period increment, category switching and active period information. The duration modeling module is used for calculating the state staying duration. And the cloud updating module is used for correcting duration time distribution in an increment mode and deducing duration time prediction parameters of a future window. And the parameter cooperative adjustment module is used for mapping the prediction result into an acceptance limit, a cache capacity and a strategy threshold value and issuing the values to the edge node. According to the invention, the processing continuity and the resource allocation efficiency under the weak network condition are improved.

The invention provides a cache management method and device, a storage medium and a product. The method comprises the steps that Internet of Vehicles system data in each time period are obtained, the Internet of Vehicles system data comprise state information, position information, cache capacity and an accessibility matrix of each roadside unit, the state information comprises data demand information and identification information and concentration value of cached data, and the data demand information comprises a target position and identification information of target data; based on the Internet of Vehicles system data, a data caching strategy of each time period is obtained through a strategy generation model, and the strategy generation model is established according to a deep reinforcement learning algorithm; based on a data caching strategy, caching management is performed on a target roadside unit set corresponding to the target position, the target roadside unit set comprises a first roadside unit and a second roadside unit, the first roadside unit is the roadside unit closest to the target position, and the second roadside unit is the roadside unit closest to the target position; the first roadside unit and the second roadside unit have communication accessibility meeting a preset condition.

The embodiment of the application discloses a kind of matrix operation method, device, electronic equipment and storage medium, belong to data processing technical field.The method includes: according to the cache capacity of each exclusive cache layer, determine a plurality of candidate basic block parameters, according to the transmission bandwidth between each adjacent cache layer, determine the estimated data throughput corresponding to each basic block parameter, according to estimated data throughput, determine target basic block parameter from multiple basic block parameters;According to target basic block parameter, determine a plurality of candidate core task quantity parameters, determine the data loading time corresponding to each core task quantity parameter according to target basic block parameter;According to data loading time, determine target core task quantity parameter;Get the first matrix and the second matrix to be processed, according to target basic block parameter and target core task quantity parameter, each computing core is scheduled, matrix operation is carried out on the first matrix and the second matrix and corresponding matrix operation result is obtained.The application improves the efficiency of matrix operation.

This invention discloses a large-scale two-dimensional convolution operator acceleration method for DSP platforms, belonging to the field of digital signal processing. This method selects the im2col or col2im algorithm to rearrange data based on the convolution type; adopts a three-segment matrix partitioning strategy to adapt to L3 cache capacity; utilizes an EDMA buffer ping-pong architecture to achieve pipeline parallelism for data transmission and computation; implements SIMD instruction-level optimization, using DMPYSP and DADDSP instructions in conjunction with pipeline optimization to achieve four FP32 multiplication and addition operations per cycle; and implements multi-core parallel scheduling, using OpenMP to achieve task-level and data-level parallelism. This method has been tested on a TI TMS320C6678 platform to achieve efficient inference of SAR target detection networks, providing a feasible solution for real-time inference of CNN networks on DSP platforms.

This application relates to an instruction fetching method, apparatus, and computer device based on a reduced instruction set (RISC). The method includes: obtaining the address of the instruction to be executed; searching for the address of the instruction to be executed in a cache block group; if a first or second cache block is hit, reading and outputting the instruction to be executed corresponding to the address of the instruction to be executed from the corresponding hit cache block; if a third or fourth cache block is hit, writing the instruction currently stored in the corresponding hit cache block into a free cache block in the first or second cache block; and reading and outputting the instruction to be executed corresponding to the address of the instruction to be executed from the free cache block. The entire instruction fetching process, by adding a small-capacity static prediction cache and a victim cache, forms a four-cache group interconnected structure with the dual cache blocks that implement general read / write operations. This improves the cache hit rate and achieves fast instruction fetching even with limited instruction cache capacity.

The invention discloses a cache optimization method and device based on distributed storage, and relates to the technical field of distributed storage systems. The method comprises the following steps: dynamically calculating a weight factor of a cache file, attenuating the weight factor based on the access frequency and timeliness of the file, and compensating and adjusting according to the size of the file; the maximum file threshold value set by the system is dynamically adjusted according to the size distribution of the files in the cache, and the maximum file threshold value is determined based on a preset quantile range so as to eliminate interference of extremely large files on weight calculation; when the weight factor of the cache file is lower than a preset threshold value, the file is removed from the cache, and the cache space is released; when the cache capacity is insufficient, the file with the minimum weight is selected for replacement based on the weight factor of the current cache file, and the high-value file is preferentially reserved in the cache. According to the method, the cache hit rate of small files in the distributed storage system is effectively increased, cache space waste and metadata operation overhead are reduced, and system performance and resource utilization rate are remarkably improved.

The invention relates to a Sencil calculation memory access concurrency performance prediction method based on a queuing theory. The method comprises the following steps: calculating memory access missing numbers under different cache capacities by utilizing a memory access missing number prediction model calculated by Stencil; obtaining CPU storage subsystem information, and extracting a processing process of the memory access request in the hardware device supporting memory access concurrency according to the CPU storage subsystem information; according to the CPU storage subsystem information, the memory access missing number, the processing process and the assumed condition, a memory access concurrency performance prediction model is constructed by using the queuing theory and the Littele law; calculating the memory access concurrency bottleneck of each memory access stream according to the memory access concurrency performance prediction model, and calculating the actual memory access bandwidth according to the memory access concurrency of the memory access concurrency bottleneck and the dynamic memory access delay by utilizing the Littele law; according to the actual execution bandwidth and the data access amount, the actual execution time of Sencil calculation is obtained through calculation. By adopting the method, the prediction precision of the Sencil calculation performance can be remarkably improved.

The invention discloses an underwater AUV (Autonomous Underwater Vehicle) service caching and switch state switching method based on a D3QN (Digital 3QN). The method comprises the following steps: firstly, for an ocean network formed by a water surface buoy node and an AUV, establishing an AUV service cache state and dormancy / activation state coupling control model; then, through consistent binding of a target switch state and a service cache write-in action, dormancy isolation constraint and a dormancy cache freezing rule, a feasible action mask meeting cache capacity constraint and anti-repeated write-in constraint is constructed; the method comprises the following steps of: firstly, constructing a comprehensive cost function according to cache update time overhead, write-in energy consumption, switch state switching cost and invalid activation penalty, and finally, solving in a legal action subspace by using D3QN, and outputting an AUV service cache and switch state switching control strategy. According to the invention, AUV service cache updating and switch state switching under the dynamic load can be effectively realized, and underwater network energy consumption and service cache updating delay are reduced.

The present disclosure provides a memory resource management method, an electronic device, a readable medium and a program product. The memory resource management method of the present disclosure is applied to a storage server, the storage server comprising at least one adjustment object, the adjustment object being a storage service unit meeting a cache memory adjustment requirement, and the method comprising: obtaining, in response to a dynamic adjustment instruction, memory parameter target values of the adjustment objects according to a preset allocation strategy based on an allocable memory capacity; the memory parameter target value of the adjustment object being a parameter value for adjusting the cache capacity of the adjustment object, and the preset allocation strategy comprising allocation according to allocation weights of the adjustment objects or average allocation according to the number of the adjustment objects; and for any one of the at least one adjustment object, updating the memory parameter of the adjustment object by using the memory parameter target value of the adjustment object in the case that the memory parameter target value of the adjustment object and the corresponding memory parameter current value are different.

The application provides a cache allocation method, device, equipment, medium and program product, and relates to the technical field of artificial intelligence. The method comprises the following steps: acquiring a multi-feature data stream, and extracting a target feature vector of the multi-feature data stream; inputting an expected cache miss rate set by a user in advance and the target feature vector into a cache strategy decision model, outputting an optimal cache eviction strategy, and inputting the optimal cache eviction strategy, the expected cache miss rate set by the user in advance and the target feature vector into a cache capacity prediction model, and outputting a target cache capacity allocation result. In the application, real-time data streams are taken as inputs to realize optimal strategy selection of a cache eviction strategy pool and optimal resource allocation of cache capacity respectively. Through mutual promotion of working capabilities of the cache strategy decision model and the cache capacity prediction model, the two cache management modes are efficiently realized, the management cost is greatly reduced, and the resource efficiency is improved.

The application belongs to the technical field of electronic evidence, and particularly relates to a full-link adaptive parallel data stream acceleration method and device and a storage medium, which comprises the following steps: monitoring the data stream state of a multi-protocol interface in real time; adopting an intelligent prefetch engine and an asynchronous decoupling pipeline to perform data reading scheduling; performing hardware parallel analysis on the data from different protocol interfaces in the physical layer and the link layer, extracting effective data load and address information, and reconstructing into a unified format data descriptor; storing the unified format data descriptor into a cache matrix; if the output rate of a device connected with the protocol interface is greater than the processing rate of a host, dynamically expanding the cache capacity of the cache matrix; when detecting that the host side is idle, initiating burst data transmission according to the maximum effective bandwidth of a PCIe interface connected with the host, and simultaneously adopting a write pointer lag control strategy to smoothly output the data stream; and through a DMA mechanism, directly writing the burst transmission data stream into the host memory bypassing the host CPU. The scheme realizes efficient electronic evidence.

An embodiment of the present invention provides an adaptive cache dynamic adjustment method, which includes: monitoring the operating status of a switch and regularly collecting port traffic information of the switch; calculating the load data of the switch in the operating state based on the port traffic information; and comparing the load data with a preset load performance benchmark to obtain a first evaluation result for the switch; calculating the current cache usage information of the switch based on the port traffic information; and comparing the cache usage information with a preset cache performance benchmark to obtain a second evaluation result for the switch; and finally, combining the first evaluation result and the second evaluation result to generate a cache adjustment policy for the switch, and adjusting the switch cache according to the cache adjustment policy. By monitoring the real-time workload and cache utilization of the switch, the embodiment of the present invention automatically adjusts the cache capacity and replacement policy to maximize cache utilization efficiency.

The invention provides a data rearrangement method, a network-on-chip system and a computer readable storage medium, and the method comprises the steps: obtaining the minimum data value of a plurality of pieces of to-be-transmitted data, and configuring a rearrangement cache space; segmenting the plurality of pieces of data to be transmitted to obtain a plurality of pieces of segmented data, storing the plurality of pieces of segmented data in a rearrangement cache space, and enabling the link pointer data corresponding to the storage position of the segmented data in the rearrangement cache space to be address position information of the next segmented data of the segmented data; and reading the segmented data according to the link pointer data, integrating the segmented data into target transmission data, and sending the target transmission data to a target host. The network-on-chip system comprises a plurality of hosts, a router and a rearrangement processing unit, the plurality of hosts are connected with the router through a network interface unit, and the router is connected with the rearrangement processing unit. According to the method, the host shares the rearrangement processing unit, and the cache capacity of the rearrangement processing unit is reduced.

The invention relates to the technical field of control or regulation systems, and discloses a special equipment display screen data interaction method with CAN communication. According to the method, CAN bus operation parameters and data frame attribute information are collected, the transmission priority is calculated through multi-dimensional indexes, the Baud rate of sending equipment is automatically recognized, analysis parameters are adjusted, the data cache capacity is dynamically adjusted, and a display screen is controlled to process and display data according to the priority. According to the method, the problems of data transmission congestion, key data delay and poor baud rate compatibility in the prior art are solved, the data transmission integrity and key information timeliness are guaranteed, the method is adaptive to CAN equipment with different baud rates, the method is suitable for a multi-equipment CAN communication data interaction scene of special equipment, and the real-time and safety requirements are met.

The application provides a kind of star-ground fusion network differentiated service flow deterministic transmission scheduling method and system, belongs to communication network technical field, according to the total demand of service flow, based on the elastic transmission algorithm of cache utilization of genetic, calculate the complementary star-ground cross-domain peak cache resource reserved, and carry out the adaptive optimization of cache resource in domain, obtain the domain node resource allocation result;According to node resource allocation result, based on the transient routing and variable queue algorithm of deep reinforcement learning, the two-dimensional scheduling of routing-queue is carried out to service flow, and deterministic transmission scheduling is carried out to meet the differentiated cache capacity demand and time demand of service flow.The application makes up the defects of traditional STIN network architecture, such as lack of differentiated deterministic service concept and loose adaptation between protocol stack levels, significantly improves the deterministic communication guarantee capability of network in different scenarios, and provides strong support for efficient operation and reliable transmission of STIN.

The invention discloses a data moving method and device, equipment and a storage medium, and the method comprises the steps: calculating a hash value of each piece of data in a local cache, the hash value being used for representing a node identifier for receiving the data; creating an array with the same capacity as the local cache, and storing the hash value of each data in the array in sequence; establishing a mapping relationship between the array and a local cache, and determining aggregated data from the local cache according to the mapping relationship; and obtaining a target hash value corresponding to the aggregated data, and copying the aggregated data to a target node cache matched with the target hash value to perform data movement. According to the embodiment of the invention, the hash array for marking and binding the data is created, the aggregated data is determined from the local cache according to the array, and the aggregated data with the same adjacent receiving nodes are copied to the target node cache at one time, so that the copying times are reduced, and the I / O load pressure is relieved.

Embodiments of the present application relate to the technical field of electronics. Disclosed are an electronic device and a method for accessing data. The electronic device comprises: a first processor, comprising an on-chip memory; and a system cache, comprising a first tag array, a second tag array, and a data array, wherein the first tag array is used for storing first tag information of the on-chip memory, and the second tag array is used for storing second tag information of the data array. The system cache is configured to: enable, by means of the first tag information, access to first system data stored in the on-chip memory; and enable, by means of the second tag information, access to second system data stored in the data array. According to the electronic device and the method for accessing data provided by the embodiments of the present application, the cache capacity of the electronic device can be improved.

The invention relates to a data transmission arbitration method and device and a storage medium. The method comprises the following steps: executing an arbitration operation on at least one received first command, and determining a thread group of a second command received in a current period; performing merging processing based on the thread group of the second command to obtain at least one related cache access request; adding the at least one cache access request to an access queue; executing an arbitration operation on at least one third command applying for arbitration in the access queue, and selecting a fourth command; and returning part or all of the data requested by the fourth command to the request module, and releasing the cache space occupied by the returned data. According to the embodiment of the invention, on the premise that the cache capacity is not increased and the structure of the upstream request module is not modified, the problems of read request accumulation and system deadlock caused by the fact that cache resources are fully occupied in the memory access process are effectively solved, and the continuous availability of a data path and the overall throughput performance of the system are remarkably improved.

The application discloses a kind of stereoscopic cache line, including machine table, cache carousel, fence, centrifugal material handling mechanism, input-output interface, feeding hub, discharging hub, feeding line, shunt runner, discharging line, the machine table is stereoscopically provided with two layers of cache carousel, the edge of the cache carousel is erected with fence, the disc surface of the cache carousel is provided with centrifugal material handling mechanism, the fence is provided with an input-output interface, the machine table is respectively erected with the feeding hub and the discharging hub that occupy at input-output interface.The above-mentioned mode, the application provides a kind of stereoscopic cache line, battery material is continuously input to cache carousel by feeding line, on the one hand, the cache capacity of stereoscopic stacking carousel is improved, on the other hand, input-output interface matching stacking hub is controlled downstream production line rhythm, so as to realize the continuous feeding requirement of more than one pull three scale, strong performance and high work efficiency, labor intensity is greatly reduced.

The invention discloses a trajectory and resource allocation optimization method and system in an unmanned aerial vehicle auxiliary cache system, and belongs to the technical field of wireless communication. The trajectory and resource allocation optimization method in the unmanned aerial vehicle auxiliary cache system comprises the steps of constructing the unmanned aerial vehicle auxiliary cache system, deriving a relationship between a user request time delay and an unmanned aerial vehicle hovering position, cache and trajectory based on unmanned aerial vehicle coverage radius and cache capacity constraints, establishing a user average request time delay minimization optimization problem, and optimizing the trajectory and resource allocation in the unmanned aerial vehicle auxiliary cache system. The optimization problem is decomposed into a user clustering sub-problem, a caching strategy sub-problem, a trajectory optimization sub-problem and a bandwidth power joint optimization sub-problem; and a neighbor clustering algorithm, a dynamic programming algorithm, an ant colony algorithm and a block coordinate descent algorithm are utilized to solve a user clustering sub-problem, a cache strategy sub-problem, a trajectory optimization sub-problem and a bandwidth power joint optimization sub-problem respectively, and finally an optimal user clustering, a cache placement strategy, an unmanned aerial vehicle flight trajectory and a bandwidth power distribution result are determined.

The application discloses a high-throughput large model inference method and device based on a time separation type pipeline architecture, equipment and a storage medium, relates to the technical field of large model inference, and the high-throughput large model inference method based on the time separation type pipeline architecture comprises the following steps: when the current inference stage is a pre-filling stage, pre-filling is performed according to a client request, and the key value cache capacity of each request decision point is determined; the stage switching time is determined according to the key value cache capacity of each request decision point and a preset memory capacity; the current inference stage is switched from the pre-filling stage to a decoding stage according to the stage switching time, and the client request is processed according to a preset load balancing strategy to obtain a target load balancing result; the inference of the large model is performed according to the target load balancing result and the pipeline architecture, and the output text corresponding to the client request is obtained according to the inference result. The efficiency of the high-throughput large model inference is improved.

The invention provides a multi-dimensional BOM collaborative management method based on a knowledge graph, a medium and a system, and belongs to the technical field of BOMs. Multi-dimensional BOM collaborative management architecture based on the knowledge graph is established, and multi-data-source BOM information is fused into a unified knowledge graph structure by adopting entity alignment and relation reasoning technologies, so that a multi-dimensional BOM collaborative management system based on the knowledge graph is obtained. A data organization mode is optimized by using a horizontal fragmentation storage strategy and a primary key attribute index, an intelligent cache strategy is constructed to identify a hotspot BOM sub-graph, and memory resource configuration is optimized by using a cache capacity function; a BOM intelligent optimization model is introduced, a multi-head attention mechanism and a recursive feature refining structure are adopted to realize intelligent decision-making of part type selection and an assembly path, and accurate BOM change influence analysis and control are realized through a graph traversal algorithm and a change propagation depth function. The technical problem of low query response efficiency caused by lack of unified collaborative management of multi-data-source BOM information is solved.

This invention relates to the field of data processing technology, and in particular to a data request processing method, apparatus, device, and medium. The method includes: adopting a scheme of separating cached metadata and cached data; using a redundant independent disk array card to uniformly manage read cached metadata; and utilizing a large-capacity host memory as a cached data storage area to decouple cached metadata and cached data. When a user's data processing request hits a cache line node in the cache area of ​​the redundant independent disk array card, the redundant independent disk array card sends the cached data address corresponding to the hit target cache line node to the host. The host processes the cached data corresponding to the cached data address on the host. Data processing can be performed directly from the host memory. By using the host memory as a cache pool, the cache capacity is greatly increased, thereby improving the data hit rate and data access speed.