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System and method for implementing memory mediation of supporting multi-bus multi-type memory device

A technology for implementing systems and memories, which is applied in the field of memory arbitration implementation systems, can solve problems such as clock cycles cannot be used to access memories, difficult verification, complex processing, etc., and achieve strong design reusability, good design flexibility and reusability , the effect of high bandwidth utilization

Inactive Publication Date: 2007-08-08
WUXI ZGMICRO ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For some memories with low bandwidth requirements, bus arbitration technology can be used; for other memories with high bandwidth requirements, memory arbitration technology can be used, but this method of combining bus arbitration technology with memory arbitration technology is different when switching between a bus master module. When the memory is accessed, the processing is complicated, it is easy to make some clock cycles cannot be used to access the memory, and it is not easy to verify various situations during verification

Method used

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  • System and method for implementing memory mediation of supporting multi-bus multi-type memory device
  • System and method for implementing memory mediation of supporting multi-bus multi-type memory device
  • System and method for implementing memory mediation of supporting multi-bus multi-type memory device

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Embodiment 1

[0053] Below in conjunction with the embodiment provided in Figure 4, the memory arbitration implementation system supporting multi-bus and multi-type memories of the present invention is further described:

[0054] As shown in Figure 4, the structure of each memory arbitration module in the m memory arbitration modules in the system of this embodiment is the same, wherein each memory arbitration module may include: a memory access arbitration module, and a memory access arbitration module related to the memory access The arbitration module is correspondingly connected with a memory control signal selection module, and the memory control signal selection module is also connected with n bus master modules.

[0055] Wherein, each memory access arbitration module receives memory access requests from n bus master modules, and arbitrates the received memory access requests, and outputs the arbitration result; that is, the memory access arbitration module accesses the memory accordin...

Embodiment 2

[0062] As shown in Fig. 5, with respect to Fig. 4, the system of the present embodiment also includes: n bus interfaces connected one-to-one with n bus master modules, and each bus interface provides a bus path;

[0063] Correspondingly, any memory access arbitration module can receive memory access request signals sent from n bus master modules through their one-to-one corresponding bus interfaces; n read data selection modules in the read data processing module output the read data from the memory, output to the n bus master modules through the n bus interfaces corresponding thereto one-to-one.

[0064] The above-mentioned bus interface is mainly used to process various types of bus protocols, and convert the received memory access request into a signal output by a unified output interface (for example, the bus interface provides a 3-bit access request line, a 16-bit read-write address line, a 16-bit byte selection line, which is equivalent to providing a unified output inte...

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Abstract

The invention discloses a memory arbiter system and implementation method that support multi-bus and multiple types of memory to solve the problem that multiple bus can not access multiple types of memory in existing technology. The invention includes: n bus main modules, the m memories, m arbiters which are connected to m memories correspondingly, the read data processing modules that are connected to n bus main modules, any memory arbiter module of the m memory arbiter modules can receive the memory access request issued by the n bus main modules; the memory arbiter module arbitrates the memory access requests and output the result; write to the memory corresponding to the memory arbiter; the read data processing module receives the arbitration results of m memory arbiter modules, and outputs the read data of corresponding memory to n bus main module according the arbitration result. It makes the multiple buses have access to multiple types of memory.

Description

technical field [0001] The invention relates to a system and method for realizing memory arbitration, in particular to a system and method for realizing memory arbitration supporting multi-bus and multi-type memories. Background technique [0002] With the technological development of system-on-chip (SOC) chips, more and more modules are integrated on a chip (including central processing unit CPU, digital signal processor DSP, and other dedicated hardware circuits, etc.), so memory (including on-chip Internal memory and off-chip memory) demand is also increasing, which includes two aspects of demand: 1. The demand for the capacity of the memory is increasing; 2. The demand for the type of memory is increasing. In practical applications, the multi-bus master module will send read / write requests to multiple memories at the same time. At present, the following technologies are mainly used in the memory arbitration of the memories: [0003] 1. Bus arbitration technology. Bus a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16
Inventor 李晓强
Owner WUXI ZGMICRO ELECTRONICS CO LTD
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