36results about How to "Consume bandwidth" patented technology

A method and apparatus for determining session parameters for a communication session between a first terminal (A) and a second terminal (B). At least the first terminal has stored at least one default set of session parameters. An identifier (404) corresponding to a proposed default set of session parameters is sent from the first terminal to the second terminal. Then, it is determined whether the second terminal accepts the proposed default set of session parameters or not. If accepted (406), the proposed default set of session parameters is retrieved in order to execute the session (408). Otherwise, the terminals fall back to a regular session setup procedure. In this way, delays and bandwidth consumption can be substantially reduced by using a minimum of messaging between the two terminals.

Systems and methods for providing carrier-centric data communications cost monitoring and controls are provided. In an embodiment, the method operates by receiving a registration request associated with a subscriber session, determining current data usage associated with the subscriber, and receiving data usage thresholds. The method further comprises receiving quotas associated with the subscriber session and collecting data usage information associated with the subscriber session. The method sends a notification to the subscriber when a pre-determined quota is exceeded during the subscriber session and controls data usage. The cost monitoring and control system comprises a usage policy server and a usage policy application. The usage policy application allows a carrier to offer alterations to terms of a subscription. The usage policy application displays current data usage information on a per-network and per-application basis using subscriber profile information, subscriber session information, and prior subscriber usage history provided by the usage policy server.

An integrated circuit, such as a processing unit, includes a substrate and integrated circuitry formed in the substrate. The integrated circuitry includes a processor core that executes instructions, an interconnect interface, coupled to the processor core, that supports communication between the processor core and a system interconnect external to the integrated circuit, and at least a portion of an external communication adapter, coupled to the processor core, that supports input / output communication via an input / output communication link.

A method is provided that supports partial cache line read and write operations to a memory module to reduce read and write data traffic on a memory channel. In a memory hub controller integrated in the memory module determines an amount of data to be transmitted to or from a set of memory devices of the memory module, in responsive to an access request. The memory hub controller generates a burst length field corresponding to the amount of data. The memory controller controls the amount of data that is transmitted to or from the memory devices using the burst length field. The amount of data is equal to or less than a standard data burst amount of data for the set of memory devices.

A memory system is provided that performs error correction at a memory device level that is transparent to a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises first error correction logic provided in write logic integrated in the memory hub device. The memory hub device comprises second error correction logic provided in read logic integrated in the memory hub device. The first error correction logic and the second error correction logic performs error correction operations on data transferred between a link interface and the set of memory devices. The memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code.

A memory system is provided that supports partial cache line write operations to a memory module to reduce write data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises burst logic integrated in the memory hub device. The burst logic determines an amount of write data to be transmitted to the set of memory devices and generates a burst length field corresponding to the amount of write data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of write data that is transmitted using the burst length field. The memory hub device transmits the amount of write data that is equal to or less than a conventional data burst amount.

An I / O communication adapter receives from a processor core an I / O command referencing an effective address within an effective address space of the processor core that identifies a storage location. In response to receipt of the I / O command, the I / O communication adapter translates the effective address into a real address by reference to a translation data structure. The I / O communication adapter then accesses the storage location utilizing the real address to perform an I / O data transfer specified by the I / O command.

A method of managing virtual routing forwarding (VRF) tables at a provider edge PE router of a L3 virtual private network (VPN) is provided. An import route target (ImpRT) tree is maintained at the PE router, which keeps the association between all ImpRT attributes currently configured on said PE router and the virtual routing table VRF at that router. When an ImpRT attribute is configured on a VRF table, the PE router first searches the tree to identify a local VRF table that contains a route(s) with that ImpRT attribute. If this information is available locally, the VRF is updated by copying the route information, and there is no need to do a route refresh. When an ImpRT is deleted from a VRF, a route refresh is avoided by parsing all the routes in the VRF and removing the routes that no longer have a matching route target. In an alternative implementation, the local source is the master RIB (routing information base) which includes all routes in all VRFs at the router, and optionally even rejected routes that were filtered out using ImpRTs. In this variant, even routes associated with ImpRTs that are new to the router would be available to update the VRF without requiring a route refresh.

Memory demands of large-memory applications continue to remain one step ahead of the improvements in DRAM capacities of commodity systems. Performance of such applications degrades rapidly once the system hits the physical memory limit and starts paging to the local disk. A distributed network-based virtual memory scheme is provided which treats remote memory as another level in the memory hierarchy between very fast local memory and very slow local disks. Performance over gigabit Ethernet shows significant performance gains over local disk. Large memory applications may access potentially unlimited network memory resources without requiring any application or operating system code modifications, relinkling or recompilation. A preferred embodiment employs kernel-level driver software.

A memory system is provided that supports partial cache line read operations to a memory module to reduce read data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub comprises burst logic integrated in the memory hub device. The burst logic determines an amount of read data to be transmitted from the set of memory devices and generates a burst length field corresponding to the amount of read data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of read data that is transmitted using the burst length field. The memory hub device transmits the amount of read data that is equal to or less than a conventional data burst amount of data.

A processing unit includes a processor core, an input / output (I / O) communication adapter coupled to the processor core, and a cache system coupled to the processor core and to the I / O communication adapter. The cache system including a cache array, a cache directory and a cache controller. The cache controller snoops I / O communication by the I / O communication adapter and, in response to snooping the I / O communication adapter performing an I / O data write of outgoing data in an exclusive state, invalidates corresponding data stored within the cache array.

Accesses to logical pages of memory are monitored. Each logical page corresponds to a logical memory address and the accesses defining an access pattern. The logical memory addresses are logged in ordered pairs of consecutive logical pages in the access pattern. Upon receipt of a request to write data to a given logical page, a given ordered pair of consecutive logical pages containing the logical memory address of the given logical page as a first logical memory address in the ordered pair of logical memory addresses associated with that consecutive pair is obtained. A first physical memory address mapping to the first logical memory address is identified, and a second logical memory address from that identified consecutive pair. A second physical memory address mapping to the second logical memory address is identified, and the data and the second physical memory address are written to the first physical memory address.