ESD (Electro-Static discharge) protection device with low trigger voltage and high balllast resistance for SCR (Silicon Controlled Rectifier)

Abstract

The invention discloses an ESD (Electro-Static discharge) protection device with low trigger voltage and high balllast resistance for an SCR (Silicon Controlled Rectifier), belonging to the technical field of electronics. By making use of the triggering of a heavily doped region and a substrate region in the vertical direction, the ESD protection device successfully transfers the avalanche breakdown from the surface of the device to the interior of the device, and with the addition of an STI (shallow trench isolation) region, the adverse effect of the silidide process is eliminated and the ballast resistance of the ESD protection device is effective improved.

Description

technical field [0001] The invention belongs to the field of electronic technology, and relates to the design technology of an electrostatic discharge (ElectroStatic Discharge, referred to as ESD) protection circuit of a semiconductor integrated circuit chip, especially a kind of silicon controlled rectifier (Silicon Controlled Rectifier, referred to as SCR) with low trigger voltage and high ballast resistance. ) ESD protection device. Background technique [0002] Electrostatic discharge is a common phenomenon in the process of manufacturing, producing, assembling, testing, storing, and transporting semiconductor devices or circuits. In the case of ESD, a large amount of charge will be transferred or transferred from the outside of the integrated circuit (IC) to the inside in a very short time, causing degradation of the performance of the integrated circuit or direct damage to the IC. In order to solve this problem, measures are usually taken in two aspects. The environme...

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Problems solved by technology

This will bring the following problems: for a process with lightly doped drain (LDD) implantation, the LDD region with a shallower junction depth will cause a drop in ESD performance due to tip discharge; the concentration of avalanche current at the surface will cause serious local overheating, cause premature thermal damage to the device

In addition, in order to improve the operation speed, integration, and reliability of the internal circuits of CMOS ICs, modern advanced CMOS processes generally use metal silicide processes (Silicide) to reduce the series resistance of MOS devices at the drain and source terminals; but from From the perspective of ESD protection, the silicide process will reduce the internal ballast resistance of the device, which will cause uneven current, resulting in local overheating and burning of the device

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