50 results about "Common drain" patented technology

The invention discloses a double-sided heat dissipation common drain module packaging structure, and belongs to the technical field of power semiconductor device packaging. The module comprises a common drain electrode upper copper layer, two drain electrode copper terminals, two power chips, two source electrode copper blocks, two L-shaped source electrode lower copper layers, two driving grid electrode copper terminals, two driving source electrode copper terminals and a bonding wire. Drain electrodes of the two power chips are welded on the common drain electrode upper copper layer, and source electrodes of the two power chips are respectively welded with the L-shaped source electrode lower copper layer through source electrode copper blocks. And the bonding wire is connected with the grid electrode and the source electrode of the chip and the driving copper terminal to realize Kelvin connection. Thermal resistance is reduced through a double-sided heat dissipation structure, parasitic inductance is reduced through a three-dimensional commutation loop, power density and reliability are improved, and the common drain geminate transistor is suitable for common drain geminate transistor application in a battery management system.

Techniques for temperature sensing in power FET switches are described. An example power field effect transistor (FET) device includes back-to-back power FETs coupled in series between a first power terminal and a second power terminal and connected to a common drain node. The power FET device also includes a temperature sense diode comprising a cathode coupled to the common drain node. A temperature sense circuit coupled to the power FET device is configured to determine a temperature of the first power FET and the second power FET based on a voltage drop across the temperature sense diode. The temperature sense circuit can include a voltage averaging circuit configured to sense a first voltage at the first power terminal, sense a second voltage at the second power terminal, and average the first voltage and the second voltage to generate a drain voltage representative of a voltage of the common drain node.

A power semiconductor module may comprise a common drain pad, a first power semiconductor device on a first region of the common drain pad, a second power semiconductor device on a second region of the common drain pad, a molding layer surrounding lateral parts of the first power semiconductor device and the second power semiconductor device on a peripheral region of the common drain pad, a common gate pad on the first power semiconductor device and the second power semiconductor device, and a source pad on the first power semiconductor device and the second power semiconductor device. The source pad may surround at least two outer lateral parts of the common gate pad.

The utility model discloses a bidirectional switch semiconductor packaging device, an AC / DC converter and an automobile, and relates to the technical field of power supplies, the device comprises a first switch chip, a second switch chip, a plastic package shell and a heat dissipation substrate; the drain electrode or the source electrode of the first switch chip is electrically connected with the drain electrode or the source electrode corresponding to the second switch chip through the same heat dissipation substrate, so that a bidirectional switch structure with the common drain electrode or the common source electrode is formed, and heat dissipation can be carried out on the two switch chips at the same time by utilizing a single heat dissipation substrate. Meanwhile, on the surface of the plastic package shell, a creepage path extension part used for increasing the creepage distance is arranged between the heat dissipation substrate and any group of pins located on the two sides of the plastic package shell. Through the structure, the packaging size of the bidirectional switch semiconductor packaging device can be kept as small as possible, and meanwhile, the problems of power output control, heat dissipation, electrical safety and the like caused by the too small packaging size can be prevented.

The application relates to a bidirectional power device module integrated with a driving circuit and an active substrate clamping circuit, which comprises a common-drain bidirectional power device, a driving circuit used for providing a driving signal to the common-drain bidirectional power device to turn on and turn off the device, and a substrate clamping circuit comprising a first switch tube and a second switch tube, wherein the first switch tube and the second switch tube are commonly connected to the substrate of the common-drain bidirectional power device, the drain of the first switch tube is connected to the first source of the common-drain bidirectional power device, and the gate is connected to the output end of a third driving unit; the drain of the second switch tube is connected to the second source of the common-drain bidirectional power device, and the gate is connected to the output end of a fourth driving unit; the input end of the third driving unit inputs a first PWM input signal which is subjected to logic processing; and the input end of the fourth driving unit inputs a second PWM input signal which is subjected to logic processing. The application can improve the substrate clamping speed and reduce the substrate potential.

This invention relates to a silicon carbide bidirectional switching half-bridge power module, belonging to the field of semiconductor device technology. The bidirectional switching half-bridge power module includes a module housing, a DBC (Diverterless Circuit Blocker), silicon carbide bidirectional switching units soldered onto the DBC, power terminals, signal terminals, and a thermistor. The silicon carbide bidirectional switching power module adopts a half-bridge structure, which consists of two bidirectional switching units. Each bidirectional switching unit is composed of two sets of silicon carbide MOSFETs connected with a common drain. The bidirectional switching half-bridge circuit is integrated on a single DBC, and the conductive areas of the silicon carbide chip and the DBC are connected by bonding wires to form the bidirectional switching units and the half-bridge structure, with corresponding power terminals and signal terminals led out. This invention achieves bidirectional conduction and bidirectional blocking of current, and is packaged as a bidirectional switching half-bridge structure, improving reliability, reducing parasitic inductance, increasing power density, and lowering the parasitic inductance of the power module.

This semiconductor device (1) comprises: a semiconductor layer (40) which has a semiconductor substrate (32) that has a first conductivity type and contains an impurity of a first concentration, and a low-concentration impurity layer (33) that is formed to be in contact with the upper surface of the semiconductor substrate (32), has the first conductivity type, and contains an impurity of a second concentration that is lower than the first concentration; a first vertical MOS transistor (10) and a second vertical MOS transistor (20) which use the semiconductor substrate (32) as a common drain region; and a first Schottky barrier diode (81) which uses the low-concentration impurity layer (33) as a cathode in a case where the first conductivity type is N-type, and uses the low-concentration impurity layer (33) as an anode in a case where the first conductivity type is P-type, the first Schottky barrier diode (81) being connected in parallel in the same forward direction with a body diode of the first vertical MOS transistor (10).

The testing system can have a controller, and a plurality of channels which may have source measure units, each channel individually connectable to one or more electrical connection of a device under test (DUT). A source measure unit can have voltage sources connected to the controller; a pulse generator having an input port connected to the voltage sources, a control port connected to the controller, and an output port; an analog-to-digital converter (ADC); and a current-to-voltage (I / V) converter having a first output port connected to the ADC, an input port connected to the output port of the pulse generator, and a third port connectable to the DUT. The testing system or the source measure unit can further have current limitation units connected in series between the source measure units and / or a fixed voltage reference and the DUT, each current limitation unit having a first transistor and a second transistor configured in a common source or common drain configuration and each having a corresponding gate, the gates having an electrical potential controllable to an intermediary value by the controller.

The disclosure concerns an electronic device comprising a HEMT transistor, called main transistor, and at least another HEMT transistor, called additional transistor, stacked on each other. The main transistor and the additional transistor comprise a common drain electrode and, respectively, a main source electrode and an additional source electrode, arranged so that electric conduction paths likely to be formed by the two conduction layers are connected in parallel when one and the other of the HEMT transistors are in the conductive state.

Embodiments include a FinFET transistor including an embedded resistor disposed in the fin between the source epitaxial region and the source contact. A control contact may be used to bias the embedded resistor, thereby changing the resistivity of the resistor. Edge gates of the FinFET transistor may be replaced with insulating structures. Multiple ones of the FinFET / embedded resistor combination may be utilized together in a common drain / common source contact design.

The invention discloses alternating current conversion equipment, and belongs to the technical field of power conversion. In the alternating-current conversion equipment, an alternating-current conversion circuit is connected with an alternating-current source and a primary winding of a transformer, the alternating-current conversion circuit comprises at least one bridge arm, the two ends of the bridge arm are connected with the alternating-current source through bridge arm buses, the bridge arm comprises an upper bridge arm and a lower bridge arm which are connected in series, and each of the upper bridge arm and the lower bridge arm comprises two switching tubes. The two switch tubes of one of the upper bridge arm and the lower bridge arm are connected in series through common source electrodes, and the two switch tubes of the other one of the upper bridge arm and the lower bridge arm are connected in series through common drain electrodes; under the condition that the bridge arm is in the dead zone time period, the follow current module is provided with a follow current path, the alternating current conversion device is provided with a closed follow current loop, and the closed follow current loop comprises the follow current path, part of the switching tubes and the primary winding. According to the invention, a closed follow current loop is provided in a dead zone period, continuous current circulation is realized without interruption, tube pressure stress overshoot of a switching device is reduced, and the risk of damage to the switching device is reduced.

This invention belongs to the field of battery thermal runaway monitoring technology, specifically relating to a thermal runaway protection device and method for lithium battery packs in electric two-wheeled vehicles. The device includes a first protection circuit and a second protection circuit connected in series between the negative terminal and the interface of the battery pack, and a BMS main control chip connected to both. The first protection circuit includes a discharge MOSFET and a charging MOSFET connected in common drain configuration, used to cut off the charging and discharging circuit according to a first control signal. The second protection circuit includes an active isolation element connected in series between the negative terminal of the battery pack and the first protection circuit, and its trigger circuit. After the main control chip detects that the voltage or temperature exceeds a first threshold and outputs a first control signal, if it detects that the voltage or temperature reaches a second threshold, it outputs a second control signal to the trigger circuit, driving the active isolation element to a permanently disconnected state, achieving permanent physical isolation of the battery circuit.

A power semiconductor module may comprise a common drain pad, a first power semiconductor device on a first region of the common drain pad, a second power semiconductor device on a second region of the common drain pad, a molding layer surrounding lateral parts of the first power semiconductor device and the second power semiconductor device on a peripheral region of the common drain pad, a common gate pad on the first power semiconductor device and the second power semiconductor device, and a source pad on the first power semiconductor device and the second power semiconductor device. The source pad may surround at least two outer lateral parts of the common gate pad.

Techniques for load current sensing in common-drain power FET switches are described. In an example embodiment, a power field effect transistor (FET) device includes back-to-back power FETs connected to a common drain node. The power FET device also includes a first replica FET coupled to the common drain node and configured to provide a sense current representative of a load current flowing through the power FET device. The power FET device also includes a second replica FET coupled to the common drain node and configured to provide a sense voltage representative of a voltage of the common drain node. A current sense circuit coupled to the first replica FET and the second replica FET may be configured to use the sense voltage from the second replica FET to draw the sense current through the first replica FET.

Aspects of the present disclosure improve operating efficiency of a Terahertz RADAR device, facilitating implementation of Terahertz RADAR on a low power budget. Some aspects of the present disclosure relate to regulating a bias state of a harmonic generation circuit in a receiver and / or transmitter of a Terahertz RADAR device. Some aspects of the present disclosure relate to coupling frequency multipliers between RF amplifiers and RF antennas in a transmitter of a Terahertz RADAR device. Some aspects of the present disclosure relate to frequency multipliers, e.g., in a transmitter of a Terahertz RADAR device, using certain transistor configurations (e.g., common-collector or common-drain). A THz RADAR device May implement one, two, or all three of these aspects.

Aspects of the present disclosure improve operating efficiency of a Terahertz RADAR device, facilitating implementation of Terahertz RADAR on a low power budget. Some aspects of the present disclosure relate to regulating a bias state of a harmonic generation circuit in a receiver and / or transmitter of a Terahertz RADAR device. Some aspects of the present disclosure relate to coupling frequency multipliers between RF amplifiers and RF antennas in a transmitter of a Terahertz RADAR device. Some aspects of the present disclosure relate to frequency multipliers, e.g., in a transmitter of a Terahertz RADAR device, using certain transistor configurations (e.g., common-collector or common-drain). A THz RADAR device May implement one, two, or all three of these aspects.

A memory cell includes an active region extending lengthwise along a first direction and first and second gate structures extending lengthwise along a second direction different from the first direction. The first gate structure engages the active region in forming a first transistor, and the second gate structure engages the active region in forming a second transistor. The memory cell further includes a first epitaxial feature disposed on a source region of the first transistor, a second epitaxial feature disposed on a common drain region of the first and second transistors, a backside contact disposed under and in electrical coupling with the first epitaxial feature, a backside signal line disposed under and in electrical coupling with the backside contact, and a first frontside contact disposed above and in electrical coupling with the second epitaxial feature.

The utility model discloses an ultra-wideband high-linearity low-noise amplifier circuit based on a common source structure, which comprises a first amplifying circuit, an inter-stage matching circuit and a second amplifying circuit which are sequentially cascaded, the drain electrode of the first transistor of the first amplification circuit and the drain electrode of the second transistor of the second amplification circuit are provided with a common drain electrode power supply matching network. The drain electrode power supply mode of the two-stage amplification circuit is optimized and adjusted, so that the drain electrode power supply of the first amplification circuit and the drain electrode power supply of the second amplification circuit jointly pass through the common drain electrode power supply matching network, and the power supply firstly passes through the common drain electrode power supply matching network and then independently supplies power to the first amplification circuit and the second amplification circuit. In addition, in order to expand the bandwidth, LC parallel connection is added to the input matching network of the first amplification circuit and the output matching network of the second amplification circuit, and the bandwidth is expanded by introducing the LC parallel connection to the ground.

A power FET device and a device including the same are disclosed. Techniques for temperature sensing in power FET switches are described. An example power field effect transistor (FET) device includes back-to-back power FETs coupled in series between a first power terminal and a second power terminal and connected to a common drain node. The power FET device also includes a temperature sensing diode including a cathode coupled to the common drain node. A temperature sensing circuit coupled to the power FET device is configured to determine a temperature of the first power FET and the second power FET based on a voltage drop across the temperature sensing diode. The temperature sensing circuit may include a voltage averaging circuit configured to sense a first voltage at the first power terminal, sense a second voltage at the second power terminal, and average the first voltage and the second voltage to generate a drain voltage representative of a voltage of the common drain node.

The application discloses a MOSFET wafer adjacent particle testing method and a testing circuit thereof, and the testing method comprises the following steps: S101, connecting the drain loading end and the drain measuring end of the MOSFET wafer through a resistor; S102, judging the basic function of N measured MOSFET particles to be normal by testing a small current parameter of VTH; S103, testing Rdson, and selecting a particle closest to the measured particle as an auxiliary particle; S104, driving the gate of the auxiliary particle to be always on; and S105, connecting the measuring end of the common drain to the source of the auxiliary particle, and then testing the Rdson parameter; the application further discloses a MOSFET wafer adjacent particle testing circuit, and the testing circuit can improve the measurement accuracy of the Rdson parameter of the MOSFET wafer and effectively reduces the testing error.

A power semiconductor module may include: a common drain pad; a first power semiconductor device on the first region of the common drain pad; a second power semiconductor device on a second region of the common drain pad; a molding layer surrounding lateral portions of the first power semiconductor device and the second power semiconductor device on a peripheral region of the common drain pad; a common gate pad on the first power semiconductor device and the second power semiconductor device; and a source pad on the first power semiconductor device and the second power semiconductor device. The source pad may surround at least two outer lateral portions of the common gate pad.

The application provides a preparation process of a common-drain double MOSFET device and the common-drain double MOSFET device. The symmetric structure is formed on the front surface and the back surface of a wafer, the problems existing in the prior art are solved, and the common-drain double MOSFET wafer with excellent performance, smaller area and stronger packaging performance is produced.

The application discloses an SRAM memory unit of an anti-soft-error SRAM, which has a double interlocking structure and comprises: first and second NMOS tubes which are connected in common source and provide interlocked first and second storage nodes, first and second PMOS tubes which are connected in common source and provide interlocked third and fourth storage nodes, a gate and a source of a fifth MOS transistor which are connected in common drain and are connected between the first and third storage nodes in phase, a gate and a source of a sixth MOS transistor which are connected in common drain and are connected between the second and fourth storage nodes in phase, a gate of a third MOS transistor which is connected to the second storage node, and a source and a drain which are connected between the first and third storage nodes. A gate of a fourth MOS transistor is connected to the first storage node, and a source and a drain are connected between the second and fourth storage nodes. The application can resist multi-node flipping and can improve RSNM and WNM.

This invention provides a bidirectional switching device, a substrate potential control method, a chip, and an electronic device, comprising: a bidirectional common-drain switching main tube formed on a substrate, having a first source, a second source, a first gate, and a second gate; a first diode, with its anode connected to the substrate and its cathode connected to the first source; a second diode, with its anode connected to the substrate and its cathode connected to the second source; a third diode, with its anode connected to the substrate and its cathode connected to the first gate; and a fourth diode, with its anode connected to the substrate and its cathode connected to the second gate. The bidirectional switching device, substrate potential control method, chip, and electronic device of this invention can overcome the influence of positive and negative dv / dt on the substrate potential; the substrate potential of the bidirectional switching device can be clamped near the lowest potential of the device, thereby ensuring stable operation; and it has good symmetry, a simple structure, and low cost.

The present application provides a nonvolatile memory, a memory system, and a data erasing method of the memory, the method comprising: applying a first conduction voltage to a memory cell included in a first stack of a plurality of stacks to be erased; after applying the first conduction voltage, applying a source erasing voltage and a drain erasing voltage to a common source and a common drain, respectively; and applying a first voltage to a dummy memory cell included in a second stack of the plurality of stacks to be erased during a level ramp-up of the source erasing voltage and the drain erasing voltage to a peak level thereof.

An amplifier circuit includes an amplifier including a common drain or a common collector having variable transconductance, a power distributor connected to an output side of the amplifier, and a switch arranged in series on a bypass path, which branches from a path with which the amplifier is connected to the power distributor, bypasses the power distributor, and is joined to an output of the power distributor. Input impedance (Zin) of the power distributor has a value different from that of output impedance (Zout1) of the power distributor.

A circuit includes a first driver, a second driver, and a bias generator. First driver has a first bias terminal, a first reference terminal, a first driver input, and a first driver output. The second driver has a second bias terminal, a second reference terminal, a second driver input, and a second driver output. The bias generator has a first input, a second input, a first bias output, and a second bias output, the first input coupled to the first reference terminal, the second input coupled to the second reference terminal, the first bias output coupled to the first bias terminal, and the second bias output coupled to the second bias terminal, wherein the bias generator is configurable to generate, based on a supply voltage, a first bias voltage at the first bias output and a second bias voltage at the second bias output.

The invention provides a packaging structure of a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) semiconductor, which is characterized in that a first MOS (Metal Oxide Semiconductor) tube group and a second MOS tube group comprising a plurality of MOS field effect transistors are arranged on the same semiconductor substrate; first common grids, first common sources, first common drains and first common shield grids of the plurality of first MOS tube groups and second common grids, second common sources, second common drains and second common shield grids of the plurality of second MOS tube groups are led to the outside through a molding compound; by configuring different first voltage signals on a first gate pin and second voltage signals on a second gate pin and configuring a flexible pin connection scheme, a power MOSFET semiconductor realizes switching among four different working states, so that collaborative optimization among SOA performance, reverse recovery performance and conduction performance is realized; and the reliability of the device in high-speed switch application is obviously improved.

Reconfigurable memory cell (400, 410) with internal logic, comprising a plurality of triple-gate feedback memory elements (401, 411) comprising a drain region, a channel region, a source region and a gate region, wherein a first and a second programming gate electrode and a control gate electrode are formed on the channel region, wherein in each of the triple-gate feedback storage elements (401, 411) the channel area under the first and second programming gate electrodes provides a channel operation consisting of a first and a second channel operation depending on a level of a programming voltage (V) applied by the first and second programming gate electrodes PG ) performs, wherein an arbitrary on-state and off-state is determined based on a level of a control voltage (V) applied by the control gate electrode. CG) is specified, and wherein a logic operation function and a memory function are based on a level of an output voltage (V) OUT ) are carried out, which changes depending on the one state in the one channel operation being carried out, and wherein the reconfigurable memory cell (400, 410) with internal logic consists of a circuit structure of a first circuit structure which consists of a plurality of first parallel connections, wherein drain regions of two triple-gate feedback memory elements (401, 411) of the triple-gate feedback memory elements (401, 411) are connected to each other and source regions of the same are connected to each other;or a second circuit structure consisting of a plurality of second parallel connections, wherein a common drain region and a common source region are connected between a first series connection, wherein a drain region and a source region of two triple-gate feedback memory elements (401, 411) of four triple-gate feedback memory elements (401, 411) are connected in series, and a second series connection, wherein a drain region and a source region of the remaining two triple-gate feedback memory elements (401, 411) are connected in series, ; the first circuit structure consists of four first parallel connections, the first parallel connection consists of two triple-gate feedback storage elements, wherein the second circuit structure consists of two second parallel connections, the second parallel connection consists of four triple-gate feedback storage elements.

The application belongs to the technical field of power semiconductors, and relates to a monolithic integrated bidirectional GaN HEMT device with adaptive substrate potential regulation. The device is connected to its own substrate by connecting a GaN HEMT in series with the source electrode of the common-drain bidirectional switch, and the conduction and turn-off of the series GaN HEMT are realized by means of the gate signal of the common-drain bidirectional switch during work, so that the substrate of the common-drain bidirectional switch can be adaptively connected to the source electrode on the side with lower potential of the device during work, and problems such as performance crosstalk, threshold voltage drift and sharp increase of dynamic on-resistance caused by floating of the substrate potential are avoided, meanwhile, no additional mask plate and process step are needed in the device manufacturing process, so that the structure is compatible with the conventional process, and is conducive to the integration of the device.