The utility model relates to a monolithic fabrication technology for the enhanced and depletion VDMOS, belonging to a technology applying for fabricating a enhanced and a depletion VDMOS with a high voltage (650V) common drain in one IC, which is characterized in that the material of the VDMOS adopting a N(100) substrate doped arsenic, which has a resistivity below 0.005 Omega-CM, the thickness of the epitaxy is 55Mum, the resistivity of the epitaxy is 24 Omega-CM. The withstand voltage can be stable on 650V, and up to 700V. To add a depletion VDMOS on the surface of the enhanced VDMOS, the depletion area needs a individual switching voltage adjustment, which is adding once more VT impurity, while adjusting the pre-and post process. The utility model has the advantages of fewer photoetching, low cost and simple fabricating control.