232 results about "Common drain" patented technology

A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.

A CMOS EPROM, EEPROM or inverter device includes an nFET device with a thin gate dielectric layer and a pFET device juxtaposed with the nFET device with a thick gate dielectric layer and a floating gate electrode. The thick gate dielectric layer is substantially thicker than the thin gate dielectric layer. A common drain node connected both FET devices has no external connection in the case of a memory device and has an external connection in the case of an inverter. There are external circuit connections to the source regions of both FET devices and to the gate electrode of the nFET device. The pFET and nFET devices can be planar, vertical or FinFET devices.

Provided is a duty cycle correction circuit for correcting a duty cycle of an imparted clock to obtain a clock whose duty cycle is 50%. A duty cycle correction circuit is provided with: a delay part 11A for delaying a clock CK1 to output a clock CK2; and a clock output part 17 composed of transistors 12, 13 with the clocks CK1, CK2 as respective gate inputs, and an inverter circuit 16 for inverting a signal CK3' which is a common drain output of the transistors to output a clock CK3. The delay part 11A delays the clock CK1 so that the falling change of the clock CK1 may appear at a timing of duty cycle 50%. The transistors 12, 13 output a ground voltage and a power supply voltage from their common drain in accordance with the rising change of the clock CK1 and the falling change of the clock CK2 (signal CK3'). The clock CK3 whose duty cycle is finally corrected to about 50% is then obtained.

The present invention relates to a battery protection circuit for protecting a plurality of batteries connected in series. The battery protection circuit includes: a controller for monitoring the batteries and outputting control signals based on predetermined conditions associated with the batteries; a first N-channel MOSFET and a second N-channel MOSFET coupled in a common-drain configuration in a low-side path, wherein at least one of the first and second N-channel MOSFETs turns off in response to the control signal received from the controller when at least one of the predetermined conditions is detected; and a gate protection circuit for preventing gate-to-source voltages of the first and second N-channel MOSFETs from exceeding a predetermined gate-to-source voltage level.

A stacked-die package for battery protection is disclosed. The battery protection package includes a power control integrated circuit (IC) stacked on top of integrated dual common-drain metal oxide semiconductor field effect transistors (MOSFETs) or two discrete MOSFETs. The power control IC is either stacked on top of one MOSFET or on top of and overlapping both two MOSFETs.

A power module with multiple equalized parallel power paths supporting multiple parallel bare die power devices constructed with low inductance equalized current paths for even current sharing and clean switching events. Wide low profile power contacts provide low inductance, short current paths, and large conductor cross section area provides for massive current carrying. An internal gate & source kelvin interconnection substrate is provided with individual ballast resistors and simple bolted construction. Gate drive connectors are provided on either left or right size of the module. The module is configurable as half bridge, full bridge, common source, and common drain topologies.

A below grade trench drain system and a method for making the trench drain system is disclosed which does not rely on the contractor's prowess to dig a trench with a proper slope. The trench drain system, in accordance with the present invention, includes a plurality of modular trench sections formed with a uniform exterior height and an interior fluid channel formed with a pre-sloped floor. As such, the trench drain system, in accordance with the present invention, can be installed in a level trench, which greatly simplifies installation by the contractor and ensures that the trench drain will be installed with the proper slope. The modular trench sections can be coupled together forming a trench drain with a continuous slope or alternatively coupled with modular trench sections with no slope to form a stepped slope. The configuration of the modular trench sections allows the modular trench sections to form a trench drain system sloped in different directions to enable connections to the common drain in the center as well at both ends. As such, the trench drain system provides more configurations for connections to the common drain system thus improving the flexibility of the system and at the same time provide a trench drain system which does not depend on the installation prowess of the installation contractor.

A composite semiconductor package is disclosed. The package includes a lead frame having first and second die bonding pads, the first and second die bonding pads having a large lateral separation therebetween, a first device bonded to the first die bonding pad, a second device bonded to the second die bonding pad, a plurality of first leads coupled to the first die bonding pad, a plurality of second leads coupled to the second die bonding pad, and an encapsulant covering the lead frame, the first and second devices and at least a portion of the first and second pluralities of leads. The package may be a TSSOP-8 composite package having a common drain MOSFET pair and an IC.