79 results about "Common drain" patented technology

The invention discloses a double-sided heat dissipation common drain module packaging structure, and belongs to the technical field of power semiconductor device packaging. The module comprises a common drain electrode upper copper layer, two drain electrode copper terminals, two power chips, two source electrode copper blocks, two L-shaped source electrode lower copper layers, two driving grid electrode copper terminals, two driving source electrode copper terminals and a bonding wire. Drain electrodes of the two power chips are welded on the common drain electrode upper copper layer, and source electrodes of the two power chips are respectively welded with the L-shaped source electrode lower copper layer through source electrode copper blocks. And the bonding wire is connected with the grid electrode and the source electrode of the chip and the driving copper terminal to realize Kelvin connection. Thermal resistance is reduced through a double-sided heat dissipation structure, parasitic inductance is reduced through a three-dimensional commutation loop, power density and reliability are improved, and the common drain geminate transistor is suitable for common drain geminate transistor application in a battery management system.

The invention relates to a circuit and a method for generating a bias voltage in a substrate clamp circuit. An electronic device includes: a gallium nitride (GaN) substrate having a GaN-based top layer attached to a silicon-based bottom layer; a bidirectional switch formed on the GaN-based top layer and including a first source node, a second source node, and a common drain node; a first bias generator circuit arranged to couple the first source node to the silicon substrate layer; and a second bias generator circuit arranged to couple the second source node to the silicon substrate layer. In one aspect, when a voltage of the first source node is higher than a voltage of the second source node, the first bias generator circuit approaches a voltage at the silicon substrate layer to the voltage at the second source node.

An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.

A power semiconductor device is provided that includes paralleled transistor cells, and a common source, a common drain and a common gate operatively coupled to the paralleled transistor cells. The power semiconductor device also includes a plurality of common gate contact pads operatively coupled to the common gate, and one or more resistors coupled to respective one or more common gate contact pads of the plurality of common gate contact pads. The one or more resistors are also coupled between the respective one or more common gate contact pads and the common gate. The plurality of common gate contact pads provide a selectable resistive decoupling of the common gate by connection of one of the plurality of common gate contact pads.

Techniques for temperature sensing in power FET switches are described. An example power field effect transistor (FET) device includes back-to-back power FETs coupled in series between a first power terminal and a second power terminal and connected to a common drain node. The power FET device also includes a temperature sense diode comprising a cathode coupled to the common drain node. A temperature sense circuit coupled to the power FET device is configured to determine a temperature of the first power FET and the second power FET based on a voltage drop across the temperature sense diode. The temperature sense circuit can include a voltage averaging circuit configured to sense a first voltage at the first power terminal, sense a second voltage at the second power terminal, and average the first voltage and the second voltage to generate a drain voltage representative of a voltage of the common drain node.

A power semiconductor module may comprise a common drain pad, a first power semiconductor device on a first region of the common drain pad, a second power semiconductor device on a second region of the common drain pad, a molding layer surrounding lateral parts of the first power semiconductor device and the second power semiconductor device on a peripheral region of the common drain pad, a common gate pad on the first power semiconductor device and the second power semiconductor device, and a source pad on the first power semiconductor device and the second power semiconductor device. The source pad may surround at least two outer lateral parts of the common gate pad.

The utility model discloses a bidirectional switch semiconductor packaging device, an AC / DC converter and an automobile, and relates to the technical field of power supplies, the device comprises a first switch chip, a second switch chip, a plastic package shell and a heat dissipation substrate; the drain electrode or the source electrode of the first switch chip is electrically connected with the drain electrode or the source electrode corresponding to the second switch chip through the same heat dissipation substrate, so that a bidirectional switch structure with the common drain electrode or the common source electrode is formed, and heat dissipation can be carried out on the two switch chips at the same time by utilizing a single heat dissipation substrate. Meanwhile, on the surface of the plastic package shell, a creepage path extension part used for increasing the creepage distance is arranged between the heat dissipation substrate and any group of pins located on the two sides of the plastic package shell. Through the structure, the packaging size of the bidirectional switch semiconductor packaging device can be kept as small as possible, and meanwhile, the problems of power output control, heat dissipation, electrical safety and the like caused by the too small packaging size can be prevented.

The application relates to a bidirectional power device module integrated with a driving circuit and an active substrate clamping circuit, which comprises a common-drain bidirectional power device, a driving circuit used for providing a driving signal to the common-drain bidirectional power device to turn on and turn off the device, and a substrate clamping circuit comprising a first switch tube and a second switch tube, wherein the first switch tube and the second switch tube are commonly connected to the substrate of the common-drain bidirectional power device, the drain of the first switch tube is connected to the first source of the common-drain bidirectional power device, and the gate is connected to the output end of a third driving unit; the drain of the second switch tube is connected to the second source of the common-drain bidirectional power device, and the gate is connected to the output end of a fourth driving unit; the input end of the third driving unit inputs a first PWM input signal which is subjected to logic processing; and the input end of the fourth driving unit inputs a second PWM input signal which is subjected to logic processing. The application can improve the substrate clamping speed and reduce the substrate potential.

This invention relates to a silicon carbide bidirectional switching half-bridge power module, belonging to the field of semiconductor device technology. The bidirectional switching half-bridge power module includes a module housing, a DBC (Diverterless Circuit Blocker), silicon carbide bidirectional switching units soldered onto the DBC, power terminals, signal terminals, and a thermistor. The silicon carbide bidirectional switching power module adopts a half-bridge structure, which consists of two bidirectional switching units. Each bidirectional switching unit is composed of two sets of silicon carbide MOSFETs connected with a common drain. The bidirectional switching half-bridge circuit is integrated on a single DBC, and the conductive areas of the silicon carbide chip and the DBC are connected by bonding wires to form the bidirectional switching units and the half-bridge structure, with corresponding power terminals and signal terminals led out. This invention achieves bidirectional conduction and bidirectional blocking of current, and is packaged as a bidirectional switching half-bridge structure, improving reliability, reducing parasitic inductance, increasing power density, and lowering the parasitic inductance of the power module.

The present invention discloses a high-voltage DC circuit topology. In the high-voltage DC circuit topology, the positive pole of the DC power supply DC is connected to the positive terminal of the bus capacitor C0 via the diode D1, and the negative pole is connected to the negative terminal of the bus capacitor C0; the positive terminal of the bus capacitor C0 is connected to the common drain of the fault current limiting unit and the full-bridge circuit, and the negative terminal is connected to the common source of the full-bridge circuit to form a radio frequency oscillator. The primary winding of the radio frequency transformer T1 is connected in parallel with the tuning capacitor C2. The radio frequency feed electrode a is connected to the a end of the first secondary winding of the radio frequency transformer, and the radio frequency feed electrode b is connected to the b end of the second secondary winding of the radio frequency transformer. A voltage multiplier is placed between the radio frequency feed electrode a and the radio frequency feed electrode b to achieve voltage superposition. The voltage multiplier is composed of a cascade of multiple radio frequency energy coupling electrodes and radio frequency rectifiers. One end of the parallel resonance filter is connected to the last-stage radio frequency energy coupling electrode of the voltage multiplier, and the other end is connected to the load to achieve a DC voltage with low ripple on the load.

The present invention discloses a multimodal nitride semiconductor CMOS array and a method for fabricating the same. The array comprises a plurality of longitudinally distributed first nanopillar structures; an insulating dielectric is filled between adjacent first nanopillar structures; each first nanopillar structure comprises: a first N-type epitaxial structure comprising a first barrier layer; a first P-type epitaxial structure comprising a second channel layer located above the first N-type epitaxial structure; a first source electrode annularly surrounding the first barrier layer; and a second source electrode annularly surrounding the second channel layer; a first gate electrode and a second gate electrode located on the surfaces of the first barrier layer and the second barrier layer, respectively, with the first and second gate electrodes sharing a common gate via metal interconnection; and a first drain electrode and a second drain electrode located on the surfaces of the first barrier layer and the second barrier layer, respectively, with an insulating dielectric filled between the first drain electrode and the first gate electrode, and between the second drain electrode and the second gate electrode, with the first and second drain electrodes sharing a common drain via metal interconnection. This invention improves the integration level of nitride semiconductor CMOS arrays.

This semiconductor device (1) comprises: a semiconductor layer (40) which has a semiconductor substrate (32) that has a first conductivity type and contains an impurity of a first concentration, and a low-concentration impurity layer (33) that is formed to be in contact with the upper surface of the semiconductor substrate (32), has the first conductivity type, and contains an impurity of a second concentration that is lower than the first concentration; a first vertical MOS transistor (10) and a second vertical MOS transistor (20) which use the semiconductor substrate (32) as a common drain region; and a first Schottky barrier diode (81) which uses the low-concentration impurity layer (33) as a cathode in a case where the first conductivity type is N-type, and uses the low-concentration impurity layer (33) as an anode in a case where the first conductivity type is P-type, the first Schottky barrier diode (81) being connected in parallel in the same forward direction with a body diode of the first vertical MOS transistor (10).

The testing system can have a controller, and a plurality of channels which may have source measure units, each channel individually connectable to one or more electrical connection of a device under test (DUT). A source measure unit can have voltage sources connected to the controller; a pulse generator having an input port connected to the voltage sources, a control port connected to the controller, and an output port; an analog-to-digital converter (ADC); and a current-to-voltage (I / V) converter having a first output port connected to the ADC, an input port connected to the output port of the pulse generator, and a third port connectable to the DUT. The testing system or the source measure unit can further have current limitation units connected in series between the source measure units and / or a fixed voltage reference and the DUT, each current limitation unit having a first transistor and a second transistor configured in a common source or common drain configuration and each having a corresponding gate, the gates having an electrical potential controllable to an intermediary value by the controller.

The disclosure concerns an electronic device comprising a HEMT transistor, called main transistor, and at least another HEMT transistor, called additional transistor, stacked on each other. The main transistor and the additional transistor comprise a common drain electrode and, respectively, a main source electrode and an additional source electrode, arranged so that electric conduction paths likely to be formed by the two conduction layers are connected in parallel when one and the other of the HEMT transistors are in the conductive state.

Embodiments include a FinFET transistor including an embedded resistor disposed in the fin between the source epitaxial region and the source contact. A control contact may be used to bias the embedded resistor, thereby changing the resistivity of the resistor. Edge gates of the FinFET transistor may be replaced with insulating structures. Multiple ones of the FinFET / embedded resistor combination may be utilized together in a common drain / common source contact design.

The invention discloses alternating current conversion equipment, and belongs to the technical field of power conversion. In the alternating-current conversion equipment, an alternating-current conversion circuit is connected with an alternating-current source and a primary winding of a transformer, the alternating-current conversion circuit comprises at least one bridge arm, the two ends of the bridge arm are connected with the alternating-current source through bridge arm buses, the bridge arm comprises an upper bridge arm and a lower bridge arm which are connected in series, and each of the upper bridge arm and the lower bridge arm comprises two switching tubes. The two switch tubes of one of the upper bridge arm and the lower bridge arm are connected in series through common source electrodes, and the two switch tubes of the other one of the upper bridge arm and the lower bridge arm are connected in series through common drain electrodes; under the condition that the bridge arm is in the dead zone time period, the follow current module is provided with a follow current path, the alternating current conversion device is provided with a closed follow current loop, and the closed follow current loop comprises the follow current path, part of the switching tubes and the primary winding. According to the invention, a closed follow current loop is provided in a dead zone period, continuous current circulation is realized without interruption, tube pressure stress overshoot of a switching device is reduced, and the risk of damage to the switching device is reduced.

This invention belongs to the field of battery thermal runaway monitoring technology, specifically relating to a thermal runaway protection device and method for lithium battery packs in electric two-wheeled vehicles. The device includes a first protection circuit and a second protection circuit connected in series between the negative terminal and the interface of the battery pack, and a BMS main control chip connected to both. The first protection circuit includes a discharge MOSFET and a charging MOSFET connected in common drain configuration, used to cut off the charging and discharging circuit according to a first control signal. The second protection circuit includes an active isolation element connected in series between the negative terminal of the battery pack and the first protection circuit, and its trigger circuit. After the main control chip detects that the voltage or temperature exceeds a first threshold and outputs a first control signal, if it detects that the voltage or temperature reaches a second threshold, it outputs a second control signal to the trigger circuit, driving the active isolation element to a permanently disconnected state, achieving permanent physical isolation of the battery circuit.

An electronic device includes a gallium nitride (GaN) substrate having a GaN-based top layer attached to a silicon-based bottom layer, a bidirectional switch formed on the GaN-based top layer and including a first source node, a second source node and a common drain node, a first bias generator circuit arranged to couple the first source node to the silicon-based bottom layer, and a second bias generator circuit arranged to couple the second source node to the silicon-based bottom layer. In one aspect, when a voltage of the first source node is at a higher voltage than the second source node, the first bias generator circuit brings a voltage at the silicon-based bottom layer close to the voltage at the second source node.

A power semiconductor module may comprise a common drain pad, a first power semiconductor device on a first region of the common drain pad, a second power semiconductor device on a second region of the common drain pad, a molding layer surrounding lateral parts of the first power semiconductor device and the second power semiconductor device on a peripheral region of the common drain pad, a common gate pad on the first power semiconductor device and the second power semiconductor device, and a source pad on the first power semiconductor device and the second power semiconductor device. The source pad may surround at least two outer lateral parts of the common gate pad.

The invention discloses a reinforcing structure for resisting a single event effect of a gallium oxide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) high-voltage device, relates to the technical field of semiconductor devices, and aims at solving the problems that in the prior art, only single-tube structure improvement is carried out on a gallium oxide MOSFET during single event effect resistance, so that additional complex process steps need to be introduced in the single-tube forming process, and the process manufacturing difficulty is increased. The provided reinforcing structure comprises a gallium oxide MOSFET array, a common grid electrode, a common source electrode and a common drain electrode, the gallium oxide MOSFET array comprises a plurality of gallium oxide MOSFETs; the plurality of gallium oxide MOSFETs form a plurality of MOSFET branches which are mutually connected in parallel; each MOSFET branch comprises N gallium oxide MOSFETs which are sequentially connected in series; all the gallium oxide MOSFETs are connected with the common grid electrode; the first end of each MOSFET branch is connected with the common source electrode; and the second end of each MOSFET branch is connected with the common drain electrode. The method is used for improving the single event effect resisting performance of the gallium oxide MOSFET high-voltage device on the premise of not excessively increasing process steps.

Techniques for load current sensing in common-drain power FET switches are described. In an example embodiment, a power field effect transistor (FET) device includes back-to-back power FETs connected to a common drain node. The power FET device also includes a first replica FET coupled to the common drain node and configured to provide a sense current representative of a load current flowing through the power FET device. The power FET device also includes a second replica FET coupled to the common drain node and configured to provide a sense voltage representative of a voltage of the common drain node. A current sense circuit coupled to the first replica FET and the second replica FET may be configured to use the sense voltage from the second replica FET to draw the sense current through the first replica FET.

Aspects of the present disclosure improve operating efficiency of a Terahertz RADAR device, facilitating implementation of Terahertz RADAR on a low power budget. Some aspects of the present disclosure relate to regulating a bias state of a harmonic generation circuit in a receiver and / or transmitter of a Terahertz RADAR device. Some aspects of the present disclosure relate to coupling frequency multipliers between RF amplifiers and RF antennas in a transmitter of a Terahertz RADAR device. Some aspects of the present disclosure relate to frequency multipliers, e.g., in a transmitter of a Terahertz RADAR device, using certain transistor configurations (e.g., common-collector or common-drain). A THz RADAR device May implement one, two, or all three of these aspects.

Aspects of the present disclosure improve operating efficiency of a Terahertz RADAR device, facilitating implementation of Terahertz RADAR on a low power budget. Some aspects of the present disclosure relate to regulating a bias state of a harmonic generation circuit in a receiver and / or transmitter of a Terahertz RADAR device. Some aspects of the present disclosure relate to coupling frequency multipliers between RF amplifiers and RF antennas in a transmitter of a Terahertz RADAR device. Some aspects of the present disclosure relate to frequency multipliers, e.g., in a transmitter of a Terahertz RADAR device, using certain transistor configurations (e.g., common-collector or common-drain). A THz RADAR device May implement one, two, or all three of these aspects.

A memory cell includes an active region extending lengthwise along a first direction and first and second gate structures extending lengthwise along a second direction different from the first direction. The first gate structure engages the active region in forming a first transistor, and the second gate structure engages the active region in forming a second transistor. The memory cell further includes a first epitaxial feature disposed on a source region of the first transistor, a second epitaxial feature disposed on a common drain region of the first and second transistors, a backside contact disposed under and in electrical coupling with the first epitaxial feature, a backside signal line disposed under and in electrical coupling with the backside contact, and a first frontside contact disposed above and in electrical coupling with the second epitaxial feature.

The utility model discloses an ultra-wideband high-linearity low-noise amplifier circuit based on a common source structure, which comprises a first amplifying circuit, an inter-stage matching circuit and a second amplifying circuit which are sequentially cascaded, the drain electrode of the first transistor of the first amplification circuit and the drain electrode of the second transistor of the second amplification circuit are provided with a common drain electrode power supply matching network. The drain electrode power supply mode of the two-stage amplification circuit is optimized and adjusted, so that the drain electrode power supply of the first amplification circuit and the drain electrode power supply of the second amplification circuit jointly pass through the common drain electrode power supply matching network, and the power supply firstly passes through the common drain electrode power supply matching network and then independently supplies power to the first amplification circuit and the second amplification circuit. In addition, in order to expand the bandwidth, LC parallel connection is added to the input matching network of the first amplification circuit and the output matching network of the second amplification circuit, and the bandwidth is expanded by introducing the LC parallel connection to the ground.

A power FET device and a device including the same are disclosed. Techniques for temperature sensing in power FET switches are described. An example power field effect transistor (FET) device includes back-to-back power FETs coupled in series between a first power terminal and a second power terminal and connected to a common drain node. The power FET device also includes a temperature sensing diode including a cathode coupled to the common drain node. A temperature sensing circuit coupled to the power FET device is configured to determine a temperature of the first power FET and the second power FET based on a voltage drop across the temperature sensing diode. The temperature sensing circuit may include a voltage averaging circuit configured to sense a first voltage at the first power terminal, sense a second voltage at the second power terminal, and average the first voltage and the second voltage to generate a drain voltage representative of a voltage of the common drain node.

The application discloses a MOSFET wafer adjacent particle testing method and a testing circuit thereof, and the testing method comprises the following steps: S101, connecting the drain loading end and the drain measuring end of the MOSFET wafer through a resistor; S102, judging the basic function of N measured MOSFET particles to be normal by testing a small current parameter of VTH; S103, testing Rdson, and selecting a particle closest to the measured particle as an auxiliary particle; S104, driving the gate of the auxiliary particle to be always on; and S105, connecting the measuring end of the common drain to the source of the auxiliary particle, and then testing the Rdson parameter; the application further discloses a MOSFET wafer adjacent particle testing circuit, and the testing circuit can improve the measurement accuracy of the Rdson parameter of the MOSFET wafer and effectively reduces the testing error.

A power semiconductor module may include: a common drain pad; a first power semiconductor device on the first region of the common drain pad; a second power semiconductor device on a second region of the common drain pad; a molding layer surrounding lateral portions of the first power semiconductor device and the second power semiconductor device on a peripheral region of the common drain pad; a common gate pad on the first power semiconductor device and the second power semiconductor device; and a source pad on the first power semiconductor device and the second power semiconductor device. The source pad may surround at least two outer lateral portions of the common gate pad.

The application provides a preparation process of a common-drain double MOSFET device and the common-drain double MOSFET device. The symmetric structure is formed on the front surface and the back surface of a wafer, the problems existing in the prior art are solved, and the common-drain double MOSFET wafer with excellent performance, smaller area and stronger packaging performance is produced.

The application discloses an SRAM memory unit of an anti-soft-error SRAM, which has a double interlocking structure and comprises: first and second NMOS tubes which are connected in common source and provide interlocked first and second storage nodes, first and second PMOS tubes which are connected in common source and provide interlocked third and fourth storage nodes, a gate and a source of a fifth MOS transistor which are connected in common drain and are connected between the first and third storage nodes in phase, a gate and a source of a sixth MOS transistor which are connected in common drain and are connected between the second and fourth storage nodes in phase, a gate of a third MOS transistor which is connected to the second storage node, and a source and a drain which are connected between the first and third storage nodes. A gate of a fourth MOS transistor is connected to the first storage node, and a source and a drain are connected between the second and fourth storage nodes. The application can resist multi-node flipping and can improve RSNM and WNM.