34results about How to "Improve error resistance" patented technology

A method for copying information from a first storage subsystem to a second storage subsystem is disclosed. The first and second storage subsystems are provided in a data storage system. The method comprises transmitting first data block from the first storage subsystem to the second storage subsystem, the first storage subsystem being associated with a first host computer and the second storage subsystem being associated with a second host computer; and transmitting first attribute information from the first storage subsystem to the second storage subsystem without intervention from the first host computer.

In the code word mapping operation of a radio communication system, mapping patterns are provided for different S / N ratios, the code word bits produced from a coder are not equally assigned to multi-level modulation bits, but weighted according to the resistance of multi-level modulation bits to error before being assigned, and the mapping patterns are switched in accordance with S / N. Since the code word mapping method is updated so that the error rate can be always minimized according to the situations of a propagation path and S / N ratio, communication can be made with high communication quality.

A static random access memory has first and second complementary field-effect transistors. The first complementary field-effect transistor includes a semiconductor substrate, a first field-effect transistor of electron conduction type which has a first drain region constituting a Schottky junction and a gate electrode, and a first field-effect transistor of positive hole conduction type which shares the first drain region and has a shared gate electrode. The second complementary field-effect transistor includes a second field-effect transistor of electron conduction type which has a second drain region and a gate electrode, a second field-effect transistor of positive hole conduction type which shares the second drain region and has a shared gate electrode. The gate electrode shared by the first and second complementary field-effect transistors is connected to the common drain region of the mutually opposing complementary field-effect transistors, and the static random access memory has superior resistance to software errors.

A communication link comprising: a first transceiver configured to transmit a first set of packets at a predetermined rate with a first error resistance level, store the transmitted data in a buffer, receive a retransmission request, and retransmit the relevant data using one or more packets encoded with a second error resistance level that is higher than the first error resistance level. And a second transceiver configured to receive the first set of packets, detect an erroneous packet, request retransmission of the erroneous packet, and forward the data received in the packets according to its original order approximately after a fixed delay.

The invention discloses a robust video transmission method combined with network coding on an end system and a relay node. An unequal protection algorithm of scalable video coding, a prioritization partition method of scalable code streams, an interleaving and packaging algorithm of video streams and a video quality distortion model are designed, and the video quality distortion model is optimized and solved to obtain an optimal redundancy allocation scheme. A sending end adds proper redundancy on a compression source stream to be transmitted through random linear network coding, and the reliability of video transmission is ensured from the angle of the end system. The relay node reduces energy consumption of network bandwidth resources, and improves efficiency of the video transmission and mistake-resisting performance through the random linear network coding. The robust video transmission method ensures that a receiving end can obtain layered code streams according to the sequences of importance of the scalable code streams, improves the quality of the video transmission, and can adapt to requirements for band widths, computing power and resolution ratios of different terminals in the network.

A construction and decoding method of a space-frequency-domain 2-dimensional bar code is disclosed. The method is characterized by: converting data to be converted into the 2-dimensional bar code into a bit stream; uniformly distributing the bit stream; performing concatenated coding; interlacing and grouping the bit stream; carrying out space frequency domain coding. The invention belongs to an information storage, transmission and identification technology field. The space frequency domain is used to store information so that an equalization technology is convenient to be used to resist influences of a channel and light pollution. A pilot frequency or differential coding is used to resist the positioning error and distortion influences. In the invention, the interlacing is combined with a cascaded code so that an error correction capability of the cascaded code can be substantially improved; a redundancy can be reduced. Compared to the 2-dimensional bar code of the prior art, by using the method of the invention, the larger storage information amount can be possessed.

In a data encoding apparatus, when a prefix length calculation and determination units determine that the code length of a variable length code constituted of continuous bits “0” is equal to or greater than the predetermined maximum prefix length max_prefix during Golomb-Rice encoding of encoding subject data having a fixed length of D bits, second encoding is performed in place of the Golomb-Rice encoding. The second encoding is performed by having a prefix generation unit generate a prefix constituted of continuous bits “0” corresponding to the max_prefix, and having a code generation unit attach the prefix to the upper order bits of the encoding subject data. Furthermore, when a control code such as a restart marker is to be attached, alarmer generation unit generates, as the control code, a code constituted of continuous bits “0” by the number which is equal to or greater than the length of (max_prefix+2×D).

The invention provides a method for improving the fault-tolerant capability of a high-speed cache of a magnetoresistance RAM (Random Access Memory), which is capable of effectively correcting or tolerating random storing and writing errors and realizing a lower storing and writing voltage or a higher storing and writing speed. The storing and writing operation substitutes traditional storing and writing operation by adopting a recursive write-read-check technology to correct random storing and writing errors caused by changing the storing and writing capacity limit or the storing and writing speed. The write-read-check technology means that data are written into a high-speed cache of an MRAM (Magneto-Resistive Random Access Memory), immediately read out and compared with written data; and the write-read-check operation is repeated until all data bits are rightly programmed in case of failures. Based on the write-read-check operation, error-checking codes or error record buffer logic is added to the MRAM high-speed cache, the fault-tolerant capability of the MRAM high-speed cache is enhanced and processor performance degradation brought by the write-read-check operation is reduced.

An image data transmitting apparatus and an image data transmitting method are provided which can distribute streaming moving images at a transfer rate in accordance with a transmission band with degradation in image quality being mitigated even at the time of congestion. A priority determining section 43 reads encoded data stored in the buffer 42 in units of VOP, and then calculates a priority for each VP in terms of VOP based on the amount of encoded data of VP and the number of MBs. A transmission control section 44 determines VPs starting from a VP of the highest priority that have a data amount up to the amount of transmittable encoded data. This determination is made based on the current state of congestion on a network 6 managed by a congestion state managing section 46 and the priorities calculated by the priority determining section 43. A VP transmitting section 45 stores the determined VPs in transmission packets for sequential transmission to a client 5.

The invention discloses a video encoding and decoding system based on image inpainting predication in the technical field of video processing. The system comprises a macroblock partitioning module, a macroblock predication module, a residual encoding module, a residual decoding module and a macroblock rebuilding module, wherein the macroblock predication module comprises an intra-frame predication submodule, an inter-frame predication submodule, an image impainting predication submodule and a mode selection submodule. In the invention, on the basis of a H.264 mixed video encoding standard system, the image inpainting predication submodule is added, which makes up the deficiency of the traditional video encoding and decoding system; and compared with the traditional video encoding and decoding system H.264, the video encoding efficiency is improved and the system has better adaptability and error resistance.

A recording and / or reproducing method for a record medium, includes the steps of reading address information from a record medium having at least a first area and a second area, with data being recordable to the first area, and the second area being followed by the first area, the address information representing the position of the second area; detecting an error corresponding to an error detection code encoded for the address information that has been from the record medium; and, when the result of the detecting step represents that an error has been detected in the address information that has been read from the record medium, notifying at least one user that an error has been detected.

The invention discloses a structure for improving the shock resistance and shock absorption capacity of a tunnel lining and a construction method, and belongs to the technical field of construction of mountain tunnels and underground engineering. The structure comprises a primary support closely attached to surrounding rock and a secondary lining located on the inner side of the primary support. Annular absorbing joints are arranged on the primary support in the longitudinal depth direction of a tunnel at equal intervals. Construction joints reserved during secondary lining construction with a lining trolley are arranged on the secondary lining in the longitudinal depth direction of the tunnel at equal intervals. The annular absorbing joints are filled with concrete containing rubber particles, the construction joints are filled with an asphaltic sand mixing material, and the annular absorbing joints and the construction joints are distributed in a staggered mode. The structure for improving the shock resistance and shock absorption capacity of the tunnel lining and the construction method have the advantages that construction efficiency is high, cost is low and no new seams need to be added.

According to one embodiment, a memory controller that writes write data provided from a host device into a memory, reads read data from the memory, and transmits the read data to the host device. The memory controller includes an external interface, a first ECC generating unit, an access unit, a first ECC correcting unit, and a control unit.

An object of the present invention is to provide a high reliable / high safe programmable logic device with high error resistance. The present invention provides a programmable logic device that has a plurality of configuration memories. The configuration memories are divided into a plurality of areas and are arranged and a part of the plurality of areas is set to a high reliable area where reliability for a failure of the configuration memory is higher than reliability in the other area.

A configuration is such as to change a mode setup of other crossbars influenced by an error occurring in one of plural crossbars from a first mode to a second mode for operating each of them independently (i.e., in a singularization mode) in the case of placing plural crossbars (i.e., crossbar units) for connecting incorporated units (i.e., processing units) and operating the plural crossbars in the first mode (i.e., a dualized mode) for dualizing them, thereby continuing an operation of a system by using a normally operable part when an error occurs in a part of the system.

Embodiments of the invention disclose a memory error processing method, and a related apparatus and system. The memory error processing method comprises the steps of receiving a first user-state data access command sent by a user-state application; converting the first user-state data access command into a first SCSI command; sending the first SCSI command to a memory through an SCSI protocol stack; and when a first response sent by an SCSI protocol is received, indicating that the execution of the first SCSI command fails by the first response, carrying a memory error code by the first response, obtaining a second SCSI command used for repairing the memory, enabling a repair operation indication of the second SCSI command to correspond to the memory error code, and sending the second SCSI command to the memory through the SCSI protocol stack. According to the technical scheme provided by the method, the apparatus and the system, memory error repair can be performed in a targeted manner.

A shuffling table memory has a shuffling table written from an external memory through a path. The external memory stores a plurality of shuffling tables corresponding to the formats of video data to be shuffled. One shuffling table selected according to the result of format determination is stored in the shuffling table memory. The shuffling table memory receives an input ID (IDi) separated from the input data as an address and outputs a converted address (IDo). The converted address (IDo) generated by the shuffling table memory is used as a write address for writing data into a data-accumulation memory. With the read address sequentially changing, shuffled data is read from the data-accumulation memory.

A recording and / or reproducing method for a record medium, includes the steps of reading address information from a record medium having at least a first area and a second area, with data being recordable to the first area, and the second area being followed by the first area, the address information representing the position of the second area; detecting an error corresponding to an error detection code encoded for the address information that has been from the record medium; and, when the result of the detecting step represents that an error has been detected in the address information that has been read from the record medium, notifying at least one user that an error has been detected.

The present invention relates to a method for transporting real-time data from a transmitter to a receiver on a radio packet communication network, said method comprising the steps of: generating, at said transmitter, real-time data frames, said time real-data frames comprising at least two bit portions; selecting said first bit portion and submitting it to a first modulation and coding scheme providing an error-resistance higher than an error-resistance threshold; selecting said second bit portion and submitting it to a second modulation and coding scheme providing an error-resistance lower than said error-resistance threshold; transmitting a first radio packet transmission unit corresponding to said first bit portion to said receiver; transmitting a second radio packet transmission unit corresponding to said second bit portion to said receiver, said second radio packet transmission unit being different from said first radio packet transmission unit.

The invention discloses a water-cooled high-power medium-high frequency power supply device, comprising: the input end of a three-phase rectification circuit is connected to a three-phase power grid; the three-phase rectification circuit is connected to a first AC interface through a first switch K1; the input end of a three-phase inverter circuit The DC bus bar connected to the output end of the three-phase rectification circuit, the output end of the three-phase inverter circuit is connected to the second AC interface through the second switch K2; the first battery pack E1 and the second battery pack E2 connected in series between the DC bus bars, the second Both ends of the battery pack E2 are connected in parallel with a first chopper circuit; the first terminal of the DC interface is connected to the output end of the first chopper circuit, the second terminal of the DC interface is connected to the negative pole of the DC bus bar, and the third terminal of the DC interface passes through the first controllable The switch Q1 is connected to the positive pole of the DC bus; the compensation circuit for stabilizing the voltage at the input end of the three-phase rectification circuit is connected between the output end of the three-phase inverter circuit and the input end of the three-phase rectification circuit. The invention solves the technical problem that the output power of the medium and high frequency power supply device is unstable.

The invention discloses a water-cooling high-power medium-high frequency power supply device. According to the device, the input end of a three-phase rectifying circuit is connected with a three-phase power grid; the three-phase rectifying circuit is connected to a first AC interface through a first switch K1. the input end of a three-phase inverter circuit is connected with a direct-current bus of the output end of the three-phase rectifying circuit, and the output end of the three-phase inverter circuit is connected to a second alternating-current interface through a second switch K2; a first storage battery pack E1 and a second storage battery pack E2 are connected in series between the direct current buses, and two ends of the second storage battery pack E2 are connected in parallel with a first chopper circuit; a first terminal of the direct-current interface is connected with the output end of a first chopper circuit, a second terminal of the direct-current interface is connected with the negative electrode of the direct-current bus, and a third terminal of the direct-current interface is connected with the positive electrode of the direct-current bus through a first controllable switch Q1; and a compensation loop is used for stabilizing the voltage of the input end of the three-phase rectifying circuit and is connected between the output end of the three-phase inverter circuit and the input end of the three-phase rectifying circuit. The technical problem that the output power supply of the medium-high frequency power supply device is unstable is solved.