74 results about "Error detection coding" patented technology

The invention relates to a front-end code testing method and system, electronic equipment and a storage medium. The method is applied to a code analysis system and comprises the steps that a code test task for a to-be-tested front-end code is received, the code test task comprises use case constraint conditions and test target information of the to-be-tested front-end code, code feature vectors are extracted from the to-be-tested front-end code, and the test target information is sent to the to-be-tested front-end code; and iteratively generating a target test case according to the case constraint condition and the test target information, and obtaining a test result of the to-be-tested front-end code by running the target test case and the error detection code feature vector. According to the scheme provided by the invention, the defect of the to-be-tested front-end code can be efficiently and comprehensively captured, and an accurate and reliable test result is output.

Provided are a data transmission method and a related device, the method comprising: a sending device generating a data burst, in the data burst, a first part of data comprising a PDU corresponding to first data, the first data comprising key information, and a second part of data comprising a PDU corresponding to second data and a first error detection code, the first error detection code is obtained by processing part or all of the PDU corresponding to the first data and the PDU corresponding to the second data; the sending device sends the data burst; and the receiving equipment receives the data burst and decodes the data burst. The first error detection code is obtained by processing part or all of the PDU corresponding to the first data and the PDU corresponding to the second data through a detection algorithm, and can be used for carrying out error detection on the PDU corresponding to the first data and the PDU corresponding to the second data, so that the error detection efficiency of the PDU corresponding to the first data and the PDU corresponding to the second data is improved under the condition that air interface burst resources are not increased. And the error detection capability of the key information in the data burst is improved.

The invention discloses an adaptive modulation and coding method based on LSTM-DQN, and belongs to the field of meteor trail communication. Aiming at the problem of insufficient timeliness of channel state information caused by long transmission time delay of a meteoric trail communication channel and the problem that performance reduction of a traditional adaptive modulation coding algorithm in a fast time-varying channel is limited, the invention provides a method for carrying out strategy selection by combining an LSTM (Long Short Term Memory) and a DQN (Digital Quality Network) network so as to improve the throughput of a system. The method comprises the following steps that firstly, a network framework of LSTM and DQN is initialized, the transmission condition of each step is obtained through a signal-to-noise ratio estimation algorithm and error detection codes to serve as neural network training data, and then the LSTM is responsible for conducting time sequence prediction to improve the problem that channel state information is expired; the DQN network uses empirical playback and a target network to train an adaptive modulation coding policy network. Through continuous iteration of network parameters, selection of modulation and coding scheme strategies under different channel states is optimized, and then a modulation and coding scheme which is more suitable for the current state of a channel is obtained.

Redundant data storage includes performing a first data transfer to a first storage device as part of a redundant write operation. A first error detection code is generated for the first data transfer. A second data transfer is performed to a second storage device as part of the redundant write operation. A second error detection code is generated for the second data transfer. The first error detection code is compared with the second error detection code for a match indicating that data of the first data transfer matches data of the second data transfer.

A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.

Embodiments of the invention relate to a MAC PDU comprising MAC subheader and MAC SDU pairs encoded with error detection codes. More specifically, a first communication device (100) transmits a MAC PDU to a second communication device (300). The MAC PDU comprises at least one MAC subheader and MAC SDU pair. The at least one MAC subheader and MAC SDU pair comprises a plurality of data fields appended to the MAC subheader and being encoded with a first error detection code, and the plurality of data fields comprising a first data field indicating a length of a pay load of the MAC SDU and a second data field indicating a length of at least the MAC subheader and a header stack of the MAC SDU, and the MAC subheader and the header stack are encoded with a second error detection code. Furthermore, embodiments of the invention also relate to a first and a second communication device, corresponding methods and a computer program.

The embodiment of the invention provides a shielded packet checksum method for more efficient digital communication, computing equipment and storage equipment. The method may generate a packet error detection code that protects only a portion of a respective packet from transmission errors, and the method includes, for a first packet associated with a first bitmask, generating a first packet error detection code based on data of the first packet, the data of the first packet is within the portion indicated by the first bit mask to be included in the error detection code to exclude at least some data within other portions of the first packet, the first packet having only a single corresponding packet error detection code; wherein the first bit mask indicates that the portion to be included in the error detection code includes a header of the first packet and a first portion of the first packet that is discontinuous from the header of the first packet.

A method performed by a wireless device to determine how long the wireless device can operate in a different mode. The method includes receiving a physical layer protocol data unit (PPDU) carrying an initial control frame, determining whether contents of the PPDU leading up to an intermediate error detection code field are valid using an error detection code extracted from the intermediate error detection code field, responsive to determining that the contents are valid, switching from operating in a first operation mode to operating in a second operation mode before completely receiving the PPDU, and determining a duration for which the wireless device can operate in the second operation mode based on the duration from the start of the preamble of the PPDU to the end of the intermediate error detection code field and the duration of the PPDU.

A method for manufacturing a reused battery system (1) is provided with: a used battery management unit (10) receiving characteristic map data (1P) corresponding to the state after the start of reuse of the used battery; the management unit (10) verifies the received characteristic mapping data (1P) using the error detection code attached to the characteristic mapping data (1P); and if the received characteristic mapping data (1P) is correct, the management unit (10) stores the characteristic mapping data (1P) in the storage unit (101).

Disclosed are a method of transmitting and receiving image signals and an image processing device for implementing the same, by which an error detection code for verification of image related data can be provided in transmitting the image related data to a receiving side from a transmitting side. The disclosure includes generating a control field frame including Average Picture Level (APL) data of image data and an error detection code for the APL data, transmitting the generated control field frame in a vertical blanking period according to a serial interface system, and transmitting pixel data of the image data in a vertical non-blanking period according to the serial interface system.

A measurement device, a control method, and a control program that can improve analysis efficiency of biological data are provided. A measurement device according to one aspect of the present invention includes a control unit (30) that performs measurement based on biological data obtained by a sensor and wireless communication with an information terminal (5). Then, the control unit (30) assigns an error detection code in a variable data length unit corresponding to content of the biological data to the biological data obtained by sensing by the sensor, and transmits, to the information terminal (5), the biological data with the error detection code assigned.

This invention relates to a log management method and a log management system. Embodiments for reliable, safety-critical system logs are disclosed. In one embodiment, a method includes: obtaining data to be added to a log; creating entries for the data; and adding the entries to a linked sequence of entries in the log, wherein the linked sequence of entries includes a plurality of data entries and a plurality of sentinels intertwined with the plurality of data entries, wherein each data entry in the entry chain is appended to an error detection code calculated for that entry and a previously calculated error detection code or error detection root of the preceding data entry, and each sentinel in the entry chain includes an error detection code calculated for that sentinel and a previously calculated error detection code or error detection root of the preceding data entry, and each sentinel includes a previously calculated and encrypted blockchain value or blockchain root value of the preceding sentinel.

A completely de-energizable defibrillator is provided, allowing the electrical components of the defibrillator to be electrically unbiased while the defibrillator is not in use. The energizing of the defibrillator can be controlled through a power switch interfaced to a relay, with the microcontroller of the AED being able to de-energize the circuitry in case of unintended activation. Additionally, the microcontroller unit of the AED includes features to prevent computational errors due to external influences, electromagnetic interference, radio frequency interference, ionizing radiation, high energy particles, cosmic radiation, and / or solar radiation, or a combination thereof, including one or more pairs of lockstep processors, error detection code, and features that prevent tampering with the microcontroller.

A communication method according to one embodiment of the present invention is used in a mobile communication system. The communication method includes a step in which a reader device, which is a network node or a user device of the mobile communication system, receives a first message transmitted from an ambient Internet of Things (IoT) device. In addition, the communication method includes a step in which the reader device generates an error detection code on the basis of data included in the first message. Further, the communication method includes a step in which the reader device transmits a second message including an error detection code to the ambient IoT device. Further, in the ambient IoT device, a contention resolution is determined on the basis of the error detection code of the data included in the first message and the error detection code included in the second message.

A system and related method includes a memory and processing circuitry to receive data and corresponding expected error detection code values. The processing circuitry processes data in the at least two portions by calculating and storing error detection code values for the respective portions in the memory. The processing circuitry is then to calculate a total error detection code value based on the respective error detection code values of the at least two portions. When the total error detection code value does not match the expected error detection code value, the processing circuitry is to correct the at least one portion and to correct the at least one portion by calculating an updated error detection code value for a respective one of the corrected portions and calculating an updated total error detection code value based on the updated error detection code value for each corrected portion and the stored error detection code value. The corrected portion is processed.

The described technology provides a multi-level error correction method, including encoding data received from a double data rate (DDR) memory by performing primary coding to generate transitional symbols, wherein the primary coding comprising at least one of cyclical redundancy check (CRC) encoding and single error correction double error detection (SECDED) encoding, performing a secondary coding on the transitional symbols to generate inner codes, the inner codes comprising code 1 parities generated from the transitional symbols and code 2 parities generated from the transitional symbols and metadata stored on the DDR memory, wherein the secondary coding comprising Reed Solomon (RS) encoding, and saving the inner codes on parity bit storage locations on a die of the DDR memory.

Communication systems and methods are disclosed that utilize Probability Amplitude Shaping (PAS) and Trellis Coded Modulation (TCM) to transmit short block-length messages. While capacity-approaching codes, such as Low Density Parity Check (LDPC) codes, Turbo codes, and Polar codes, can achieve data rates approaching the Shannon limit at large block-lengths, the performance of these codes can deteriorate dramatically at short block-lengths. Communication systems configured in accordance with various embodiments of the invention can utilize classical codes to encode short block-length messages to achieve communication rates exceeding Polyanskiy's Random Coding Union bound. In several embodiments, message bits are transmitted using a TCM system in which message bits that have been previously encoded by an error detection code are encoded using a convolutional code (CC). In a number of embodiments, the error detection code and the CC are obtained via a joint optimization with respect to a Frame Error Rate bound.

A device comprising the following: physical layer logic for: receiving initial data on multiple data lanes of a physical connection; receiving a current signal corresponding to the initial data on a current lane, wherein the current lane is another of the lanes of the physical connection, and wherein the current signal corresponding to the initial data serves to identify a type of initial data; identifying a first instance of a fault detection code of a specific type in the initial data; receiving second data on at least some of the multiple data lanes; receiving a current signal corresponding to the second data on the current lane, wherein the current signal corresponding to the second data serves to identify a type of second data, the type of second data being different from the type of first data;and identifying a second instance of the error detection code of the special type in the second data, and path error detection logic for: determining from a syndrome associated with the error detection code corresponding to the first data that a bit error is present in the first data; determining from the syndrome in which bit of the first data the error occurred; and assigning the bit with the error to one of the several paths.

Light emitting diode (LED) packages are disclosed, and more particularly, error detection in LED packages is disclosed. The LED packages are arranged for cascade communication as part of a larger LED display. A separate active electronic component is integrated with each LED package to facilitate active matrix addressing from the data stream, check for input error detection codes, and generate new output error detection codes into the data stream. Each electronic component within each LED package is capable of independently changing one or more portions of the data received in the data stream, transmitting the changed data to the next downstream LED package, and generating an output error detection code based on the changed data. When the active electronic component recognizes corrupted data based on the input error detection code, the generated output error detection code may be corrupted intentionally, so that the downstream LED package also recognizes that the corresponding data has been corrupted.

Light-emitting diode (LED) packages and more particularly error detection in LED packages is disclosed. LED packages are arranged for cascade communication as part of a larger LED display. A separate active electrical element is integrated with each LED package for facilitating active matrix addressing from a data stream, checking input error detection codes, and generating new output error detection codes to the data stream. Each electrical element within each LED package is separately capable of changing one or more portions of received data in the data stream, transmitting the changed data to the next downstream LED package, and generating output error detection codes based on the changed data. When the active electrical element identifies corrupted data based on input error detection codes, the generated output error detection codes may be intentionally corrupted so downstream LED packages will also identify the respective data as being corrupted.

Cyclic redundancy check (CRC) algorithms are utilized in digital communication and storage systems for error detection. CRC encoding and decoding may be implemented using linear feedback shift registers (LFSRs). To achieve high throughput, a parallel LFSR may be implemented by registers using feedback matrix and pre-processing matrix multiplication. In conventional architectures, a feedback matrix may be decided by look-ahead computations of an FSR, and the corresponding matrix multiplication may contribute to a significant portion of the overall complexity of the LFSR. The methods described herein are provide for searching over a wide range of powers of a companion matrix describing the parallel LFSR in order to minimize the logic gate count required for the feedback matrix multiplication.

The described technology provides a multi-level error correction method including encoding data received from a dual data rate (DDR) memory by performing primary encoding to generate transition symbols, where the primary encoding includes at least one of cyclic redundancy check (CRC) encoding and single error correction dual error detection (SECDED) encoding; performing secondary encoding on the transition symbol to generate an inner code, the inner code including a Code 1 parity generated from the transition symbol and a Code 2 parity generated from the transition symbol and metadata stored on the DDR memory, where the secondary encoding includes Reed-Solomon (RS) encoding, and saving the inner code on a parity storage location on a die of the DDR memory.

The invention discloses a digital phased-array antenna synchronization method and device, particularly relates to the field of digital communication, and is used for solving the problem that framing boundaries and time identifier mapping of service data streams are difficult to stably align under the conditions of cache jitter and clock micro-drift. The sending end inserts a first synchronous anchor frame and a second synchronous anchor frame after the calibration synchronization is triggered, writes an alignment element identifier and a count value of a sending sampling counter, and registers a sending cache record table; a receiving end verifies the error detection code, pairs anchor frames according to a fixed anchor spacing rule, calculates an alignment offset and a forward inter-anchor stepping steady-state length, and generates an alignment proof message; checking the sending cache record table and the proof code, counting that the return proof reaches consistent continuity, indexing an offline training confidence matrix and outputting an alignment credibility level, and when conditions are met, updating framing boundary and time identifier mapping and sending a mapping effective message; and the receiving end starts the mapping version identifier, rechecks the stability of the alignment offset by means of the monitoring anchor frame, and sends a resynchronization request when the alignment offset fails.

A first flit is generated according to a first flit format, where a first number of error detection codes are to be provided for an amount of data to be sent in the first flit, and the first flit is to be sent on a link by the transmitter while the link operates with a first link width. The link transitions from a first link width to a second link width, where the second link width is narrower than the first link width. A second flit is generated according to a second flit format based on the transition to the second link width, where the second flit is to be sent while the link operates at the second link width, and the second flit format defines that a second, higher number of error detection codes are to be provided for the same amount of data.

This invention discloses a data verification method, a distributed system, and a storage medium. The method includes: a first server receiving a first acquisition request from a second server for requesting target data, and converting the target data into first error detection information using a preset processing algorithm; the first error detection information includes a first parity error detection code; the second server receiving the first error detection information and the target data encapsulated and transmitted by the first server, and generating a second parity error detection code based on the received first error detection information; the second server confirming whether the second parity error detection code matches the first parity error detection code; if the second parity error detection code does not match the first parity error detection code, the second server determining that the target data transmission is erroneous, and resending a second acquisition request to the first server for requesting new target data. This invention ensures data transmission consistency and improves data verification speed and efficiency.

The memory component and the controller transmit commands and data to each other. The commands to activate and then access the data, and the data itself, are transmitted between the controller and the memory component at different times. The controller and the memory component each calculate a corresponding error detection code (EDC) value for the activation command information (e.g., the memory bank address and the row address), and store the error detection code value indexed by the memory bank address. When the memory component is accessed, the retrieved EDC value is combined with the EDC value calculated based on the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for inspection.

The invention provides a control device, a detection method, and a detection program, which can detect whether a power supply is cut off when writing data is written into a non-rewritable storage part, and can repair the stored writing data. In a control device, a processor acquires write data, assigns an error detection code to the write data as first write data and stores the write data in a first region of a non-volatile storage unit, and stores the first write data as second write data in a second region of a non-rewritable storage unit. The second write data is stored as third write data in a third region of the non-volatile storage unit.

A first flit is generated according to a first flit format, where a first number of error detection codes are to be provided for an amount of data to be sent in the first flit, and the first flit is to be sent on a link by the transmitter while the link operates with a first link width. The link transitions from a first link width to a second link width, where the second link width is narrower than the first link width. A second flit is generated according to a second flit format based on the transition to the second link width, where the second flit is to be sent while the link operates at the second link width, and the second flit format defines that a second, higher number of error detection codes are to be provided for the same amount of data.