21 results about "Error detection coding" patented technology

Embodiments of the invention relate to a MAC PDU comprising MAC subheader and MAC SDU pairs encoded with error detection codes. More specifically, a first communication device (100) transmits a MAC PDU to a second communication device (300). The MAC PDU comprises at least one MAC subheader and MAC SDU pair. The at least one MAC subheader and MAC SDU pair comprises a plurality of data fields appended to the MAC subheader and being encoded with a first error detection code, and the plurality of data fields comprising a first data field indicating a length of a pay load of the MAC SDU and a second data field indicating a length of at least the MAC subheader and a header stack of the MAC SDU, and the MAC subheader and the header stack are encoded with a second error detection code. Furthermore, embodiments of the invention also relate to a first and a second communication device, corresponding methods and a computer program.

This invention relates to a log management method and a log management system. Embodiments for reliable, safety-critical system logs are disclosed. In one embodiment, a method includes: obtaining data to be added to a log; creating entries for the data; and adding the entries to a linked sequence of entries in the log, wherein the linked sequence of entries includes a plurality of data entries and a plurality of sentinels intertwined with the plurality of data entries, wherein each data entry in the entry chain is appended to an error detection code calculated for that entry and a previously calculated error detection code or error detection root of the preceding data entry, and each sentinel in the entry chain includes an error detection code calculated for that sentinel and a previously calculated error detection code or error detection root of the preceding data entry, and each sentinel includes a previously calculated and encrypted blockchain value or blockchain root value of the preceding sentinel.

A communication method according to one embodiment of the present invention is used in a mobile communication system. The communication method includes a step in which a reader device, which is a network node or a user device of the mobile communication system, receives a first message transmitted from an ambient Internet of Things (IoT) device. In addition, the communication method includes a step in which the reader device generates an error detection code on the basis of data included in the first message. Further, the communication method includes a step in which the reader device transmits a second message including an error detection code to the ambient IoT device. Further, in the ambient IoT device, a contention resolution is determined on the basis of the error detection code of the data included in the first message and the error detection code included in the second message.

Light-emitting diode (LED) packages and more particularly error detection in LED packages is disclosed. LED packages are arranged for cascade communication as part of a larger LED display. A separate active electrical element is integrated with each LED package for facilitating active matrix addressing from a data stream, checking input error detection codes, and generating new output error detection codes to the data stream. Each electrical element within each LED package is separately capable of changing one or more portions of received data in the data stream, transmitting the changed data to the next downstream LED package, and generating output error detection codes based on the changed data. When the active electrical element identifies corrupted data based on input error detection codes, the generated output error detection codes may be intentionally corrupted so downstream LED packages will also identify the respective data as being corrupted.

Cyclic redundancy check (CRC) algorithms are utilized in digital communication and storage systems for error detection. CRC encoding and decoding may be implemented using linear feedback shift registers (LFSRs). To achieve high throughput, a parallel LFSR may be implemented by registers using feedback matrix and pre-processing matrix multiplication. In conventional architectures, a feedback matrix may be decided by look-ahead computations of an FSR, and the corresponding matrix multiplication may contribute to a significant portion of the overall complexity of the LFSR. The methods described herein are provide for searching over a wide range of powers of a companion matrix describing the parallel LFSR in order to minimize the logic gate count required for the feedback matrix multiplication.

The described technology provides a multi-level error correction method including encoding data received from a dual data rate (DDR) memory by performing primary encoding to generate transition symbols, where the primary encoding includes at least one of cyclic redundancy check (CRC) encoding and single error correction dual error detection (SECDED) encoding; performing secondary encoding on the transition symbol to generate an inner code, the inner code including a Code 1 parity generated from the transition symbol and a Code 2 parity generated from the transition symbol and metadata stored on the DDR memory, where the secondary encoding includes Reed-Solomon (RS) encoding, and saving the inner code on a parity storage location on a die of the DDR memory.

The invention discloses a digital phased-array antenna synchronization method and device, particularly relates to the field of digital communication, and is used for solving the problem that framing boundaries and time identifier mapping of service data streams are difficult to stably align under the conditions of cache jitter and clock micro-drift. The sending end inserts a first synchronous anchor frame and a second synchronous anchor frame after the calibration synchronization is triggered, writes an alignment element identifier and a count value of a sending sampling counter, and registers a sending cache record table; a receiving end verifies the error detection code, pairs anchor frames according to a fixed anchor spacing rule, calculates an alignment offset and a forward inter-anchor stepping steady-state length, and generates an alignment proof message; checking the sending cache record table and the proof code, counting that the return proof reaches consistent continuity, indexing an offline training confidence matrix and outputting an alignment credibility level, and when conditions are met, updating framing boundary and time identifier mapping and sending a mapping effective message; and the receiving end starts the mapping version identifier, rechecks the stability of the alignment offset by means of the monitoring anchor frame, and sends a resynchronization request when the alignment offset fails.

This invention discloses a data verification method, a distributed system, and a storage medium. The method includes: a first server receiving a first acquisition request from a second server for requesting target data, and converting the target data into first error detection information using a preset processing algorithm; the first error detection information includes a first parity error detection code; the second server receiving the first error detection information and the target data encapsulated and transmitted by the first server, and generating a second parity error detection code based on the received first error detection information; the second server confirming whether the second parity error detection code matches the first parity error detection code; if the second parity error detection code does not match the first parity error detection code, the second server determining that the target data transmission is erroneous, and resending a second acquisition request to the first server for requesting new target data. This invention ensures data transmission consistency and improves data verification speed and efficiency.

A self-managed DRAM module and method. The module includes a plurality of DRAM chips; and a controller chip configured to store a data block received from a host according to a process that includes: compressing the data block to generate a compressed data block; performing error detection code (EDC) encoding on the compressed block and adding an EDC redundancy to the compressed block; partitioning the compressed block with the EDC redundancy into a set of m data chunks; performing error correction code (ECC) encoding on each of the m data chunks to generate m codewords; and writing the m codewords to the DRAM chips.

Systems and methods for error detection in video data are described. An encoding computing system can receive a video frame. The encoding computing system can encode and decode the video frame based on an encoding scheme. The encoding computing system can generate a frame error detection code for the decoded video frame based on an error detection code generation scheme. The encoding computing system can send the encoded video frame and the error detection code to a decoding computing system. The decoding computing system can decode the encoded video frame and generate a second error detection code using the code generation scheme. The decoding computing system can detect a decoded video frame corruption by comparing the error detection code and the second error detection code.

A completely de-energizable defibrillator is provided, allowing the electrical components of the defibrillator to be electrically unbiased while the defibrillator is not in use. Additionally, the microcontroller unit of the AED includes features to prevent computational errors due to external influences, electromagnetic interference, radio frequency interference, ionizing radiation, high energy particles, cosmic radiation, and / or solar radiation, or a combination thereof, including one or more pairs of lockstep processors, error detection code, and features that prevent tampering with the microcontroller.

Embodiments refer to applications, platforms, architectures, etc., for authenticating and initializing a peripheral device. For example, one or more initialization operations may be performed on the peripheral device before it is authenticated. In these and other embodiments, authentication may be based on information maintained during initialization, such as error detection code values ​​and / or message counter values. Performing the authentication and initialization operations in the disclosed manner can reduce the time required for authenticating and initializing peripheral devices compared to the typical practice of authenticating first and then initializing.

A semiconductor device includes a first semiconductor die including a first interface circuit; and a second semiconductor die stacked with the first semiconductor die and including a second interface circuit connected to the first semiconductor die by a plurality of via structures, wherein the first interface circuit is configured to generate an error detection code for transmission data and transmit the data signal including the transmission data and the error detection code to the second interface circuit through at least some of the plurality of via structures, and the second interface circuit is configured to generate response data indicating whether the data signal is normally received and an error correction code of the response data, and transmit a response signal including the response data and the error correction code to the first interface circuit through at least one via structure among the plurality of via structures.

A fault detection system includes a state register, an error detection code (EDC) register, logic circuitry, an EDC generator, and an EDC checker. The state and EDC registers store first reference data and first checksum data, respectively. The logic circuitry executes a logic function based on the first reference data to iteratively generate second reference data that is different from the first reference data, and updates the first reference data of the state register with the second reference data of one iteration. The EDC generator iteratively generates second checksum data based on the iteratively generated second reference data and updates the first checksum data of the EDC register with the second checksum data of one iteration. The EDC checker detects a fault in the IC based on the updated first reference data and the updated first checksum data.

This quantum error detection device generates a logical state |+⟩ L, 1 of a first quantum error detection code that is a quantum error detection code representing one logical qubit by n1 physical qubits and is a quantum error detection code having a code distance d1. The quantum error detection device executes a logical Rz rotation gate operation of the first quantum error detection code with respect to the logical state |+⟩ L, 1 of the first quantum error detection code, thereby generating a logical state |+θ⟩ L, 1 of the first quantum error detection code. The quantum error detection device executes a sequence of unitary quantum gate operations with respect to the logical state |+θ⟩ L, 1 of the first quantum error detection code, thereby converting the logical state |+θ⟩ L, 1 of the first quantum error detection code into a second quantum error detection code representing one logical qubit by n2 (n2 > n1) physical qubits. The quantum error detection device acquires an error syndrome of a logical state |+θ⟩ L, 2 of the second quantum error detection code.

A code generation device 1 which generates code in which parameter setting in an API call has been corrected comprises: a detection code addition unit 11 which generates second code by adding API error detection code for detecting an error related to a defect in API parameter setting to first code containing API call processing; a code execution unit 12 which executes the second code, and if said error is not detected, outputs the second code as code in which parameter setting in the API call has been corrected, and if said error is detected, stores the execution result of the code containing the error; a prompt creation unit 13 which creates a prompt containing the second code, the code execution result, and an instruction text for correcting the second code on the basis of the code execution result, and which inputs the prompt to a learning server; and a corrected code re-input unit 14 which re-inputs the corrected code output from the learning server to the code execution unit as second code.

The invention relates to device initialization and authentication for computing systems and applications. Various embodiments relate to applications, platforms, architectures, and the like for authenticating and initializing peripheral devices. For example, before the peripheral device is authenticated, one or more initialization operations with respect to the peripheral device may be performed. In these and other embodiments, authentication may be based on information maintained during initialization, such as error detection code values and / or message counter values. Performing the authentication and initialization operations in the disclosed manner may reduce the amount of time used to authenticate and initialize the peripheral device as compared to as typically done to authenticate first and then initialize.

This terminal comprises: a control unit that assumes that the payload of a low-power wake-up signal is divided into segments corresponding to a terminal group, and that an error detection code is assigned to each segment; and a reception unit that monitors and receives the low-power wake-up signal.

A semiconductor device is provided. The storage device comprises a plurality of storage elements, each of which is designed to store a data value; and a controller designed to read a plurality of stored data values ​​from the plurality of storage elements; to process the stored data values ​​using an error detection code to generate a first erase vector; to map an address list of permanently dysfunctional storage elements, generated during the initial testing of the storage device, to the plurality of storage elements to generate a second erase vector; and to process the plurality of stored data values ​​using an error correction code, taking into account the first and second erase vectors.

According to one embodiment, a communication method is provided. The communication method includes performing a first operation when a first condition is satisfied for B mode and A mode. The B mode uses B transmission unit. The A mode uses A transmission unit. The first operation generates a data frame by adding B error detection code and A error detection code to data. The B error detection code corresponds to the B transmission unit. The A error detection code corresponds to the A transmission unit. The communication method includes performing a second operation when a second condition is satisfied for the B mode and the A mode. The second operation generates a data frame by adding the B error detection code to data without adding the A error detection code to the data. The communication method includes transmitting the data frame generated in the first operation or the second operation.