17 results about "Inverse operation" patented technology

The invention relates to the technical field of information security, in particular to a lightweight encryption and decryption method, which comprises the following steps: acquiring a continuous binary data stream of a sensor and segmenting the continuous binary data stream into fixed-length groups; calling a pre-generated round key sequence and a whitening key, wherein the round key sequence is generated through master key shift operation and round constant iteration; performing XOR operation on the grouped data and the whitening key to output initial confusion data; segmenting the initial confusion data into four equal-length sub-segments to execute multiple rounds of iterative processing, wherein each round comprises 16-bit modular addition operation and fixed-bit cyclic shift; xOR is carried out on the shifted data and a current round key, a sub-segment state is updated according to a preset branch processing rule, and linear transformation is carried out on the updated state by adopting a self-inverse matrix; the last-round output sub-segments are spliced into a ciphertext to be transmitted to an execution mechanism; during decryption, reversely calling the round key sequence, and multiplexing the self-inverse matrix to execute inverse transformation and reverse operation to recover original data. The problem of high encryption delay of industrial control equipment is solved.

The invention provides a modular inverse operation hardware implementation system based on Hensel lemma and Newton iteration, belongs to the technical field of hardware security, and is specially used for accelerating modular inverse operation of prime power modulus in a security encryption chip. In the algorithm level, hierarchical modulus expansion improved by Hensel is combined with Newton-Raphson iteration, so that the iteration level is reduced, and the post-processing overhead is eliminated. In hardware implementation, a dynamic resource multiplexing architecture driven by a state machine is adopted, a configurable multiplication-modulo composite circuit and a shift-addition and subtraction unit are integrated, pipeline parallelization is realized through a register block double-buffer design, the bit width of an intermediate variable is compressed by 40%-50%, and the logic resource consumption is reduced by 35%-45%. Real-time calculation of modulus at pk (k is smaller than or equal to 256) is supported, the working frequency reaches 300-350 MHz, only log2 (k) + 5 periods are needed for single modular inverse operation, and the speed is effectively increased. The method can be integrated in hardware acceleration modules of various algorithms, and the key generation and signature verification efficiency is remarkably optimized.

The application provides a small interval interpolation fitting bootstrap method based on a residue system, which splits operation data into multiple numbers with less digits by using the residue system, respectively performs Lagrange interpolation calculation in multiple small intervals, and finally combines the calculation results to obtain fresh ciphertext after bootstrap, so as to improve the overall efficiency of the bootstrap process. Compared with the prior art, the application can effectively improve the operation efficiency of the modular multiplication operation and the modular inverse operation, and reduce the time consumption of the scheme under high security parameters. When there are parallel executable tasks in the scheme, the efficiency of the scheme can be greatly improved through parallel processing. Compared with the original bootstrap method, the scheme realizes the operation of the module function in the approximate calculation full homomorphic encryption scheme bootstrap process, and greatly improves the operation efficiency of the scheme bootstrap process.

In one embodiment, a method includes, in a first adder circuit of a cryptographic engine, combining a round key with a masking plaintext to generate an additive masking input; converting, in a first converter of the encryption engine, the additive mask input to a multiplicative mask input; and in a replacement box circuit of the encryption engine, performing a non-linear inverse operation on the multiplication mask input when the multiplication mask input is non-zero, and performing a non-linear inverse operation on the random non-zero value when the multiplication mask input is zero. Other embodiments are described and claimed.

The embodiment of the present application provides a mask protection method and device for the Advanced Encryption Standard AES algorithm, including performing XOR processing on the data carrying the i-th round mask and the key data, reusing N multiplication modules to perform inversion operation and affine transformation, performing row transformation, if i=10, performing mask compensation, and then performing demasking processing, outputting the ciphertext processed by the key data, if i<10, after column confusion, performing mask compensation, obtaining the j-th round data carrying the mask, and continuing to perform the step of performing XOR processing on the j-th round data carrying the mask and the key data, j=i+1, 2≤j≤10. That is to say, when performing the inversion operation, the multiplication module is reused to optimize the inversion operation in the AES algorithm. Compared with the resources required by the multiplication module in other protection methods, the resource overhead occupied by the multiplication module in the present application is greatly reduced, meeting the requirements of reducing the use of resources and reducing resource overhead of the protection method.

The application provides a digital signature verification method and device, electronic equipment and a storage medium, which comprises the following steps: calculating a point on an elliptic curve based on Jacobian projection coordinate system change to avoid one division operation, and further avoiding inverse operation by transformation under the premise of only adding one judgment step by using the characteristics of finite field operation. By optimizing the inverse algorithm on different prime fields, the modulus inverse operation required for the final coordinate system conversion in the digital signature verification calculation process is converted into modulus multiplication operation under the same condition by adding one judgment, and considering that the overhead of inverse operation is often much larger than that of modulus multiplication operation, the verification speed is greatly improved after the improvement.

The invention discloses a security detection method and device for a cryptographic algorithm, and the method comprises the steps: setting target plaintext data, and carrying out the processing of a target plaintext through a predefined cryptographic algorithm, and obtaining a target ciphertext; performing inverse operation of CBC chain operation on the target ciphertext to obtain an intermediate ciphertext; comparing the target plaintext data with the intermediate ciphertext, and cracking to obtain an S box; constructing an inverse S box according to the S box; solving according to the intermediate ciphertext and the inverse S box to obtain a decryption result; and comparing the decryption result with the target plaintext data to obtain a comparison result. The device comprises a memory and a processor used for executing the security detection method of the cryptographic algorithm. The invention provides a new direction aiming at the security performance detection of the encryption method. The method can be widely applied to the field of security detection.

The present application relates to the technical field of information security, and more particularly to a lightweight encryption and decryption method, comprising: obtaining sensor continuity binary data stream and dividing it into fixed length packets; calling pre-generated round key sequence and whitening key, wherein the round key sequence is generated by main key shift operation and round constant iteration; performing XOR operation on the packet data and the whitening key to output initial confusion data; dividing the initial confusion data into four equal length subsegments to perform multi-round iteration processing, each round including 16-bit modulo addition operation and fixed bit cyclic shift; performing XOR operation on the shifted data and the current round key, updating the subsegment state according to a preset branch processing rule, and performing linear transformation on the updated state using a self-inverse matrix; splicing the subsegments output in the last round into ciphertext and transmitting to an execution mechanism; and calling the round key sequence in reverse direction during decryption, performing inverse transformation and inverse operation using the self-inverse matrix to restore the original data. The present application solves the problem of high encryption delay of industrial control equipment.

In one embodiment, a method comprises: combining, in a first adder circuit of a cryptographic engine, a round key with masked plaintext to generate an additively masked input; converting, in a first converter of the cryptographic engine, the additively masked input to a multiplicatively masked input; and performing, in a substitution box circuit of the cryptographic engine, a non-linear inverse operation on the multiplicatively masked input when the multiplicatively masked input is non-zero, and performing the non-linear inverse operation on a random non-zero value when the multiplicatively masked input is zero. Other embodiments are described and claimed.

The invention discloses a quantum processor and a plaintext encryption method for realizing S box replacement calculation, and relates to the technical field of quantum calculation, the replacement calculation is S (a) = Aa-1 + c, a represents a byte of a plaintext, S (a) is a replacement calculation result, and the quantum processor comprises a modular inverse operation circuit, a first multiplication operation circuit and a modular addition operation circuit; the modular inverse operation circuit acts on the first register to convert modular inverse operation of an element a in a first finite field into modular inverse operation of an element P in a combined field of the first finite field, a modular inverse operation result is stored in the second register, an initial quantum state of the first register is a quantum state corresponding to the element a, P = Ma, and P = Ma; m is a conversion matrix from the first finite field to a first finite field combination field; the first multiplication operation circuit and the modular addition operation circuit sequentially act on the second register and are used for conducting Aa-1 + c calculation on the modular inverse operation result a-1 stored in the second register to obtain a replacement calculation result S (a), and S box replacement calculation can be achieved through a quantum computer.

The present invention discloses a processing method and device for triangular matrix inverse operation. The method includes: evenly dividing the target task into multiple computing cores of the target processing platform; obtaining the triangular matrices corresponding to the multiple blocks, and inverting the triangular matrix to obtain the inverse matrix of the triangular matrix; storing the diagonal elements and the unit matrix of the inverse matrix of the triangular matrix into the first storage medium, respectively, and storing the known part of the inverse matrix and the coefficient matrix into the second storage medium; retrieving data from the first storage medium to perform parallel calculations on the data retrieved from the first storage medium, and retrieving data from the second storage medium to perform cube volume calculations on the data in the second storage medium, and obtaining the inverse operation result of the inverse matrix. The present invention solves the technical problem in the related art that the execution of triangular matrix inverse operation on the artificial intelligence computing platform NPU involves a large number of scalar operations and a high degree of operation dependence, making the entire processing process inefficient.

The embodiments of this specification provide a permutation encryption and decryption method and device suitable for homomorphic operations. When encrypting plaintext data m, a first operation is performed on the plaintext data m based on a key to obtain a first intermediate value x, and the first intermediate value x has a data structure that satisfies additive homomorphism. Then, the first intermediate value x is divided into η segments to obtain an array x′ containing η elements, and the elements in the array x′ are permuted according to the permutation rule π to obtain the ciphertext c of the plaintext data m. When decrypting the ciphertext c, the elements in the ciphertext c are reversely permuted according to the permutation rule π to obtain the array x′. Then, the η elements are spliced ​​according to the order of the elements in the array x′ to form a first intermediate value x, and an inverse operation related to the first operation is performed on the first intermediate value x based on the key, and the plaintext data m of the ciphertext c is determined from the obtained operation result. The homomorphic algorithm is implemented based on symmetric encryption and can be used in the field of data circulation.

The invention provides a parameterized Reed-Solomon code unified decoding method and device and a medium, and relates to the technical field of forward error correction. In order to solve the problems of complex hardware implementation and high resource consumption of the existing configurable decoder, the method configures decoding steps according to a first code pattern parameter representing the number of check symbols and a second code pattern parameter representing the truncation characteristic. The decoding step comprises the following steps: calculating a syndrome; solving the key equation by adopting a recombined non-inverse algorithm to obtain an error position polynomial and an error value polynomial; and error positioning, error value calculation and error correction are carried out. By adopting the non-inverse algorithm, complex Galois field inversion operation is avoided, hardware implementation is remarkably simplified, resource consumption is reduced, and efficient and flexible unified decoding is achieved.

The invention relates to the field of electrical digital data processing, in particular to an elliptic curve batch scalar multiplication acceleration method based on optimized Jacobian coordinate transformation, which comprises the following steps: generating a scalar set K to be processed and an elliptic curve point set P; performing batch scalar multiplication on K and P by using a Jacobian coordinate system; z coordinates of all points in the calculation result set are extracted, a Z coordinate set is constructed, and a multiplication tree is constructed according to the Z coordinate set; performing modular inverse operation on the root node value of the multiplication tree to obtain a modular inverse element of the root node, and constructing an inverse element tree from top to bottom based on the modular inverse element of the root node; performing batch conversion on the Jacobian coordinates based on leaf node values in the inverse element tree, and converting a calculation result set from the Jacobian coordinates to affine coordinates; according to the method, n times of modular inverse operation is optimized into one time of modular inverse operation and 3n-3 times of modular multiplication operation, so that the overall elliptic curve batch scalar multiplication efficiency is remarkably improved, and the calculation overhead of an elliptic curve cryptographic scheme is reduced.

The method and device for faster Reed-Solomon error decoding used a new approach—instead of calculating syndromes in a received signal in the traditional way to determine initially the coefficients of syndromes expansion into series of basic K linear-independent polynomials (called the basic group) of the certain powers belonging to the pre-determined set of powers. After that the syndromes which are necessary for accomplishing the stage 2—determination of the error positions—are calculated with the obtained coefficients, and the erasures and errors magnitudes on the step 3 are calculated through vector-matrix multiplication of a vector of the mentioned coefficients by the inverse of the conversion matrix (from the mentioned polynomials of the given and found on the stage 2 powers into the polynomials of the pre-determined set of powers).Use of lesser number of necessary computations is achieved by using the remarkable properties of the conversion matrices obtained by the proper division of all n available powers into (n+1) / K certain groups with K powers in each. The K−1 obtained conversion matrices belong to the so called Latin Squares with their entries belonging to the limited alphabet of only K symbols. Due to that the efficient procedures for doing vector-matrix multiplications necessary for the mentioned operation of finding syndromes as well as inverting the conversion matrix have been developed. As a result the number of arithmetic operations for syndromes calculation and matrix inversion in comparison to the most advanced methods can be greatly reduced. In addition the approach allows for greater concurrency and using parallel processors while the known solutions are operated on scalars that contributes to further encoding speed up. The task has been completely solved for the case when n+1=K2=22q, q—an integer, among them it covers the cases of R-S code (255,239), (1023,991), (15,11), (63,55). There for the step 1 the number of necessary multiplications can be reduced in K / 2 times, while the additions number remains the same. As for the step 3 for K=4 the method overpasses the known one almost 2 times in the number of the multiplications, for K=8 in 7 / 6 times and for K=16 more-less the same, with further K increase it is going to lose to the known methods.

The invention discloses a discrete period Riccati equation solving method based on non-inverse iteration and newest estimation information, which comprises the following steps of: firstly, converting an original equation into an equation with only one inversion operation through a Schur complementary theorem to reduce the inversion operation, and then carrying out non-inverse iteration on the inversion operation to further realize a non-inverse solving algorithm, so that the discrete period Riccati equation is obtained. The solving speed of the equation is improved, and the solving speed of the equation is further improved in combination with latest estimation information obtained through calculation in iterative calculation. According to the method, by optimizing the solving algorithm, the calculation complexity is reduced, the efficiency of solving the discrete period Riccati equation and the numerical stability are improved, and an effective solution is provided for solving the discrete period Riccati equation in the related fields.

The application discloses a quantum processor for implementing S-box substitution calculation, a plaintext encryption method, and relates to the technical field of quantum calculation. ‑1 ⊕c, wherein a represents one byte of plaintext, S(a) is a substitution calculation result, the quantum processor comprises a modular inverse operation circuit, a first multiplication operation circuit and a modular addition operation circuit; the modular inverse operation circuit acts on a first register, converts a modular inverse operation of an element a on a first finite field into a modular inverse operation of an element P on a first finite field combination field, a modular inverse operation result is stored in a second register, an initial quantum state of the first register is a quantum state corresponding to the element a, P = Ma, M is a conversion matrix from the first finite field to the first finite field combination field; the first multiplication operation circuit and the modular addition operation circuit act on the second register in sequence, and are used for performing Aa ‑1 ‑1 ⊕c calculation on the modular inverse operation result aThe S-box substitution calculation can be implemented by using a quantum computer.