A quantum processor for implementing s-box permutation calculations, plaintext encryption method

Abstract

The application discloses a quantum processor for implementing S-box substitution calculation, a plaintext encryption method, and relates to the technical field of quantum calculation. ‑1 ⊕c, wherein a represents one byte of plaintext, S(a) is a substitution calculation result, the quantum processor comprises a modular inverse operation circuit, a first multiplication operation circuit and a modular addition operation circuit; the modular inverse operation circuit acts on a first register, converts a modular inverse operation of an element a on a first finite field into a modular inverse operation of an element P on a first finite field combination field, a modular inverse operation result is stored in a second register, an initial quantum state of the first register is a quantum state corresponding to the element a, P = Ma, M is a conversion matrix from the first finite field to the first finite field combination field; the first multiplication operation circuit and the modular addition operation circuit act on the second register in sequence, and are used for performing Aa ‑1 ‑1 ⊕c calculation on the modular inverse operation result aThe S-box substitution calculation can be implemented by using a quantum computer.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of quantum computing, and particularly relates to a quantum processor for implementing S-box permutation calculation and a plaintext encryption method. BACKGROUND

[0002] A quantum computer is a kind of physical device that performs high-speed mathematical and logical operations, stores and processes quantum information in accordance with the laws of quantum mechanics. When a device processes and calculates quantum information and runs a quantum algorithm, it is a quantum computer. A quantum computer becomes a key technology under research because it has a higher efficiency in processing mathematical problems than a general computer, for example, can accelerate the time for cracking RSA keys from several hundred years to several hours.

[0003] The Advanced Encryption Standard (AES) is a kind of symmetric block cipher algorithm. The plaintext block length of AES is 128 bits (16 bytes), and the key length can be 128 bits (16 bytes), 192 bits (24 bytes) or 256 bits (32 bytes). According to the different key lengths, AES is divided into AES-128, AES-192 and AES-256.

[0004] The AES encryption system is also composed of multiple rounds of encryption. Except for the last round at the end, each round is composed of four steps: byte substitution, row shift, column confusion and round key addition. The last round only includes three steps of byte substitution, row shift and round key addition. At present, in the scene of implementing AES encryption on a classical computer, byte substitution is a simple table lookup operation. Specifically, for each byte of plaintext, an S-box table is used for table lookup substitution. A byte of plaintext consists of 8 bits, and the high 4 bits are used as the row value of the S-box table, and the low 4 bits are used as the column value of the S-box table. The corresponding substitution result is found in the S-box table, and the substitution of the plaintext byte is implemented to realize plaintext encryption.

[0005] However, in the implementation of AES encryption using a quantum computer, the above-mentioned byte substitution step cannot use S-box table lookup operation, and needs to use S-box permutation calculation formula based on the value representing the plaintext byte to calculate the substitution result, substitute the plaintext byte, and realize plaintext encryption. Therefore, how to implement the key step of S-box permutation calculation in AES encryption on a quantum computer is crucial. SUMMARY

[0006] The purpose of the present application is to provide a quantum processor for implementing S-box permutation calculation and a plaintext encryption method, which aims to implement the step of S-box permutation calculation in AES encryption in a quantum computer.

[0007] To achieve the above object, a first aspect of the embodiment of the present application provides a quantum processor for implementing S-box permutation calculation, the permutation calculation being wherein a represents one byte of plaintext, being an element on a first finite field, A is a matrix to be multiplied, c is a vector to be added modulo, S(a) is a permutation calculation result, the quantum processor comprising a modular inverse operation circuit, a first multiplication operation circuit and a modulo addition operation circuit;

[0008] The modular inverse operation circuit acts on a first register to convert the modular inverse operation of the element a on the first finite field into the modular inverse operation of the element P on the first finite field combination domain, the modular inverse operation result being stored in a second register, an initial quantum state of the first register being a quantum state corresponding to the element a, P = Ma, M being a conversion matrix from the first finite field to the first finite field combination domain;

[0009] The first multiplication operation circuit and the modulo addition operation circuit act on the second register in sequence to perform the calculation of -1 to obtain the permutation calculation result S(A).

[0010] In a possible implementation manner, the first multiplication operation circuit is obtained by the following manner:

[0011] performing matrix decomposition on the matrix to be multiplied, and constructing the multiplication operation circuit based on the matrix decomposition result, a CNOT gate and a SWAP gate.

[0012] In a possible implementation manner, the modulo addition operation circuit is constructed according to the element values of the vector c to be added modulo and an X gate, the element values of the vector c to be added modulo being 0 or 1.

[0013] In a possible implementation manner, the modular inverse operation circuit comprises a first multiplication inverse operation circuit, the first multiplication inverse operation circuit being configured to represent the element P on the first finite field combination domain as a multiplication inverse operation of an element b on a second finite field to obtain P -1 =(Ma) -1 , the second finite field being a subfield of the first finite field combination domain.

[0014] In a possible implementation manner, the modular inverse operation circuit further comprises a second multiplication operation circuit, the second multiplication operation circuit being constructed based on the matrix decomposition result of the conversion matrix M, a CNOT gate and a SWAP gate, and the second multiplication operation circuit being configured to implement the calculation of M(Ma) -1 =a -1 .

[0015] ​In a possible implementation, the first multiplicative inverse operation circuit includes a second multiplicative inverse operation circuit.

[0016] The second multiplicative inverse operation circuit is configured to convert an inverse operation of an element b in a second finite field into an inverse operation of an element Nb in a second finite field combination field, N being a conversion matrix from the second finite field to the second finite field combination field.

[0017] In a possible implementation, the second multiplicative inverse operation circuit includes a third multiplicative inverse operation circuit and a third multiplicative operation circuit.

[0018] The third multiplicative inverse operation circuit is configured to calculate an inverse operation result (Nb) -1 of the element Nb in the second finite field combination field, and store the result in a third register.

[0019] The third multiplicative operation circuit is constructed based on a matrix decomposition result of the conversion matrix N, a CNOT gate, and a SWAP gate, and the third multiplicative operation circuit operates on the third register to perform a multiplicative operation of the matrix N on the third register, to obtain an inverse operation result (Nb) -1 = b -1 .

[0020] In a second aspect, a plaintext encryption method is provided, and the method includes:

[0021] constructing the quantum processor as in the first aspect above;

[0022] inputting an element a representing any byte of a plaintext to be encrypted into the quantum processor, to obtain an S-box permutation calculation result output by the quantum processor;

[0023] replacing the element a representing any byte of the plaintext based on the S-box permutation calculation result, to obtain a ciphertext after encryption of the plaintext to be encrypted.

[0024] In a third aspect, a plaintext encryption apparatus is provided, and the apparatus includes:

[0025] a construction module configured to construct the quantum processor as in the first aspect above;

[0026] an input module configured to input an element a representing any byte of a plaintext to be encrypted into the quantum processor, to obtain an S-box permutation calculation result output by the quantum processor;

[0027] a replacement module configured to replace the element a representing any byte of the plaintext based on the S-box permutation calculation result, to obtain a ciphertext after encryption of the plaintext to be encrypted.

[0028] In a fourth aspect of the embodiments of the present application, a storage medium is provided, and the storage medium has a computer program stored therein, where the computer program is configured to execute the steps of the method in any one of the first aspect when running.

[0029] In a fifth aspect of the embodiments of the present application, an electronic device is provided, which includes a memory and a processor, where the memory has a computer program stored therein, and the processor is configured to execute the steps of the method in any one of the first aspect when running the computer program.

[0030] Based on the above technical solution, a quantum processor for implementing S-box permutation calculation is provided, and the permutation calculation is where a represents a byte of plaintext, which is an element on a first finite field, A is a matrix to be multiplied, c is a vector to be added, S(a) is a permutation calculation result, the quantum processor includes a modular inverse operation circuit, a first multiplication operation circuit and a modular addition operation circuit; the modular inverse operation circuit acts on a first register, and converts a modular inverse operation of an element a on a first finite field into a modular inverse operation of an element P on a first finite field combination field, a result of the modular inverse operation is stored in a second register, an initial quantum state of the first register is a quantum state corresponding to the element a, P = Ma, and M is a conversion matrix from the first finite field to the first finite field combination field; the first multiplication operation circuit and the modular addition operation circuit act on the second register in sequence, and are used for performing a multiplication operation on the modular inverse operation result a -1 to obtain the permutation calculation result S(a). Based on an S-box permutation calculation formula , a quantum circuit is designed, and the permutation calculation result can be obtained according to a plaintext byte a in a ciphertext matrix, so that the permutation calculation result is calculated by using the quantum circuit, the byte substitution operation is implemented, the byte substitution is implemented without searching an S-box table, and the step of the S-box permutation calculation in the AES encryption is implemented in the quantum computer. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a network block diagram of a plaintext encryption system according to an example embodiment.

[0032] Figure 2 is a quantum circuit schematic diagram of a quantum processor for implementing S-box permutation calculation according to an example embodiment.

[0033] Figure 3 is a schematic diagram of a first multiplication operation circuit according to an example embodiment.

[0034] Figure 4 is a schematic diagram of a modular addition operation circuit according to an example embodiment.​

[0035] Figure 5 is a schematic diagram of a second multiplication operation circuit according to an example embodiment.

[0036] Figure 6 is a schematic diagram of a first multiplication inverse operation circuit according to an example embodiment.

[0037] Figure 7 is a schematic diagram of a second multiplication inverse operation circuit according to an example embodiment.

[0038] Figure 8 is a schematic diagram of a variable modulus multiplication operation circuit according to an example embodiment.

[0039] Figure 9 is a schematic diagram of a constant modulus multiplication operation circuit according to an example embodiment.

[0040] Figure 10 is a schematic diagram of a third multiplication operation circuit according to an example embodiment.

[0041] Figure 11 is a task decomposition schematic diagram of S-box permutation calculation according to an example embodiment.

[0042] Figure 12 is a flow schematic diagram of a plaintext encryption method according to an example embodiment.

[0043] Figure 13 is a schematic diagram of a plaintext encryption apparatus according to an example embodiment.

[0044] Figure 14 is a block diagram of a computer device according to an example embodiment. DETAILED DESCRIPTION

[0045] The embodiments described below are exemplary and are intended to be illustrative of the present application, but are not to be construed as limiting the present application.

[0046] Figure 1 is a network block diagram of a plaintext encryption system according to an example embodiment. The plaintext encryption system can include a network 110, a server 120, a wireless device 130, a client 140, a storage 150, a classical computing unit 160, a quantum computing unit 170, and can also include additional storage, classical processors, quantum processors and other devices not shown.

[0047] The network 110 is a medium for providing communication links between various devices and computers connected together in a plaintext encryption system, including but not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof, and the connection mode can adopt a wired, wireless communication link or an optical cable, etc.

[0048] The server 120, the wireless device 130 and the client 140 are conventional data processing systems, which can contain data and have application programs or software tools for performing conventional computing processes. The client 140 can be a personal computer or a network computer, so the data can also be provided by the server 120. The wireless device 130 can be a smart phone, a tablet, a notebook computer, a smart wearable device, etc. The storage unit 150 can include a database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, quantum programs, etc.

[0049] The classical computing unit 160 (quantum computing unit 170) can include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data), which can be boot files, operating system images, and application programs 163 (application programs 173), which can be used to implement quantum algorithms compiled according to the plaintext encryption method provided by the embodiments of the present application.

[0050] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0051] It should be noted that a real quantum computer is a hybrid structure, which at least includes Figure 1 two parts: the classical computing unit 160 responsible for performing classical computation and control; and the quantum computing unit 170 responsible for running quantum programs and thus implementing quantum computation.

[0052] The classical computing unit 160 and the quantum computing unit 170 can be integrated in one device or distributed in two different devices. For example, a first device including the classical computing unit 160 runs a classical computer operating system, on which quantum application development tools and services are provided, and storage and network services required by quantum applications are also provided. A user develops a quantum program through the quantum application development tools and services thereon, and sends the quantum program to a second device including the quantum computing unit 170 through the network services thereon. The second device runs a quantum computer operating system, which parses the code of the quantum program into instructions that can be recognized and executed by the quantum processor 170, and the quantum processor 170 implements a quantum algorithm corresponding to the quantum program according to the instructions.

[0053] The computing unit of the classical processor 161 in the classical computing unit 160 is a CMOS tube based on a silicon chip, which is not limited by time and coherence, i.e., it is not limited by the use time and is available at any time. In addition, the number of such computing units in a silicon chip is sufficient, and the number of computing units in a classical processor 161 is currently thousands or even more. The number of computing units is sufficient and the computing logic of the CMOS tube is fixed, for example: AND logic. When operating with CMOS tubes, a large number of CMOS tubes are combined with limited logic functions to achieve the effect of operation.

[0054] The basic computing unit of the quantum processor 171 in the quantum computing unit 170 is a quantum bit, and the input of the quantum bit is limited by coherence and coherence time, i.e., the quantum bit is limited by the use time and is not available at any time. It is a key problem of quantum computing to fully use the quantum bit within the available use time of the quantum bit. In addition, the number of quantum bits in a quantum computer is one of the representative indicators of the performance of a quantum computer, and each quantum bit realizes computing functions through on-demand configured logic functions. Given the limited number of quantum bits and the diversified logic functions in the field of quantum computing, such as Hadamard gate (H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), X gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, etc. When quantum computing, a limited number of quantum bits are combined with a variety of logic functions to achieve the effect of operation.

[0055] Based on these differences, the design of classical logic function acting on CMOS tube and the design of quantum logic function acting on quantum bit are significantly and essentially different; the design of classical logic function acting on CMOS tube does not need to consider the individuality of CMOS tube, such as the individual identification of CMOS tube in the silicon chip, the position, the available time length of each CMOS tube, so the classical algorithm composed of classical logic function only expresses the operation relationship of the algorithm, and does not express the dependence of the algorithm on the individuality of CMOS tube.

[0056] And the quantum logic function acting on quantum bit needs to consider the individuality of quantum bit, such as the individual identification of quantum bit in the quantum chip, the position, the relationship with the surrounding quantum bits, and the available time length of each quantum bit. Therefore, the quantum algorithm composed of quantum logic function not only expresses the operation relationship of the algorithm, but also expresses the dependence of the algorithm on the individuality of quantum bit.

[0057] Examples:

[0058] Quantum algorithm one: H1, H2, CNOT(1,3), H3, CNOT(2,3);

[0059] Quantum algorithm two: H1, H2, CNOT(1,2), H3, CNOT(2,3);

[0060] Quantum algorithm one and quantum algorithm two use the method of quantum logic gate plus Arabic numerals to represent the quantum bits acted on by the quantum logic gate, wherein the Arabic numerals 1, 2, 3 can represent three quantum bits Q1, Q2, Q3 connected in sequence or quantum bits Q1, Q2, Q3 connected with each other;

[0061] The example explanation of the influence of quantum bit coherence time on quantum algorithm is as follows:

[0062] Define the execution time of a single quantum bit logic gate as t, and the execution time of two single quantum bit logic gates acting on adjacent bits as 2t; then:

[0063] When Q1, Q2, Q3 are connected with each other, the calculation of quantum algorithm one needs 6t, which is divided into four time periods, and the time length required in each time period is t, 2t, t, and 2t respectively, and the operation performed in each time period is: H1, H2; CNOT(1,3); H3; CNOT(2,3);

[0064] The calculation of quantum algorithm one needs 5t, which is divided into three time periods, and the time length required in each time period is t, 2t, and 2t respectively, and the operation performed in each time period is: H1, H2, H3; CNOT(1,2); CNOT(2,3);

[0065] When Q1, Q2, Q3 are connected in turn, the quantum algorithm one needs to be equivalent to: H1, H2; swap(1, 2), CNOT(2, 3), swap(1, 2); H3; CNOT(2, 3). The calculation of the equivalent quantum algorithm one needs 10t, and is divided into 4 time periods, and the time length needed in each time period is t, 6t, t, and 2t respectively. The operations performed in each time period are: H1, H2; swap(1, 2), CNOT(2, 3), swap(1, 2); H3; CNOT(2, 3).

[0066] Therefore, the design of the quantum logic function acting on the quantum bit (including the design of whether to use the quantum bit and the design of the efficiency of each quantum bit) is the key to improving the operation performance of the quantum computer, and needs special design, which is the uniqueness of the quantum algorithm based on the quantum logic function, and is significantly different from the essence of the classical algorithm based on the classical logic function. The above design for quantum bits is a technical problem that ordinary computing devices do not need to consider and face. The present application provides a quantum processor for implementing S-box permutation calculation, a plaintext encryption method, to implement the steps of S-box permutation calculation in AES encryption in a quantum computer.

[0067] The embodiment of the present application provides a quantum processor for implementing S-box permutation calculation, and the permutation calculation is Wherein, a represents a byte of plaintext, which is an element in a first finite field, A is a matrix to be multiplied, c is a vector to be mod-added, S(a) is a permutation calculation result, and the quantum processor comprises a modular inverse operation circuit, a first multiplication operation circuit and a modular addition operation circuit.

[0068] The modular inverse operation circuit acts on the first register, and converts the modular inverse operation of the element a in the first finite field into the modular inverse operation of the element P in the first finite field combination field, and the modular inverse operation result is stored in the second register. The initial quantum state of the first register is the quantum state corresponding to the element a, and P = Ma, M is a conversion matrix from the first finite field to the first finite field combination field.

[0069] The first multiplication operation circuit and the modular addition operation circuit act on the second register in turn, and are used for calculating The permutation calculation result S(a) is obtained.

[0070] In the embodiment of the present application, the permutation calculation is Wherein, the matrix to be multiplied A is an 8-order matrix, and the vector to be mod-added c is an 8-order vector. It can be seen that the S-box permutation calculation includes the matrix modular multiplication operation about the matrix to be multiplied A, the vector modular addition operation about the vector to be mod-added c, and the operation about a in the finite field The inverse operation of multiplication.

[0071] Therefore, permutation calculations are implemented based on quantum processors. The task can be broken down into three parts for implementation:

[0072] The first part is the design of the first multiplication circuit for implementing the modular multiplication of the matrix A to be multiplied.

[0073] Part Two, Design for Implementation The modular inverse operation circuit for the modular inverse operation of the element a.

[0074] The third part is the design of a modular addition circuit for implementing the modular addition operation of the vector c to be added.

[0075] One byte of plaintext is 8 bits long, meaning 'a' is an 8-bit binary number, and the first finite field is... The first finite field combination domain is a is an element in the first finite field, P is an element in the first finite field combination field, and the elements P and a in the first finite field satisfy the mapping relation P = Ma, where M is the transformation matrix from the first finite field to the first finite field combination field.

[0076] The second part of the design described above is used to implement the first finite field. The modular inverse circuit for the modular inverse operation of the element 'a'.

[0077] First Finite Field Combination domain with the first finite field Isomorphism, let the first finite field be... To the first finite field combinatorial domain If the transformation matrix is ​​M, then the following definition holds: Therefore, the first finite field The inverse multiplication operation of element a can be represented as the first finite field combinatorial field. The inverse operation of multiplication of the element P, i.e., a -1 =P -1 =M -1 (Ma) -1 .

[0078] like Figure 2 As shown, Figure 2 This application provides a schematic diagram of a quantum circuit for implementing S-box permutation computation using a quantum processor. Figure 2 The diagram shows M, and M -1 The modular inverse circuit is used to calculate a. -1Also shown are the first multiplication operation circuit A and the modulo addition operation circuit c, the input of the quantum circuit is a, and the output is S(a) of the second register.

[0079] Based on the above technical solution, a quantum processor for implementing S-box permutation calculation is provided, and the permutation calculation is Wherein, a represents a byte of plaintext, which is an element on a first finite field, A is a matrix to be multiplied, c is a vector to be added, S(a) is a permutation calculation result, the quantum processor comprises a modular inverse operation circuit, a first multiplication operation circuit and a modulo addition operation circuit; the modular inverse operation circuit acts on a first register, and converts a modular inverse operation of an element a on a first finite field into a modular inverse operation of an element P on a first finite field combination field, a result of the modular inverse operation is stored in a second register, an initial quantum state of the first register is a quantum state corresponding to the element a, P = Ma, M is a conversion matrix from the first finite field to the first finite field combination field; the first multiplication operation circuit and the modulo addition operation circuit act on the second register in sequence, and are used for calculating a permutation calculation result S(a) of the second register stored modular inverse operation result a -1 The calculation obtains the permutation calculation result S(a). Based on the S-box permutation calculation formula The quantum circuit is designed, the permutation calculation result can be obtained according to the plaintext byte a in the ciphertext matrix, so that the permutation calculation result is calculated by using the quantum circuit, the byte substitution operation can be realized, the byte substitution is realized without searching the S-box table, and the step of the S-box permutation calculation in the AES encryption is realized on the quantum computer.

[0080] In another embodiment of the present application, the first multiplication operation circuit in the above embodiment is obtained by the following method:

[0081] The matrix to be multiplied is decomposed into a lower triangular matrix and an upper triangular matrix, and the multiplication operation circuit is constructed based on the matrix decomposition result, a CNOT gate and a SWAP gate.

[0082] In the embodiment of the present application, matrix decomposition is a method of splitting a matrix into several more manageable components that have specific mathematical properties. The most common matrix decomposition techniques include LU decomposition, QR decomposition, and singular value decomposition (SVD).

[0083] LU decomposition: it decomposes a matrix into the product of a lower triangular matrix and an upper triangular matrix. For example, the matrix to be multiplied A can be decomposed into L x U, where L is a lower triangular matrix and U is an upper triangular matrix. This decomposition is very useful in solving linear equations.

[0084] QR decomposition: this method decomposes a matrix into the product of an orthogonal matrix Q and an upper triangular matrix R. It is particularly useful in calculating the eigenvalues and eigenvectors of a matrix.​

[0085] Singular Value Decomposition (SVD): SVD decomposes a matrix into the product of three matrices: an orthogonal matrix, a diagonal matrix, and another orthogonal matrix. SVD is particularly important in data compression and dimensionality reduction, such as in image processing applications.

[0086] Taking LU decomposition as an example, the matrix to be multiplied, A, can be decomposed into an upper triangular matrix (U), a lower triangular matrix (L), and a permutation matrix (P). The specific steps are as follows:

[0087] Step 1: Construct an identity matrix P0 based on the given matrix A.

[0088] Step 2: Select the row containing the element with the largest absolute value in the first column of matrix A, and swap it with the first row to obtain a new matrix A1.

[0089] Step 3: Construct a lower triangular matrix L1 such that the element in the first column is the first column of A1 divided by the first element of A1.

[0090] Step 4: Construct an upper triangular matrix U1 such that the elements of the first row are the elements of the first row of A1.

[0091] Step 5: Update matrix A1 so that A1 = A1 - L1 * U1.

[0092] Step 6: Repeat steps 2-5 until you obtain the upper triangular matrix U and the lower triangular matrix L.

[0093] LU decomposition can be used in applications such as solving linear equations, calculating the determinant of a matrix, and finding the inverse matrix.

[0094] For example, the matrix A to be multiplied in the embodiments of this application can be defined as:

[0095]

[0096] After LU decomposition, the following matrix is ​​obtained:

[0097] Permutation matrix:

[0098] Upper triangular matrix:

[0099] Lower triangular matrix:

[0100] like Figure 3 As shown, Figure 3A schematic diagram of the first multiplication operation circuit A constructed according to the P matrix, the U matrix and the L matrix provided in the embodiments of the present application is shown in the following figure, the input of the first multiplication operation circuit A is an 8-order vector {x0, x1, x2, x3, x4, x5, x6, x7}, Figure 3 The quantum logic gate acting between x5, x6 and x6, x7 is a SWAP gate, and the rest of the quantum logic gates are CNOT gates.

[0101] By using the above scheme, the multiplication operation of the multiplication matrix A is realized by performing matrix decomposition on the multiplication matrix A, and using SWAP gates and CNOT gates to construct a quantum circuit according to the decomposition result.

[0102] In another embodiment of the present application, the modulo addition operation circuit of the third part is constructed according to the element values of the to-be-modulo-added vector c and X gates, and the element values of the to-be-modulo-added vector c are 0 or 1.

[0103] In the embodiments of the present application, the modulo addition operation circuit can be obtained by applying X gates to the corresponding quantum bits according to the element values of the to-be-modulo-added vector c.

[0104] For example, the to-be-modulo-added vector c can be defined as:

[0105]

[0106] Based on the elements of the to-be-modulo-added vector c, the modulo addition operation circuit can be constructed by X gates as shown in the following figure, Figure 4 Figure 4 The initial quantum state on the left side of the modulo addition operation circuit shown in the following figure is zero state, and the quantum state on the right side is the quantum state after the evolution of the X gate, and the modulo addition operation circuit includes X gates acting on the first, second, sixth and seventh quantum bits, and can realize the modulo addition operation of the to-be-modulo-added vector c.

[0107] In another embodiment of the present application, the modulo inverse operation circuit further includes a second multiplication operation circuit, the second multiplication operation circuit is constructed based on the matrix decomposition result of the conversion matrix M, CNOT gates and SWAP gates, and the second multiplication operation circuit is used to realize the calculation of M(Ma) -1 -1 .

[0108] In the embodiments of the present application, the conversion matrix M can be defined as:

[0109]

[0110] After matrix decomposition, the following matrix can be obtained:

[0111] ​​​

[0112]

[0113]

[0114] The specific method for performing matrix decomposition on the transformation matrix M is the same as the matrix decomposition method for the multiplicative matrix A in the above embodiments. Please refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0115] like Figure 5 As shown, Figure 5 The diagram shows the second multiplication circuit M constructed according to the above embodiment. Similar to the first multiplication circuit A, the input of the second multiplication circuit M is an 8th-order vector {x0, x1, x2, x3, x4, x5, x6, x7}. Among them, the gates acting between x1, x4, x3, x6, x2, x4, x5, x6 and x4, x5 are SWAP gates, and the remaining quantum logic gates are CNOT gates.

[0116] Using the embodiments of this application, the transformation matrix M from the first finite field to the combined field of the first finite field is obtained, and then a second multiplication circuit is designed based on the matrix decomposition result of the transformation matrix M to calculate M(Ma). -1 =a -1 .

[0117] In another embodiment of this application, the above-mentioned modular inverse operation circuit includes a first multiplication inverse operation circuit, which is used to represent an element P in the first finite field combination field as the inverse multiplication operation of an element b in the second finite field, to obtain P. -1 =(Ma) -1 The second finite field is a subfield of the combined field of the first finite fields.

[0118] In this embodiment of the application, calculating the inverse multiplication operation of element P on the first finite field combination field may still be quite complicated. The calculation of the inverse multiplication operation of element P on the first finite field combination field can be converted into the inverse multiplication operation of element b on the second finite field subfield.

[0119] Still taking the first finite field as The first finite field combination domain is For example, the subfield of the first finite field combinatorial field is: That is, the second finite field is

[0120] First finite field combination domain It is the second finite field The second extension of the domain, namely x 2 +x+λ is An irreducible polynomial on, wherein the constant term therefore An element P on a given surface can be generated by its subfields. The elements p0 and p1 on the array represent P, i.e., P = p0 + p1x. Then P -1 =(P 17 ) -1 P 16 =(P 17 ) -1 (p0+p1)+(P 17 ) -1 p1x, where

[0121] First finite field combination domain The elements on are derived from their subfields and the second finite field. The elements on the top are composed of P = Ma = p0 + p1x, where The inverse multiplication operation of element P can then be converted into the following calculation method:

[0122] P -1 =(P 17 ) -1 (p0+p1)+(P 17 ) -1 p1x, where, We can let b = P 17 .

[0123] Therefore, the first finite field combination domain The inverse operation of multiplication of the elements above can be transformed into the second finite field of its subfield. The inverse operation of multiplication of the previous element.

[0124] like Figure 6 As shown, Figure 6 This is a schematic diagram of a first multiplication inverse operation circuit provided in an embodiment of this application. Figure 2 The circuit for the first inverse multiplication operation is represented as follows: Figure 5 The inputs of the first inverse multiplication circuit shown are p0 and p1 in P = p0 + p1x, and the output is P. -1 =n0+n1x, where n0 and n1 are the first inverse multiplication circuit, which includes a constant modular multiplication circuit. Modular multiplication circuit Mul, and inverse multiplication circuit. And multiple CNOT gates.

[0125] The second multiplication inverse operation circuit in the above embodiment is described below. Constant modular multiplication circuit And the variable modulus multiplication operation circuit Mul, in another embodiment of the present application, the first multiplication inverse operation circuit includes a second multiplication inverse operation circuit;

[0126] The second multiplication inverse operation circuit is configured to convert the inverse operation of an element b in the second finite field into the inverse operation of an element Nb in a second finite field combination domain, N being a conversion matrix from the second finite field to the second finite field combination domain.

[0127] In the embodiment of the present application, for calculating the multiplication inverse operation of an element b in the second finite field, it is still possible to convert the multiplication inverse operation of the element b in the second finite field into the multiplication inverse operation of an element Nb in the second finite field combination domain.

[0128] Continuing the example in the above embodiment, the second finite field is GF(2^8) The second finite field combination domain is GF(2^8) The second finite field is GF(2^8) The second finite field combination domain is GF(2^8) isomorphic, there is a mapping matrix N, such that the element in the second finite field GF(2^8) can be mapped to the element in the second finite field combination domain GF(2^8) , that is, the element b in the second finite field GF(2^8) is mapped to the element Nb in the second finite field combination domain GF(2^8) under the action of N, so that b -1 =N(Nb) -1 , where

[0129]

[0130] As shown in FIG. 8, Figure 7 a second multiplication inverse operation circuit provided by an embodiment of the present application Figure 7 is a schematic diagram, the second multiplication inverse operation circuit Figure 7 shown in FIG. 8 The input of the second multiplication inverse operation circuit is an element b in the second finite field, and the second multiplication inverse operation circuit includes a third multiplication inverse operation circuit The third multiplication operation circuit N and N -1 .

[0131] The first multiplication inverse operation circuit further includes a variable modulus multiplication operation circuit and a constant modulus multiplication operation circuit;

[0132] The variable modulus multiplication operation circuit is configured to calculate (P 17 ) -1 (p0+p1) and (P 17 ) -1 p1;

[0133] The constant modular multiplication operation circuit is used for calculating p1={p10, p11, p12, p13}.

[0134] As shown in Figure 8 , Figure 8 a variable modular multiplication operation circuit Mul provided by an embodiment of the present application, Figure 8 the input variables of the variable modular multiplication schematic diagram shown are {f0, f1, f2, f3} and {g0, g1, g2, g3}, and the output variable is {fg0, fg1, fg2, fg3}, Figure 8 the variable modular multiplication operation circuit Mul shown is used for calculating (P 17 ) -1 (p0+p1) and (P 17 ) -1 p1 calculation, including XOR operation and AND operation, wherein the XOR operation is realized through a CNOT gate, and the AND operation is realized through a Toffoli gate.

[0135] As shown in Figure 9 , Figure 9 a constant modular multiplication operation circuit provided by an embodiment of the present application, the input of the constant modular multiplication operation circuit Figure 9 is p1={p 10 , p 11 , p 12 , p 13}, the constant modular multiplication operation circuit includes a CNOT gate acting on p 11 , p 12 , p 10 , p 11 and p 11 , p 13 , and a SWAP gate acting on p 10 , p 11 , p 12 , p 13 and p 10 , p 13 .

[0136] In another embodiment of the present application, the second multiplication inverse operation circuit includes a third multiplication inverse operation circuit and a third multiplication operation circuit;

[0137] The third multiplication inverse operation circuit is used for calculating the inverse operation result (Nb) -1 of an element Nb on

[0138] The third multiplication circuit is constructed based on the matrix decomposition result of the transformation matrix N, the CNOT gate, and the SWAP gate. The third multiplication circuit operates on the third register to perform matrix N multiplication operations on the third register, obtaining the inverse operation result N(Nb). -1 =b -1 .

[0139] Matrix N is defined as:

[0140]

[0141] After LU matrix decomposition, the following matrix is ​​obtained:

[0142]

[0143] The third multiplication circuit constructed based on the above P matrix, U matrix, and L matrix is ​​as follows: Figure 10 As shown, Figure 10 The inputs of the third multiplication circuit shown are x0, x1, x2, and x3, including a SWAP gate operating between x1 and x2, and eight CNOT gates.

[0144] like Figure 11 As shown, Figure 11 This is a task decomposition diagram of S-box permutation calculation provided in an embodiment of this application, with the first finite field as the... For example, S-box operations It can be decomposed into multiplication of the matrix A to be multiplied, and the first finite field. a on -1 The operation involves the addition of the first finite field to the vector C, where the modulus of the vector C to be added is modulo the operation. a on -1 The operation can be further decomposed into: matrix multiplication of M, and the first finite field combination field. (Ma)⁻¹ operation on; first finite field combinatorial field (Ma) -1 The operation can be decomposed into a second finite field. b on -1 Operations, Second Finite Field Modular multiplication of variables and second finite field Constant modular multiplication on; second finite field b on -1 The operation can be decomposed into a second finite field combinatorial field. Matrix multiplication operations on N and the combination of second finite fields (Nb) -1 Calculation.

[0145] The above embodiments continuously apply a to the first finite field.-1 The operation task is decomposed, and inverse operation is performed on the second finite field and the second finite field combination field. Compared with directly calculating a -1 , the calculation complexity can be reduced.

[0146] The plaintext encryption method provided in the embodiments of the present application is shown in the following. Figure 12 Figure 12 The flowchart of the plaintext encryption method provided in the embodiments of the present application is shown in the following. The method comprises the following steps.

[0147] S1201, constructing a quantum processor as described in the above embodiments.

[0148] S1202, inputting an element a representing any byte of the plaintext to be encrypted into the quantum processor, and obtaining a S-box permutation calculation result output by the quantum processor.

[0149] The length of one byte of the plaintext is 8 bits, that is, a is a binary number with a length of 8 bits. The input element a is encoded on a first register. The quantum processor comprises a modular inverse operation circuit, a first multiplication operation circuit and a modular addition operation circuit. The modular inverse operation circuit acts on the first register, and converts the modular inverse operation of the element a on the first finite field into the modular inverse operation of the element P on the first finite field combination field. The modular inverse operation result is stored in a second register. The initial quantum state of the first register is the quantum state corresponding to the element a. P = Ma, and M is a conversion matrix from the first finite field to the first finite field combination field.

[0150] The first multiplication operation circuit and the modular addition operation circuit act on the second register in sequence, and are used for performing calculation on the modular inverse operation result a -1 stored in the second register. , to obtain the permutation calculation result S(a).

[0151] The specific implementation manners of the modular inverse operation circuit, the first multiplication operation circuit and the modular addition operation circuit comprised in the quantum processor provided in the embodiments of the present application are described in the above embodiments, which will not be described herein.

[0152] S1203, replacing the element a representing any byte of the plaintext based on the S-box permutation calculation result, to obtain the ciphertext after encryption of the plaintext to be encrypted.

[0153] By inputting the element a representing any byte of the plaintext to be encrypted into the quantum processor, the S-box permutation calculation result output by the quantum processor is obtained, the plaintext byte is replaced using the permutation calculation result, the plaintext is encrypted, the S-box permutation calculation is realized using the quantum computer, the byte replacement using the S-box table lookup operation in the prior art is not needed, and the encryption efficiency of the plaintext is improved.​

[0154] Based on the same inventive concept, the embodiments of the present application also provide a plaintext encryption device, as shown in Figure 13 The device comprises:

[0155] A construction module 1301 is configured to construct the quantum processor according to the first aspect.

[0156] An input module 1302 is configured to input an element a representing any byte of plaintext to be encrypted into the quantum processor to obtain an S-box permutation calculation result output by the quantum processor.

[0157] A replacement module 1303 is configured to replace the element a representing any byte of plaintext based on the S-box permutation calculation result to obtain encrypted ciphertext of the plaintext to be encrypted.

[0158] The specific functions and effects of the plaintext encryption device can be explained in detail by referring to other embodiments of the present application, and will not be repeated here. Each module in the plaintext encryption device can be implemented by software, hardware, or a combination thereof. The modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0159] Please refer to Figure 14 The embodiments of the present application also provide a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the plaintext encryption method according to any of the embodiments of the present application when executing the computer program. Please refer to Figure 14 The computer device can be a classical computer. The computer device can also be a quantum computer.

[0160] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program. The computer program is executed by a computer to make the computer execute the plaintext encryption method according to any of the embodiments of the present application.

[0161] The embodiments of the present application also provide a computer program product comprising instructions, which are executed by a computer to make the computer execute the plaintext encryption method according to any of the embodiments of the present application.

[0162] It can be understood that the specific examples in the present application are only to help those skilled in the art better understand the embodiments of the present application, and not to limit the scope of the present application.

[0163] It can be understood that, in various embodiments in the present specification, the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments in the present specification.

[0164] It can be understood that the various embodiments described in the present specification can be implemented alone or in combination, and the embodiments in the present specification do not limit this.

[0165] Unless otherwise specified, all technical and scientific terms used in the embodiments of the present specification have the same meanings as understood by those skilled in the art of the technology of the present specification. The terms used in the present specification are only for the purpose of describing the specific embodiments and are not intended to limit the scope of the present specification. The term "and / or" used in the present specification includes any and all combinations of one or more of the related listed terms. The singular forms "a", "an" and "the" used in the embodiments of the present specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0166] It can be understood that the processor of the embodiments of the present specification can be an integrated circuit chip with signal processing capability. In the implementation process, each step of the above method embodiments can be completed by integrated logic circuits of hardware in the processor or instructions in the form of software. The processor described above can be a general processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component. The disclosed methods, steps and logic block diagrams in the embodiments of the present specification can be implemented or executed. The general processor can be a microprocessor or the processor can be any conventional processor. The steps of the method disclosed in conjunction with the embodiments of the present specification can be directly embodied as a hardware coding processor for execution, or a combination of hardware and software modules in the coding processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, or other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory and combines the hardware to complete the steps of the above method.

[0167] It is appreciated that the memory in the embodiments of the present specification can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Among them, the nonvolatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM). It should be noted that the memory of the system and method described herein is intended to include, but not limited to, these and any other suitable types of memory.

[0168] Those of ordinary skill in the art can be aware that, in combination with the embodiments disclosed in the present document, units and algorithm steps of each example described above can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present specification.

[0169] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0170] In several embodiments provided in the present specification, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are merely schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0171] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e. can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the present embodiment.

[0172] In addition, each functional unit in each embodiment of the present specification can be integrated in one processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit.

[0173] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present specification or the parts of the technical solutions that essentially contribute to the prior art can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in each embodiment of the present specification. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0174] The above is only a specific embodiment of the present specification, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present specification, which should be covered within the protection scope of the present specification. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A quantum processor for implementing S-box permutation calculations, characterized by, The substitution calculation is Wherein, a represents one byte of plaintext, is an element on the first finite field, A is a matrix to be multiplied, c is a vector to be added, S(a) is a substitution calculation result, and the quantum processor comprises a modulus inverse operation circuit, a first multiplication operation circuit and a modulus addition operation circuit. The modular inverse operation circuit acts on the first register to convert a modular inverse operation of an element a on a first finite field into a modular inverse operation of an element P on a first finite field combination domain, and the modular inverse operation result is stored in a second register, an initial quantum state of the first register is a quantum state corresponding to the element a, P = Ma, and M is a conversion matrix from the first finite field to the first finite field combination domain; The first multiplication operation circuit and the modulo addition operation circuit sequentially operate the second register, to obtain a modulo inverse operation result a -1 are performed are calculated, to obtain the permutation calculation result S(a).

2. The quantum processor of claim 1, wherein, The first multiplication operation circuit is obtained by the following way: The matrix multiplication circuit is obtained by performing matrix decomposition on the to-be-multiplied matrix and constructing the multiplication operation circuit based on a matrix decomposition result, a CNOT gate and a SWAP gate.

3. The quantum processor of claim 1, wherein, The modular addition operation circuit is constructed according to each element value of the to-be-modularly-added vector c and an X gate, and each element value of the to-be-modularly-added vector c is 0 or 1.

4. The quantum processor of claim 1, wherein, The modular inverse operation circuit includes a first multiplication inverse operation circuit configured to represent an element P on a first finite field combined domain as a multiplication inverse operation of an element b on a second finite field to obtain P -1 = (Ma) -1 , and the second finite field is a subfield of the first finite field combined domain.

5. The quantum processor of claim 4, wherein, The modular inverse operation circuit further comprises a second multiplication operation circuit, which is constructed based on a matrix decomposition result of the conversion matrix M, a CNOT gate and a SWAP gate, and is used to implement calculation M(Ma) -1 = a -1 .

6. The quantum processor of claim 4, wherein, The first multiplication inverse operation circuit includes a second multiplication inverse operation circuit; The second multiplication inverse operation circuit is used to convert an inverse operation of an element b on a second finite field into an inverse operation of an element Nb on a second finite field combination domain, and N is a conversion matrix from the second finite field to the second finite field combination domain.

7. The quantum processor of claim 6, wherein, The second multiplication inverse operation circuit includes a third multiplication inverse operation circuit and a third multiplication operation circuit. The third multiplication inverse operation circuit is used for calculating an inverse operation result (Nb) of an element Nb on a second finite field combined domain -1 and storing the result in the third register. The third multiplication operation circuit is constructed based on a matrix decomposition result of the conversion matrix N, a CNOT gate and a SWAP gate, and the third multiplication operation circuit acts on the third register to perform multiplication operation of the matrix N on the third register to obtain an inverse operation result N(Nb) -1 = b -1 .

8. A method of encrypting plaintext, characterized by The method comprises: constructing the quantum processor according to any one of claims 1-7; inputting an element a representing any byte of to-be-encrypted plaintext into the quantum processor to obtain a S-box permutation calculation result output by the quantum processor; replacing the element a representing any byte of plaintext based on the S-box permutation calculation result to obtain ciphertext after encryption of the to-be-encrypted plaintext.

9. A plaintext encryption apparatus characterized by comprising: The device comprises: a construction module configured to construct the quantum processor according to any one of claims 1-7; an input module configured to input an element a representing any byte of to-be-encrypted plaintext into the quantum processor to obtain a S-box permutation calculation result output by the quantum processor; a replacement module configured to replace the element a representing any byte of plaintext based on the S-box permutation calculation result to obtain ciphertext after encryption of the to-be-encrypted plaintext.

10. A storage medium, characterized by The storage medium stores a computer program, and the computer program is configured to execute the method of claim 8 when running. 11.An electronic device comprising a memory and a processor, the electronic device characterized by, The memory stores a computer program, and the processor is configured to execute the computer program to execute the method of claim 8.

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