11 results about "Path protection" patented technology

The invention provides a 2M non-framing double-path protection intelligent switching method and system based on redundancy check, and relates to the technical field of communication, and the method comprises the steps: obtaining double-path 2M non-framing code streams, carrying out the alignment processing, generating a check result through employing cyclic redundancy check, carrying out the statistics of error code feature vectors in a sliding time window, and constructing a link quality track. According to the method, the quality degradation early warning signal is extracted, the stage switching strategy is constructed based on the early warning signal, the switching time sequence is determined in combination with the neural network evaluator, link switching is executed, self-adaptive optimization of the switching strategy is achieved, and the intelligence and reliability of link switching are improved.

This invention relates to the field of industrial internet security technology, and discloses a method and system for evaluating industrial internet data security protection capabilities. The method includes acquiring network traffic logs and system response records; performing time-series correlation analysis and sequence causal relationship completion based on the logs and records to obtain a dynamic evolution sequence of attack behavior; constructing an attack path graph model and parsing the correlation structure based on the sequence to obtain an attack path correlation structure; identifying high-latency paths and calculating response time differences to obtain a set of high-latency paths; extracting time feature vectors and quantifying the similarity of protection effectiveness from this set to obtain a quantitative score for path protection effectiveness; combining the score and difference index to perform a comprehensive risk assessment of physical topology mapping and node cascade failure analysis to obtain the system's comprehensive protection weaknesses; and performing adaptive scenario reconstruction closed-loop verification based on the weaknesses. This method can achieve accurate evaluation and dynamic verification of system protection weaknesses in complex adversarial scenarios.

The utility model discloses a kind of multi-path protection signal control circuit, belong to the technical field of automation equipment protection circuit.The circuit is input by several protection sensor signals, and each signal is connected to N channel MOS field effect transistor through input resistance and load resistance, and MOS tube is connected to triode after cascading, and triode output end connects motor driver I O port, and 24V is simultaneously stabilized as 5V for sensor power supply using 78L05.The utility model solves the problem of insufficient motor controller I O port resources, high cost and low reliability in prior art, can be flexibly configured according to sensor type, reduces cost and assembly difficulty, and improves system reliability.

This invention provides a method and system for intelligent handover of 2M unframed dual-path protection based on redundancy check, relating to the field of communication technology. The method includes acquiring and aligning dual 2M unframed bitstreams, generating check results using cyclic redundancy check, statistically analyzing error feature vectors within a sliding time window, constructing a link quality trajectory, extracting quality degradation warning signals, constructing a phased handover strategy based on the warning signals, and determining the handover timing sequence and executing link handover using a neural network evaluator. This achieves adaptive optimization of the handover strategy, improving the intelligence and reliability of link handover.

The application relates to the technical field of optical communication, and provides a protection switching threshold setting method and device of an optical transmission system and a medium, the optical transmission system comprising a sending end, a working path, a protection path and a receiving end, signals of the sending end are combined by a wavelength division multiplexer, split into two paths by a splitter, and transmitted to a protection switch of the receiving end through the working path and the protection path; the method collects data of the optical transmission system in real time through a physical layer, and constructs a digital twin model of the optical transmission system; the digital twin model is used to simulate the deterioration of the working path and the protection path at an entry point, and an initial deterioration value and a deterioration step are set in advance; in the simulation process, the optical signal-to-noise ratios of all wave channels of the working path and the protection path are calculated according to the digital twin model, the working path deterioration value and the protection path deterioration value that make any wave channel reach the optical signal-to-noise ratio threshold are obtained, and the protection switching threshold is deployed to the protection switch and used for path selection.

The invention relates to the technical field of communication, and provides an SRv6 node protection method and device, electronic equipment and a storage medium. The method is applied to each segment routing SRv6 node based on IPv6, and comprises the following steps: determining whether a current segment identifier of a target message is reachable, and determining a backup flag bit corresponding to the current segment identifier based on the current segment identifier under the condition that the current segment identifier is not reachable; under the condition that the backup flag bit represents that backup exists in the current segment identifier, determining a backup segment identifier corresponding to the current segment identifier based on the target message; and replacing the current segment identifier of the target message based on the backup segment identifier, replacing the current destination address of the target message based on the backup segment identifier, and forwarding the replaced target message. Compared with an existing path protection method, the method has the advantages that redundant backup is carried out by taking the segment identifier as granularity, protection of node level and other finer granularity can be realized, and the resource utilization rate is improved. Compared with an existing node protection method, reliability protection is provided for the unreachable segment identifier, and the integrity of the service chain service is guaranteed.

The invention relates to a signal analog quantity conversion output circuit with multiple protection paths and a control method. The output circuit comprises a dimming panel, a control module, a PWM signal conversion module, a multi-path protection management module and a dimming load. The signal output end of the dimming panel is connected with the signal input end of the PWM signal conversion module, the signal output end of the PWM signal conversion module is connected with the signal input end of the multi-path protection management module, and the signal output end of the multi-path protection management module is connected with the signal input end of the dimming load; the enabling signal input end of the multi-path protection management module is connected with the enabling signal output end of the control module, the control module generates a corresponding path management strategy according to the electrical characteristics and the dimming characteristics, and the limitation of a traditional single protection path in complex dimming application is overcome through a multi-path protection mechanism. Therefore, the reliability and adaptability of the overall operation of the system are improved while the output precision matching performance is ensured.

The invention discloses a double-path protection approximate multiplier for neural network acceleration. According to the method, multiplication is decomposed into addition operation of an index and a mantissa on the basis of the McCheer logarithm principle, and the design comprises three parts, namely a decomposition unit, a parallel addition unit and a reconstruction unit; wherein the parallel addition unit comprises an index path and a mantissa path, the index path adopts an approximate triple modular redundancy addition structure, and high-reliability fault tolerance is realized through three parallel addition modules and a majority voter; and a mantissa path adopts a truncation self-detection adder structure, truncation calculation is performed on high effective bits, and fault detection and result switching are performed based on structural invariants, so that lightweight fault tolerance is realized. And the reconstruction unit combines the results of the exponential path and the mantissa path through a barrel-shaped shifter, and outputs an approximate product result. The area and power consumption can be remarkably reduced, high reliability and high efficiency are both achieved, and the method is suitable for scenes such as neural network acceleration and safety-critical calculation.

The invention discloses a chip power consumption optimization system based on a generative adversarial network, and the system comprises the following modules: a data preprocessing module which is used for obtaining and processing chip design data; the thermal sensing logic diagram generation module is used for generating a thermal sensing logic diagram based on the thermal sensing memory migration network; the graph deformation optimization module is used for calculating an edge weight of a logic connection edge and executing deformation iteration processing through an attractive repulsion driving deformation mechanism; the critical path protection module is used for generating a limited optimization circuit diagram based on a synaptic logic retention mechanism; the multi-target discrimination module is used for outputting a discrimination feedback result based on a multi-target discriminator; the constraint adjustment module is used for generating updated EDA design constraint data; and the rear-end optimization implementation module is used for importing the limited optimization circuit diagram and the updated constraint data into a rear-end physical design tool for wiring. According to the method, the thermal sensing memory migration network and deformation iterative optimization are fused, and the chip power consumption optimization layout is realized.

The invention relates to a cognitive frequency hopping sequence construction method and system with path protection, belongs to the technical field of communication, and solves the problem of low spectrum resource utilization rate in the prior art. The method comprises the following specific steps: performing cognitive processing on a radio environment to obtain a cognitive decision result of communication mode selection and spectrum allocation, and extracting equipment ID information corresponding to a communication mode, an available frequency slot number Q of spectrum allocation and a spectrum hole result; the equipment ID information is combined with system time TOD to serve as plaintext information PT; encrypting the plaintext information PT to generate a pseudorandom sequence CT; based on the pseudo-random sequence CT, generating a corresponding frequency hopping code in combination with an available frequency slot number Q, and obtaining a frequency hopping base sequence of a specified frequency slot number; and monitoring a frequency hopping code of the frequency hopping base sequence based on a frequency spectrum hole result, and generating a cognitive frequency hopping sequence. The cognitive radio technology is integrated into the design of the frequency hopping sequence, and efficient utilization of spectrum resources and avoidance of interference are achieved.

In one example, an apparatus comprises: a first switch and a second switch coupled between a fuse terminal and a ground terminal, the first switch having a first switch control terminal, the second switch having a second switch control terminal; and a driver circuit having a control input, a first control output, and a second control output, the control input coupled to the fuse terminal, the first control output coupled to the first switch control terminal, and the second control output coupled to the second switch control terminal.