Vertical MOSFET SRAM cell

a mosfet sram cell, vertical technology, applied in the field of mosfet sram cells, can solve the problems of significant risk of data loss, sensitivity of the cell, and undesirable alternative to providing external body contacts, and achieve the effect of no area penalty
US20070007601A1Inactive Publication Date: 2007-01-11HSU LOUIS L +3
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
HSU LOUIS L
Publication Date
2007-01-11
Estimated Expiration
Not applicable · inactive patent

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Abstract

A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.
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Description

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to MOSFET SRAM cells and more particularly to a method of manufacturing a Vertical MOSFET SRAM cell and the structure provided thereby.

[0003] 2. Description of Related Art

[0004] Use of vertical channel MOSFETs enables precise control of channel length, for high performance applications.

[0005] U.S. Pat. No. 6,477,080 of Noble for “Circuits and Methods for a Static Random Access Memory Using Vertical Transistors” describes a vertical SRAM device with floating bodies of the FET devices in the SRAM circuit. The patent also states as follows:

[0006] “The n-channel and p-channel transistors of memory cell . . . have gates that are formed of n+ and p+ polysilicon, respectively. The polysilicon gates in an inverter are coupled together with a gate contact that is formed of a refractory metal so as to provide a dual work function feature for desired surface channel characteristics in each transistor ...

Claims

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