Vertical MOSFET SRAM cell
a mosfet sram cell, vertical technology, applied in the field of mosfet sram cells, can solve the problems of significant risk of data loss, sensitivity of the cell, and undesirable alternative to providing external body contacts, and achieve the effect of no area penalty
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Benefits of technology
Problems solved by technology
Method used
Image
Examples
Embodiment Construction
[0043]FIG. 1A illustrates a structure made in accordance with the method of this invention comprising an SRAM cell circuit 10 including a cross-coupled latch device solely comprising vertical channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The entire cell circuit 10, including the pass gate transistors PG1 / PG2 and the cross-coupled inverters formed by four MOSFET transistors PD1, PD2, PU1 and PU2, occupies an area (including isolation) of 112 F2. Interconnection of the drains D2 / D5 and D3 / D4 of the cross-coupled pairs of MOSFET transistors PD1, PD2, PU1 and PU2 in the SRAM circuit is provided by lower level wiring M0 and studs which are borderless to the gate conductors. The next level of wiring M1, which is borderless to the lower level wiring M0, is used to cross-couple the inverters PD1, PD2, PU1 and PU2 and to connect their outputs to the pass gate MOSFETs PG1 and PG2 of the SRAM cell circuit 10.
[0044] However, the size of the SRAM device can be reduced to...
PUM
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com