157 results about "Low-dropout regulator" patented technology

The invention discloses a dual-redundancy servo controller and a main-standby autonomous switching method thereof, and belongs to the technical field of electric servo control. The controller comprises a host machine and a standby machine; each of the host and the standby machine comprises a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), a hardware ID (Identity) identification module, a motor power driving IPM (Intelligent Power Module) and a generator tripping instruction module which are in signal connection; the DSP and the FPGA are respectively connected with an LDO (Low Dropout Regulator) power module; the FPGA is in communication connection with the control system; the motor power driving IPM is connected with the execution mechanism; the DSP processors of the host and the standby machine are in signal connection; and the switching instruction modules of the host and the standby are in signal connection. The invention discloses a main / standby autonomous switching method for a dual-redundancy servo controller, which adopts a DSP and an FPGA to cooperatively detect and process faults, improves the fault detection rate by 5%, and reduces the possibility that the output of an IPM module is not turned off by 20% when a fault occurs; three heterogeneous redundant generator tripping modes of hardware generator tripping, serial port generator tripping and heartbeat generator tripping are adopted, and the reliability of main and standby independent generator tripping is improved by 20%.

The invention relates to the technical field of chip detection, and discloses a high-reliability power supply chip circuit fault detection system, which comprises a built-in self-test architecture integrated in a low dropout regulator chip, and the built-in self-test architecture is provided with a first test mode and a second test mode which are switched based on a mode switching control circuit. The detection module is used for detecting key performance parameters of an error amplifier sub-circuit in a low dropout linear regulator chip, the detection module is used for measuring the direct current loop gain, the offset voltage, the common mode rejection ratio and the power supply ripple rejection ratio of the amplifier in the first test mode, and the detection module is used for measuring the unity gain bandwidth of the amplifier in the second test mode. According to the invention, through the design of a built-in self-test architecture and two test modes, abnormal states such as differential circuit imbalance and feedback loop fault can be identified in a bare chip stage, chips with poor performance are rejected in advance, and the LDO chip is ensured to reach a ppb-magnitude high reliability standard.

The invention relates to the technical field of Internet of Things, in particular to a circuit for simultaneously converting UART (Universal Asynchronous Receiver / Transmitter) to multi-path different level communication, which comprises a double-USB input module, a power supply processing module, a USB-UART core conversion module and a multi-path level conversion module, the double-USB input module comprises an MINI-USB interface J6 and a USB-B interface J8, VBUS pins of the two interfaces are connected in parallel through a Schottky diode and then output to the power supply processing module, and data differential pair pins are connected in parallel and then connected to the USB-UART core conversion module; and the power supply processing module comprises an LDO (Low Dropout Regulator) voltage stabilizing chip and a filter capacitor, and is used for converting 5V voltage output by the double-USB input module into 3.3 V stable voltage. The circuit design that the UART is connected with various different levels for communication is adopted, the tool integration technology is achieved, the design that the two USB ports are connected in parallel is adopted, the compatibility of the USB data line can be effectively improved, the demands of customers are met, and the technical difficulty that one UART bus is connected with multiple USB ports is broken through.

A low dropout regulator includes output terminal circuit and amplifier. The output terminal circuit is configured to generate output voltage according to input voltage and is configured to generate feedback voltage according to the output voltage. The amplifier is configured to generate control voltage to the output terminal circuit according to reference voltage and the feedback voltage, so as to adjust the output voltage, wherein the amplifier includes input stage circuit, current mirror circuit and filter circuit. The input stage circuit is configured to receive the reference voltage and the feedback voltage to generate a differential output. The filter circuit is configured to filter the input voltage to generate dependent current related to noise of the input voltage on the current mirror circuit, wherein the current mirror circuit is configured to output the control voltage according to the differential output and the dependent current.

The invention relates to a method and a circuit system for regulating power supply by using a low dropout regulator, the method comprising: monitoring a voltage level by a power detector: detecting the voltage level according to a predetermined first voltage level as a high voltage and a second voltage level as a medium voltage, the high voltage being powered on first and the medium voltage being powered on later; performing a bias shift and a fixed bias mechanism according to the detected voltage level; adjusting the output voltage according to the feedback loop by using the actual output voltage of the source follower and the predetermined safety voltage as the reference; the bias voltage shifting mechanism is executed when the high voltage is detected during the initial power-on period of the high-voltage rail and comprises the steps of conducting the high-voltage protection circuit, reducing the actual bias voltage to counteract the required high bias voltage and applying the actual bias voltage to the feedback system; the fixed bias mechanism is performed when the high voltage is detected, including opening the overvoltage protection circuit, applying a fixed reference voltage to an actual gate of a source follower of the feedback system, so that the feedback system is instantaneously started together with the medium voltage when started.

The invention discloses an LDO (Low Dropout Regulator) with a load transient response enhancement circuit and electronic equipment, and belongs to the technical field of integrated circuits. The circuit comprises an error amplifier, a buffer, a power tube, a feedback circuit, a compensation circuit and an LTRE module. The output end EAO of the error amplifier is connected with the grid electrode of the power tube through the buffer, the error amplifier compares reference voltage with feedback voltage, an EAO signal adjusts the conduction degree of the power tube, and the output voltage of the LDO is kept stable; the compensation circuit comprises an NMOS tube and a capacitor. The grid of the NMOS tube is connected with the input end of the buffer, the drain is connected with one end of the capacitor, and the source is grounded; the other end of the capacitor is connected with the EAO; one end of a delay circuit in the LTRE module is connected with the input end of the buffer, and the other end of the delay circuit is connected with the grid electrode of the NMOS tube, so that the grid electrode voltage is delayed to rise when the buffer voltage rises. The circuit has the advantages of low working voltage, low voltage drop and low static power consumption, and the transient response can be enhanced when the load current is increased or decreased.

The multifunctional control circuit comprises an FPGA (Field Programmable Gate Array) logic module, an LDO (Low Dropout Regulator) power supply module and a superconducting quantum computing chip which are in communication connection in sequence, the FPGA logic module comprises an AWG waveform memory, an AWG waveform playing controller, a bypass SFDR cancellation module and an RFSoC digital-to-analog conversion module which are in communication connection in sequence along the signal transmission direction, wherein the output end of the RFSoC digital-to-analog conversion module is set as the output end of the FPGA logic module; the FPGA logic module further comprises a clock synchronization module, and the clock synchronization module inputs a clock signal to the RFSoC digital-to-analog conversion module. According to the invention, the XY microwave pulse, the DC Pulse pulse and the DC Offset DC voltage are unified to be generated in the same FPGA and RFSoC architecture, the bypass SFDR cancellation module is added to generate a cancellation signal opposite to the phase of a spurious component, and the method has the advantages of significantly reducing the main spurious component in an output channel and improving the effective signal purity.

A voltage regulation device includes: a first low-dropout (LDO) regulator, a second LDO regulator and a signal coupling circuit. The first LDO regulator is configured to receive an input voltage of the voltage regulation device and accordingly generate and stabilize an output voltage of the voltage regulation device. The second LDO regulator is coupled in parallel with the first LDO regulator, and configured to provide supplementary regulation to further stabilize the output voltage. The signal coupling circuit is coupled between the first LDO regulator and the second LDO regulator, configured to apply a voltage provided by second LDO regulator to the first LDO regulator, thereby modulating an operation of the first LDO regulator.

The invention relates to a regulator circuit, a low dropout regulator and a method for increasing power supply ripple suppression. A regulator circuit includes a first stage, a second stage, and a boost circuit. The first stage includes a reference input and a feedback input configured to receive feedback from an output of the regulator circuit. The second stage is coupled to the first stage. The second stage includes an output transistor configured to drive the output of the regulator circuit. The boost circuit includes a first transistor configured to generate a bias current based on an output current of the output transistor. The boost circuit also includes a current-to-voltage converter configured to generate a bias voltage based on the bias current, and a capacitive element coupled between the current-to-voltage converter and a node of the first stage.

A low dropout regulator (LDO) includes a bias circuit including a first transistor, a second transistor, and a bias resistor, where a gate of the second transistor is coupled to a drain of the first transistor, and a difference between gate-source voltages of the first transistor and the second transistor generates a bias current on the bias resistor, the bias circuit is further configured to generate a first bias voltage based on the bias current; the output stage circuit comprises a power transistor and a feedback circuit, and the output voltage of the low dropout regulator is output from the drain electrode of the power transistor; the feedback circuit is coupled between the grid electrode and the drain electrode of the power transistor and is configured to change the grid electrode voltage of the power transistor in the same direction according to the change of the output voltage; and the feedback circuit receives the first bias voltage and generates an output voltage based on the first bias voltage. Therefore, stable power supply voltage can be provided at low cost.

Technologies related to transient response of low dropout regulator (LDO) circuits are described. The LDO circuit has a lower standby output voltage and a greater active output voltage. When transitioning to the greater active output voltage, a wakeup circuit controls peak current between voltage supply and LDO output.

The invention provides an HUD self-locking and ultra-low power consumption standby current control circuit which comprises an automobile storage battery, an MCU, an automobile regulation level low dropout regulator LDO, an ignition signal detection circuit, a triode Q2 and a CANINH signal end, the automobile storage battery outputs 12V voltage to the input end of the LDO, the output end of the LDO is connected with the MCU so as to provide 3.3 V working voltage, the MCU is connected with the triode Q2, the ignition signal detection circuit is connected with the triode Q2, and the CANINH signal end is connected with the triode Q2. The input end of the ignition signal detection circuit is connected with an ignition signal IGN +, the output end of the ignition signal detection circuit is connected with the enabling end EN of the LDO, the CANINH signal end is connected with the enabling end EN of the LDO, the collector electrode of the triode Q2 is connected with the enabling end EN of the LDO, the base electrode of the triode Q2 is connected with the MCU-OFF / ON pin of the MCU through a base electrode current-limiting resistor, and the output end of the triode Q2 is connected with the MCU-OFF / ON pin of the MCU. The problem that an existing power supply control circuit cannot meet the self-locking requirement can be solved.

In described examples, a low dropout voltage regulator includes an input voltage terminal, a resistive element, first and second transistors, an output terminal, a differential amplifier, and first and second saturation prevention circuits. The resistive element is coupled between the input voltage terminal and a gate of the first transistor. The output terminal is coupled to the drain of the first transistor and the source of the second transistor. A first input of the differential amplifier receives a reference voltage, and a second input is coupled to the output terminal. The first saturation prevention circuit provides a first clamp current to the differential amplifier output if the gate-source voltage of the first transistor is less than a first threshold voltage. The second saturation prevention circuit provides a second clamp current to the differential amplifier output if the gate-source voltage of the second transistor is greater than a second threshold voltage.

This disclosure is directed to a hybrid low dropout voltage regulator circuit, hereinafter referred to as the LDO, including a flipped voltage follower (FVF), coarse grain voltage adjustment circuitry, and fine grain voltage adjustment circuitry. The LDO may provide an output voltage based on receiving a reference voltage. The flipped voltage follower may supply the output voltage to one or more other electronic circuits. The coarse grain voltage adjustment circuitry and the fine grain voltage adjustment circuitry may adjust the output voltage based on a desired voltage level. The LDO may use feedback signals, feedforward signals, or both to provide the output voltage.

The present invention proposes a timing controller comprising an eFuse block for generating a final setting value determined according to whether fusing or trimming is performed, and a method for selecting the final setting value. The timing controller comprising the eFuse block comprises: an analog signal transmission and reception unit which comprises a low dropout regulator, and receives a final setting value to adjust an operating condition of a function block installed therein; and an efuse block which selects the final setting value corresponding to a voltage level of an LDO output terminal, the final setting value being determined according to whether a fusing or trimming process for adjusting the voltage level of the LDO output terminal is performed.

The present disclosure describes various aspects of implementing a low-dropout regulator in a gate-all-around process. In some aspects, a low-dropout (LDO) regulator circuit includes an amplifier and a power transistor with a source terminal coupled to a power rail. The LDO circuit may also include protection circuitry configured to prevent devices of the circuit from exceeding inter-terminal voltage ratings, which may protect the devices from damage when the LDO circuit is active or inactive. In some implementations, the protection circuitry includes a transistor coupled in series with the power transistor, voltage sources that provide signals or bias at intermediate voltages below a voltage of the power rail, and other transistors that operate based on or apply the intermediate voltages to the devices of the circuit. By so doing, the LDO circuit can be implemented in advanced fabrication processes (e.g., gate-all-around) in which devices may have reduced inter-terminal voltage ratings.

The utility model provides a low dropout linear regulator which comprises a multi-output band-gap reference source, a filtering selection circuit and an adjusting output circuit, the multi-output band-gap reference source is used for outputting multiple paths of first reference voltage, and the filtering selection circuit can trigger on-off according to a received selection control signal. And the adjusting output circuit compares the second reference voltage with the output voltage and adjusts the output voltage, so that the output voltage is controlled to be the second reference voltage constantly, and constant-voltage output is realized. According to the low dropout linear regulator, the multi-output band-gap reference source, the filtering selection circuit and the adjusting output circuit are arranged, so that multi-gear adjustable, stable and low-noise direct-current voltage can be output, a high power supply rejection ratio is achieved, and the power supply requirements of different circuit modules or application scenes are met.

An integrated circuit includes a first temperature-sensitive device configured to generate a first voltage, a second temperature-sensitive device configured to generate a second voltage, and an output terminal configured to generate a reference voltage which is a summation of the first voltage and the second voltage. The first voltage monotonically increases with an absolute temperature. The second voltage monotonically decreases with the absolute temperature. In the integrated circuit, a low-dropout regulator has a first input connected to the output terminal and an output connected to the gate of a power regulating transistor. The channel of the power regulating transistor is connected between a first terminal configured to receive a first supply voltage and a second terminal configured to generate a second supply voltage.

The invention provides a low dropout regulator. The low dropout regulator comprises an amplifier circuit, an equalizer circuit, a compensation capacitor, a discharge circuit and a detection circuit. The amplifier circuit operates between a first supply voltage and a second supply voltage, and includes a differential input pair having a first stage input circuit and a second stage input circuit. The amplifier circuit is configured to generate an output voltage according to an input voltage and a reference voltage. The equalizer circuit is coupled between two intermediate nodes spliced by the first stage input circuit and the second stage input circuit, and is configured to be short-circuited under the control of a control signal. The discharge circuit is configured to be controlled by the control signal to lower the common mode voltage of the common end of the differential input pair. The detection circuit is configured to generate a control signal according to a node voltage of one of the two intermediate nodes.

The invention belongs to the technical field of integrated circuits, and particularly relates to a fast transient response off-chip capacitor-free low dropout regulator (LDO) circuit based on a flip voltage follower (FVF) architecture. Comprising an error amplifier, an FVF-stage circuit and a transient enhancement circuit, the negative end of the error amplifier is connected with reference voltage VREF, the positive end of the error amplifier is connected with feedback voltage VFB formed by voltage division of the output resistor through the feedback resistor, the output end of the error amplifier is connected with the FVF-level input end, the FVF-level output end of the error amplifier is connected with VOUT, a high-gain loop is formed, and the output precision and the load regulation rate of the LDO are improved. A fast loop is formed in the FVF-stage circuit, has the characteristics of low gain and high bandwidth, and can quickly feed back and suppress output voltage fluctuation; the transient enhancement circuit compares the VFB voltage and the VOUT voltage at the same time and feeds back the VFB voltage and the VOUT voltage to the grid electrode of the power tube, so that the overshoot and the undershoot of the output voltage are further suppressed. The circuit provided by the invention can be widely applied to a power supply management system, does not need an off-chip capacitor, reduces the system area, and has a better transient response characteristic.

Power amplifier circuitry is disclosed having an inverse Class-D amplifier functioning as a power amplifier and self-biasing circuitry generating gate bias voltages for switching type power transistors within the power amplifier. The self-biasing circuitry includes a low-dropout regulator that generates and applies a gate bias voltage in response to a feedback current scaled according to the power amplifier's operating current. A current-based digital-to-analog converter is configured to generate the reference current based on a received digital value. Additionally, a digital processor is configured to generate the digital value in response to the gate bias voltage. The power amplifier circuitry enhances performance and efficiency while ensuring precise control over power transistors'operation, offering advantages for various applications requiring radio frequency signal amplification.

A digital low-dropout regulator and a control method thereof are provided. The digital low-dropout regulator can include a power switch circuit, an error detector, and a control circuit coupled to the power switch circuit and the error detector. The power switch circuit can be configured to receive an input voltage to generate an output voltage, wherein a voltage difference between the input voltage and the output voltage is controlled by a switch control code. The error detector can be configured to generate an error code based on an error between the output voltage and a target voltage. The control circuit can be configured to determine a compensation based on the switch control code and the error code, and update the switch control code based on the compensation to cause the output voltage to approach the target voltage.

A low drop-out (LDO) regulator includes an NMOS transistor having one of a source and drain terminal configured to be coupled to a voltage supply and the other of the source and drain terminal coupled to the low drop out voltage regulator output. A gate driver for the LDO regulator includes a boost converter having a boost converter input configured to be coupled to a boost converter reference voltage, a boost converter output configured to output a boosted voltage greater than the boost converter reference voltage and the voltage supply; and a boost converter clock input configured to receive a clock signal. The gate driver further includes a notch filter having a notch filter input coupled to the boost converter output and a notch filter output coupled to the gate driver output.

The embodiment of the invention provides a low-dropout linear voltage regulator and a chip. The voltage regulator comprises an error amplifier, a target transistor, a target capacitor and a sampling unit, the error amplifier comprises a blocking element, the first end of the blocking element is connected with the grid electrode of the target transistor through the output end of the error amplifier, the second end of the blocking element is connected with the first end of the target capacitor, and the blocking element is used for receiving a constant voltage signal. The blocking element is a one-way conduction element under the action of the constant voltage signal; the source electrode of the target transistor is connected with a power supply, and the drain electrode of the target transistor is the output end of the voltage stabilizer; the second end of the target capacitor is connected with the drain electrode of the target transistor; and the sampling unit is connected with the drain electrode of the target transistor and the error amplifier, and inputs a feedback signal to the error amplifier according to the output voltage of the voltage stabilizer so as to control the voltage value of the output voltage of the voltage stabilizer to be within the target voltage range. According to the scheme, the transient response performance of the voltage stabilizer is optimized.

A low dropout regulator circuit with reduced overshoot and undershoot during transient state is discussed. The low dropout regulator circuit has a power device operating at a restive region, a first amplification stage and a second amplification stage. The first amplification stage amplifies a difference between a feedback voltage and a reference voltage to generate a positive signal and a negative signal. The feedback voltage is derived from an output voltage via a feedback resistor network. The second amplification stage amplifies a difference between the positive signal and a sum of a feed forward signal and the negative signal to generate an amplified signal. The feed forward signal is derived from an output voltage via a capacitor network.

The utility model provides a soft start circuit and a low dropout linear regulator, and the soft start circuit comprises a driving unit and a reference unit. The driving unit comprises a first capacitor, starts to charge or discharge the first capacitor in a power-on process, and generates a driving signal when the first capacitor reaches a first potential; the reference unit comprises a second capacitor, is controlled by the driving signal to start charging the second capacitor, and generates a reference signal when the second capacitor reaches a second potential; wherein the establishment speed of the driving signal is set by setting the charging time or the discharging time of the first capacitor, and the establishment speed of the reference signal is at least set based on the establishment speed. According to the low dropout linear regulator, the problem that in the prior art, the output power-on speed of the low dropout linear regulator is too fast is solved.

A charge-pump based low dropout (LDO) regulator is provided that overcomes latch-up issues. The LDO regulator is a high PSR low noise LDO regulator that uses a latch-up mitigated charge-pump voltage doubler which includes a N-type metal-oxide-semiconductor field-effect transistor (MOSFET), NMOS, pass transistor. This LDO regulator architecture may be used to provide a very low-noise supply regulated output voltage with high power supply rejection for an on-chip low jitter oscillator. Latch-up is mitigated using control circuitry and a power supply timing sequence. This scheme ensures that parasitic diodes associated with various transistors in the regulator are not forward biased.

A current measurement system for a digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, the output voltage of the digital LDO being dependent on a first DAC code signal, the current measurement system comprising a current determination unit configured to receive the first DAC code signal, and generate an output current signal using the first DAC code signal.

The invention discloses an optical IO core particle-oriented quick response digital low-dropout voltage stabilizer, which comprises a voltage difference calculation logic unit used for calculating a voltage difference between an output voltage of a power tube and a reference voltage; the parameter generation logic is used for acquiring an optimal algorithm tuning parameter of the system according to the genetic algorithm; the feedback logic is used for generating feedback control quantity of the voltage control loop according to PID tuning of the voltage error quantity; the first summator is used for summing and generating the total feedback control quantity of the voltage control loop; the feed-forward logic is used for generating a feed-forward control quantity of the current control loop; and the second summator is used for summing the number of the power switches turned on at the current moment t, the total feedback control quantity and the feedforward control quantity to obtain the number of the power switches turned on at the next moment t + 1 so as to control the states of the power switches in the power tube. The invention aims to realize active compensation of load current fluctuation before significant voltage drop and realize excellent voltage regulation performance.

A process for regulating power supply using a low-dropout regulator may include detecting voltage levels based on a predetermined first voltage level as high voltage and a second voltage level as medium voltage, wherein the high voltage is powered up followed by the medium voltage; a shifting bias mechanism when high voltage is detected during the initial power up of the high voltage rail, including turning on the overvoltage protection circuit, lowering actual bias voltage to counter back the required high bias voltage, and applying the actual bias voltage for a feedback system; performing the fix bias mechanism when medium voltage is detected, including turning off the overvoltage protection circuit and applying a fixed voltage reference to an actual pass gate of source follower for the feedback system enabling an instant startup together with the medium voltage when it powers up.