Low dropout regulator

Abstract

The invention discloses a low dropout regulator, which comprises an error amplifier, a buffer circuit, a P-channel metal oxide semiconductor (PMOS) regulation transistor, an N-channel metal oxide semiconductor (NMOS) push-pull tube, a voltage division feedback circuit, a compensation circuit and an output circuit, wherein the gate of the PMOS regulation transistor is connected with the output end of the buffer circuit, the source of the PMOS regulation transistor is connected with power voltage, and the drain of the PMOS regulation transistor is used as the output end of the low dropout regulator; the gate of the NMOS push-pull tube is connected with the output end of the error amplifier, the drain of the NMOS push-pull tube is connected with the drain of the PMOS regulation transistor, and the source of the NMOS push-pull tube is grounded; and the error amplifier, the compensation circuit, the buffer circuit, the PMOS regulation transistor, the voltage division feedback circuit and an output circuit form a main control loop, and the error amplifier, the compensation circuit, the NMOS push-pull tube, the voltage division feedback circuit and the output circuit form an auxiliary control loop. According to the low dropout regulator, the transient response of the regulator can be quickened, and the accuracy of output voltage can be improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a low-dropout linear regulator circuit. Background technique [0002] Low Dropout Regulator (LDO) is a step-down DC linear regulator. With the development of SOC technology, it is widely used in industries such as computers, communications, instrumentation, consumer electronics, and camera monitoring. . Although compared with the DC-DC switching voltage converter, the efficiency of the LDO is lower, but it has the advantages of fewer peripheral components, small ripple, low noise, small chip area, and simple circuit structure, so the LDO is used in power management chips. has always held a large proportion. [0003] With the improvement of integration, more and more LDOs are integrated into the SOC chip as a sub-module of the SOC (System on Chip, System on Chip) chip to supply power to a key module, and the powerful SOC chip integrates It is common to have multiple...

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Problems solved by technology

[0008] In general, in order to ensure that the output has sufficient driving capability, the size of the PMOS adjustment transistor MP is usually relatively large, and the large gate parasitic capacitance (usually tens of picofarads) brought by the large-size PMOS adjustment transistor MP will be significant. Slow down the charging and discharging speed of the parasitic capacitance in the intermediate buffer stage, thereby seriously reducing the transient response speed of the system

[0009] In addition, in order to ensure the accuracy of the output voltage Vo and high low-frequency PSRR (power supply rejection ratio), the error amplifier OP is required to have a high gain, and the high gain leads to a large impedance of the output node of the error amplifier OP, which seriously reduces the bandwidth of the system on the one hand. This reduces the transient response speed of the system, and on the other hand increases the difficulty of system compensation

[0010] Therefore, the traditional LDO voltage feedback loop is a slow feedback loop with multiple poles. When the load current IL has a large mutation, the output voltage Vo not only has tens or even hundreds of millivolts of undershoot and overshoot. charging voltage (overshoot), and it takes a long transition process to return to the steady-state value, which leads to low output accuracy and cannot provide clean and reliable output for some high-speed and high-performance SOCs (such as pixel arrays in monitoring chips) today. DC power supply

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