125 results about "Feedback capacitor" patented technology

The invention provides a front-end readout electronics circuit for a silicon PIN detector. The front-end readout electronics circuit solves the technical problems that an existing front-end readout circuit cannot meet the requirements for quick response, dynamic adjustment of the dynamic range and small nonlinearity error. The charge sensitive amplifier comprises a charge sensitive amplifier and a forming module connected with the charge sensitive amplifier, and the charge sensitive amplifier receives an analog charge signal of the silicon PIN detector and converts the analog charge signal into an analog voltage signal according to a certain gain; the gain is controlled by a feedback capacitor which is dynamically controlled by a register; the reset module is connected in parallel to two ends of the charge sensitive amplifier and is used for releasing the accumulated charge quantity of the charge sensitive amplifier; the forming module performs filtering forming on the analog voltage signal to obtain a Gaussian-like waveform; the forming module comprises a fast forming unit and a slow forming unit, and the fast forming unit is sequentially connected with a comparator and a digital-to-analog converter; the slow forming unit is sequentially connected with the sampling hold circuit, the digital control center module and the analog-to-digital converter. The method can be widely applied to the technical field of particle detection.

The invention provides a feedback compensation circuit for a switching power supply. The feedback compensation circuit comprises a reference voltage source, an error amplifier, a feedback capacitor, a sampling circuit, an optocoupler output circuit and a PWM control chip, output voltage is connected to the inverted input end of the error amplifier through the sampling circuit, the reference voltage source is connected to the in-phase input end of the error amplifier, and the output end of the error amplifier is connected to a feedback pin of the PWM control chip through the optocoupler output circuit. The sampling circuit comprises an upper sampling resistor, a lower sampling resistor, a second resistor and a second capacitor; the feedback capacitor is connected between the inverting input end and the output end of the error amplifier; by selecting feedback capacitors with different capacities, the low-frequency gain of a transfer function from output to control of the feedback compensation circuit is adjusted. According to the invention, the element parameter design process is greatly simplified, the controllability of low-frequency gain is enhanced, and the technical effects of easy parameter design and simple debugging are achieved.

The invention discloses a capacitor mismatch error shaping circuit and method suitable for a multi-bit quantization Sigma-Delta ADC, and belongs to the technical field of integrated circuits, and the capacitor mismatch error shaping circuit comprises a data weight averaging module which is used for adopting a data weight averaging technology for high-bit quantization code words, and correcting the high-bit quantization code words according to the data weight averaging technology; averaging the mismatch error of the capacitor corresponding to the high-order quantization code word to obtain an averaged high-order capacitor; and the mismatch error shaping module is used for taking the averaged high-order capacitance as a reference, adopting a mismatch error shaping technology, keeping low-order feedback of the current low-order quantization code word of the lower polar plate of the capacitive digital-to-analog converter during Sigma-Delta ADC sampling, and realizing subtraction operation between two adjacent low-order quantization code words. According to the invention, the error caused by the mismatch of the CDAC capacitor fed back by the multi-bit quantization Sigma-Delta ADC can be effectively suppressed, the linearity of the system is improved, and the circuit overhead is remarkably reduced.

The invention discloses a Kelvin source series connection type active gate drive circuit, and belongs to the technical field of power generation, power transformation or power distribution. The circuit is composed of a signal conditioning circuit, a bidirectional follower circuit, a feedback capacitor, a gate driver and a power supply circuit thereof, and a driving resistor. The signal conditioning circuit is provided with two input ports and two output ports, the two input ports are respectively connected with a power source electrode and a feedback capacitor of the switching device, and the two output ports are connected with an input port of the bidirectional follower circuit. The bidirectional follower circuit is provided with two input ports and a modulation output port, and the modulation output port is connected with a reference point of the gate driver and the power supply circuit of the gate driver. The output port of the gate driver and power supply circuit is connected with the gate of the switching device after being connected with the driving resistor. On the basis of common gate drive, low-delay and real-time feedback closed-loop active gate drive is realized by changing a circuit connection structure and utilizing reference point voltage modulation, and the purpose of reducing voltage and current overshoot of a power device is achieved.

A frequency multiplier includes an oscillator and a harmonic generator. The oscillator has a resonant cavity and a negative resistance unit. The negative resistance unit includes a feedback capacitor and a parasitic capacitor. The feedback capacitor and the parasitic capacitor collectively provide negative resistance for the resonant cavity. The harmonic generator is configured to generate a harmonic signal based on a fundamental frequency signal taken as input. The oscillator is electrically connected to the harmonic generator, and is configured to receive the harmonic signal, and to output an intrinsic signal with the resonant cavity. A frequency of the intrinsic signal is a multiple of a frequency of the fundamental frequency signal.

The invention relates to an MDAC circuit of a pipelined analog-to-digital converter. The technical problems that in the prior art, an assembly line ADC is large in stage number and large in delay are solved, and jitter signal injection is facilitated. According to the technical scheme, the circuit comprises a first sampling capacitor array, a second sampling capacitor array, a first feedback capacitor array, a second feedback capacitor array and an operational amplifier. According to the further technical scheme, the circuit further comprises a first bridge capacitor, a first correction capacitor array, a second bridge capacitor and a second correction capacitor array. According to the technical scheme, the operational amplifiers of the adjacent sub-conversion stages are shared, so that one operational amplifier is saved, and the overall power consumption of the ADC is effectively reduced. The single conversion stage can adopt high-resolution conversion processing, the serial stage number of the whole assembly line analog-to-digital converter is reduced, and the assembly line delay is reduced. The capacitors of two adjacent sub-conversion stages are shared, so that the number of the capacitors is reduced, and the layout area of an integrated circuit is reduced.

The invention provides an analog amplifier circuit based on capacitance feedback, which relates to the technical field of signal processing, and comprises a positive voltage local voltage stabilization module, an amplifier module, a bias module and a negative voltage local voltage stabilization module, the positive voltage local voltage stabilization module, the bias module and the negative voltage local voltage stabilization module are all connected with the amplifier module; the positive voltage local voltage stabilization module is used for providing a first stable power supply for the amplifier module; the amplifier module is used for receiving a to-be-amplified signal input externally, performing signal amplification on the to-be-amplified signal to obtain an amplified signal, and outputting the amplified signal; the signal amplification is realized based on a transistor and a feedback capacitor in the amplifier module; the bias module is used for providing first bias voltage for the amplifier module; the negative voltage local voltage stabilization module is used for providing a second stable power supply for the amplifier module. The driving requirement and energy consumption of the amplifier are reduced by adopting capacitance feedback, the energy efficiency of the amplifier circuit is improved, signal amplification is realized through the transistor, and the amplifier circuit with a small area is realized.

The invention discloses a multi-path instrumentation amplifier which comprises a low-frequency amplification circuit and a high-frequency amplification circuit which are coupled between a voltage input end and a voltage output end. The high-frequency amplification circuit comprises a first amplifier, a second amplifier, a first input resistor, a first input capacitor, a second input resistor, a second input capacitor, a first feedback capacitor and a second feedback capacitor. The reverse output end and the non-reverse output end of the first amplifier are respectively coupled with the non-reverse input end and the reverse input end of the second amplifier, and the non-reverse output end and the reverse output end of the second amplifier are coupled with the voltage output end. The first feedback capacitor is coupled between the voltage output terminal and the inverting input terminal of the first amplifier. The second feedback capacitor is coupled between the voltage output terminal and the non-inverting input terminal of the first amplifier.

The invention provides a high-fidelity neuron circuit based on a full-printed electrochemical transistor, which comprises an amplification unit, a reset OECT, a film capacitor element, a feedback capacitor element, a current input end, a voltage source VDD and a common grounding end GND, and is characterized in that a grid electrode of a first-stage OECT in the amplification unit is connected with one end of the film capacitor element and is connected with the current input end at a connection node; the drain electrode of the first-stage OECT is connected to one end of the corresponding resistor to form a first-stage inverter; an output node is formed at a connection node of the resistor and the drain electrode of the first-stage OECT; the output node is connected with the grid electrode of the next stage of OECT; the source electrode of each stage of OECT is connected with a common grounding end GND, and a voltage source pin VDD is connected with the other ends of the four resistors; one end of the feedback capacitor element is connected to the output node of the last-stage OECT; the grid electrode of the reset transistor is connected with the output node of the last-stage OECT, the source electrode of the reset transistor is connected to the input port of the amplification unit, the structure is remarkably simplified, and large-scale integration is facilitated.

The present application belongs to the field of MEMS devices, and specifically discloses a MEMS accelerometer, a seismic detector, and a preparation method. The sensitive unit of the accelerometer is prepared on SOI, and includes: an outer frame, a mass block, a spring structure, a pickup structure, a first feedback capacitor structure, and a second feedback capacitor structure; the spring structure is prepared on the first layer of SOI, and the first feedback capacitor structure and the second feedback capacitor structure are prepared on the third layer of SOI, and the first layer and the third layer are any combination of a substrate layer and a device layer; the first feedback capacitor structure and the second feedback capacitor structure are respectively arranged on the sensitive axis and the perpendicular sensitive axis of the mass block, and are variable area capacitors and variable spacing capacitors respectively; the pickup structure is arranged above the mass block on the first layer of SOI. Through this application, the area occupied by the MEMS accelerometer is reduced based on the SOI process, and the sensing signal and the feedback signal can be isolated through the insulating layer of SOI, thereby improving the detection accuracy of the accelerometer and regulating the linearity of the accelerometer feedback execution.

A touch sensing reading device includes an operation circuit and an adjustment circuit. The operation circuit includes a feedback capacitor, receives a sensing signal through a first input terminal, receives a driving signal through a second input terminal, and feedbacks an output signal via an output terminal through the feedback capacitor and the first input terminal. The adjustment circuit provides an adjustment signal to the first input terminal of the operation circuit, and adjusts the output signal. A first sub-signal in the adjustment signal is set based on the inverted signal of the driving signal. A second sub-signal in the adjustment signal is set based on the inverted signal of the sensing signal.

The invention relates to the technical field of communication equipment, and discloses a frequency hopping filter with a hopping transmission zero point, a hopping control method and communication equipment. At least one resonant inductor of an LC resonant circuit of the frequency hopping filter is connected with a radio frequency switch feedback capacitor array in parallel; the frequency of a transmission zero point at a higher harmonic of the frequency hopping filter is controlled by controlling the opening and closing of a channel where each feedback capacitor in the radio frequency switch feedback capacitor array is located, so that the frequency of the transmission zero point changes along with the center frequency of the frequency hopping filter; and finally, far-end suppression, relative bandwidth stability and frequency hopping accuracy in a wide frequency range are improved.

This invention relates to instrumentation amplifiers and biosignal acquisition methods, specifically to a capacitively coupled instrumentation amplifier and biosignal acquisition method. It solves the technical problems of poor accuracy and integrity of biosignals acquired by existing instrumentation amplifiers, as well as their large area. This invention employs an input impedance enhancement circuit to increase the input impedance, resulting in more complete biosignals. It also uses a transimpedance matching enhancement circuit to increase the matching degree between the output signal of the feedback loop and the differential output signal. Simultaneously, by reducing the feedback capacitor to increase the closed-loop gain and lower the requirement for the input capacitor, it not only reduces the area but also increases the input impedance, improving the accuracy and integrity of the acquired biosignals. The second-order DC electrode offset cancellation circuit uses a second-order low-pass filter to narrow the transition band, more effectively separating the DC electrode offset signal from the biosignal, eliminating the DC electrode offset problem during biosignal acquisition, and making the acquired biosignals more accurate.

This disclosure discloses a sensing circuit and a source driver including the sensing circuit, which can reduce the impact of panel load on the performance of the integrator and reduce the chip area by eliminating the feedback capacitor of the integrator. The sensing circuit can convert the input current received from the display panel into an output current with linearity and a current quantity less than the input current.

The invention provides a second-order noise shaping SAR ADC circuit and electronic equipment, and the circuit comprises a sampling and quantification module which is used for completing the sampling and quantification of an input signal of an nth conversion period when being controlled by a time sequence, and outputting a digital code and a residual signal; the integral amplifier is connected with the sampling quantization module and is used for accessing the residual signal under the control of a first time sequence signal, integrating the residual signal and storing an integration result in a group of feedback capacitors of the integral amplifier; and the integral amplifier is also used for accessing the voltage stored on the group of feedback capacitors under the control of a second time sequence signal so as to carry out secondary integration, and the output end of the integral amplifier is connected to the input coupling node of the sampling quantization module so as to provide correction voltage participating in the quantization process of the (n + 1) th conversion period. According to the invention, high energy efficiency and high-order noise shaping capability can be considered at the same time.

The utility model provides a built-in IEPE circuit used for a piezoelectric type shock wave pressure sensor, comprising a high gain amplifier, a feedback capacitor and a constant current source, the high gain amplifier is composed of an N channel enhanced field effect transistor, a P channel enhanced field effect transistor, a resistor R1, a resistor R2, a feedback resistor R3 and a resistor R4, the two ends of the high-gain amplifier are connected with the constant current source, the positive electrode of the constant current source is an output end, and the constant current source is connected to the P-channel enhanced field effect transistor; the piezoelectric sensor sensitive element is connected with the input end and receives a charge signal generated by the piezoelectric sensor sensitive element through the input end; the feedback capacitor is installed between the input end and the output end to form negative feedback to form a charge amplifying circuit, a small number of electronic components are used for constructing a complete IEPE circuit, and the charge amplifying circuit has the advantages of being high in integration level, small in size and high in anti-interference capacity and can be integrated in a sensor to amplify charge signals.

Logarithm (100) comprehensive an input amplifier (101), a logarithmic component (102), and a feedback capacitor (103) which is designed to stabilize the logarithm (100), characterized by the fact that the logarithm (100) comprises a switching device (110), and the feedback capacitance (103) is divided into a plurality of n partial feedback capacitances (103a, 103b, 103c) connected in parallel, wherein a first partial feedback capacitor (103a) is a permanently stabilizing component of the logarithm converter (100), and wherein a number of n-1 of the n partial feedback capacitors (103a, 103b, 103c) are switchable partial feedback capacitors (103b, 103c), wherein the n-1 partial feedback capacitors (103b, 103c) can be switched on separately as stabilizing components in addition to the first partial feedback capacitor (103a), and where the switching device (110) is configured to individually switch the n-1 switchable partial feedback capacitors (103b, 103c) depending on an input current (I Ph ) of the logarithm (100) to be automatically switched on or off and thus depending on the input current (I Ph ) of the logarithm (100) automatically increases or decreases an effective feedback capacity (103) with which the logarithm (100) is stabilized, wherein the effective feedback capacitance (103) corresponds to a sum of the first partial feedback capacitance (103a) and all switched-on switchable partial feedback capacitances (103b, 103c), and wherein the switching device (110) comprises • at least one reference current source (111, 111a, 111b), • at least one reference transistor (112, 112a, 112b), • at least one switching amplifier (113a, 113b), and • at least one switch (114a, 114b).

Circuit arrangement measuring at least one measurement capacitor having inverting amplifier with high open-circuit voltage gain, input connected to connection of at least one measurement capacitor and to connection of negative feedback capacitor, another connection of at least one measurement capacitor connected to a reference potential and another connection of negative feedback capacitor connected to output of inverting amplifier; rectifier circuit fed voltage at the output of inverting amplifier and generates at its output voltage corresponding to voltage at output of inverting amplifier; a holding capacitor buffering voltage supply of inverting amplifier and rectifier circuit, a supply voltage connection of inverting amplifier supplied with a periodic control voltage with respect to reference potential and other supply voltage connection of inverting amplifier supplied via a diode with external supply voltage, periodic control voltage generated by signal source having a control input via which level of periodic control voltage can be infinitely variably set and this control input connected to an output of a control device which compares voltage generated at output of rectifier circuit with a desired voltage and, depending on comparison, emits output signal fed to control input of signal source, until level of periodic control voltage fed to supply voltage connection of inverting amplifier reaches value at voltage generated at output of rectifier circuit matches desired voltage, if voltage present at output of rectifier circuit matches desired voltage, at least voltage present at output of control device is a measure for at least one measurement capacitor.

Disclosed are a pixel and a display device including the same. The pixel includes: a light emitting element; a constant current generating circuit for generating a constant current; the pulse generating circuit is used for generating a pulse signal; and an emission transistor providing a constant current to the light emitting element in response to the pulse signal. The pulse generating circuit includes: a plurality of inverters connected in series with each other, in which the plurality of inverters output a pulse signal at a pulse output node based on a voltage of a first node; and a feedback capacitor including a first electrode connected to the first node and a second electrode connected to the pulse output node.

The application provides a true rail-to-rail input and output reference voltage buffer circuit suitable for high-precision ADC, which alternately performs a sampling phase F1 and a holding phase F2 during operation; the circuit comprises a sampling capacitor C s During the sampling phase F1, the bottom plate tracks the input reference voltage, and the top plate is reset to the ground; a level shift capacitor C LVL During the sampling phase F1, the difference between the input reference voltage and the output common-mode voltage of a transconductance operational amplifier (OTA) is synchronously sampled, and during the holding phase F2, the output voltage is connected to the output end of the transconductance operational amplifier (OTA), so as to realize the expansion of the true rail-to-rail range of the output voltage; a feedback capacitor C f During the sampling phase F1, the charge is not cleared, and during the holding phase F2, the sampling capacitor C s is connected in parallel, and the output voltage is established through charge averaging; the switch network is used for controlling the connection state of the capacitors in the sampling phase F1 and the holding phase F2. The application embodiment can realize true rail-to-rail input and output and high effective input impedance.

An arrangement of a pulse-width controlled vector-matrix multiplication unit and a method for its operation are disclosed. The system includes an input block connected to word lines of a matrix formed from non-volatile adjustable capacitors, and output blocks including amplifiers with inverting inputs and feedback capacitors with parallel switches. A voltage ramp generator is coupled to the word lines via switches that are controlled by the input pulse width. The amplifier in the output block operates as a non-inverting amplifier in conjunction with the matrix capacitors. A second phase of operation involves a reference capacitor and a reverse voltage ramp generator connected to the inverting input of the amplifier. The arrangement can improve energy efficiency and analog computation accuracy by implementing a comparator design within a dual-ramp timing architecture.

The invention relates to a feed-forward mismatch error shaping successive approximation analog-to-digital converter and a mismatch error shaping method thereof. The analog-to-digital converter comprises a first CDACP module, a first CDACN module, a second CDACP module, a second CDACN module, a four-input dynamic comparator module and a digital logic module. The input ends of the first CDACP module, the first CDACN module, the second CDACP module and the second CDACN module are connected with input voltage, the output ends of the first CDACP module, the first CDACN module, the second CDACP module and the second CDACN module are connected with the input end of the four-input dynamic comparator module, and the output end of the four-input dynamic comparator module is connected with the digital logic module. According to the invention, feed-forward capacitor mismatch error shaping is provided on the basis of traditional feedback capacitor mismatch error shaping, and the method is suitable for a high-precision environment of lower-level board sampling.

A regulation circuit includes: an operational amplifier, a first regulation unit, a second regulation unit, a first resistor, and a second resistor. The input of the first regulation unit is adapted to receive a ramp signal, and the output of the first regulation unit is connected to the input of the second regulation unit and the negative input of the operational amplifier. The output of the second regulation unit is connected to the output of the operational amplifier and the first end of the first resistor. The second end of the first resistor is connected to the first end of the second resistor and the output of the regulation circuit. The second end of the second resistor is adapted to be grounded. The first regulation unit includes a sampling capacitor, and the second regulation unit includes a feedback capacitor and a first switch; alternatively, the first regulation unit includes a sampling resistor, and the second regulation unit includes a feedback resistor.

This invention relates to a biomedical front-end detection circuit with duty cycle adjustable positive feedback capacitor and a method for fixing the capacitance value of the positive feedback capacitor. The circuit includes a duty cycle adjustment signal generator, a fully differential gain circuit, a positive feedback capacitor loop, and a low-pass filter. The fully differential gain circuit amplifies physiological signals. The positive feedback capacitor loop is an array of positive feedback capacitors connected to the fully differential gain circuit, and the positive feedback capacitor array includes a high-order positive feedback capacitor and a low-order feedback capacitor. The low-pass filter circuit filters the high-frequency biological signals output by the fully differential gain circuit. The duty cycle adjustment signal generator generates a duty cycle adjustment signal and continuously adjusts the low-order feedback capacitor to generate the minimum equivalent capacitance value. The beneficial effect is that by adjusting the duty cycle of the positive feedback capacitor to obtain an adjustable minimum capacitance value, high gain and high input impedance calibration resolution are achieved.

Techniques are disclosed to instruct how a switched capacitor digital power amplifier (PA) is configured to operate using high supply voltage levels beyond twice the maximum voltage rating for any of the transistor terminals such as Vds / Vdg / Vsg. The digital PA has a topology that comprises a dual-feedback capacitive path that comprises a capacitive divider and a voltage stabilizing feedback path to selectively couple the capacitive divider to DC bias voltages.

The invention relates to a capacitance feedback type current detection amplifier circuit, which comprises an operational amplifier, a feedback capacitor, a load capacitor, a reset switch, a first capacitor, a second capacitor, a first change-over switch and a second change-over switch, reference voltage is input to the in-phase input end of the operational amplifier, the output end of the operational amplifier is connected with the second end of the feedback capacitor and the first end of the load capacitor, the reset switch is connected with the feedback capacitor in parallel, the second end of the load capacitor is grounded, and the second end of the first capacitor is grounded. The second end of the second capacitor is selectively connected to the in-phase input end of the operational amplifier or the first change-over switch through the second change-over switch, and the first end of the first capacitor is selectively connected to the output end of the operational amplifier or the second change-over switch through the first change-over switch. According to the invention, the influence of noise random sampling values on the circuit can be suppressed.

The invention relates to the field of charge amplifiers, in particular to a multi-gear multi-channel charge amplification device for a differential three-dimensional force detection mechanism. A multi-gear multi-channel charge amplification device for a differential three-dimensional force detection mechanism comprises a charge amplifier integrated circuit board electrically connected with the differential three-dimensional force detection mechanism, and the charge amplifier integrated circuit board is provided with a charge signal input interface, a power supply interface and at least three multi-gear charge amplifier units. The multi-gear charge amplifier unit comprises a precision operational amplifier chip and n adjustable amplification gears, and the on-off states of n feedback capacitors are switched through a 2n-bit patch dial switch to achieve gear switching. The method has the advantage of being higher in universality, can be used for cutting machining of various products, meets the requirements of different measurement ranges, and does not need to additionally add signal debugging equipment.

The embodiment of the invention discloses a capacitive coupling chopping instrument amplifier circuit and a ripple calibration method. The circuit comprises a first chopping switch, an input capacitor, a first resistor, a second resistor, a two-stage operational amplifier circuit, a feedback capacitor, a second chopping switch and a ripple calibration module, the two-stage operational amplifier circuit comprises a plurality of first transistors and a plurality of second transistors which are used for signal amplification; the control end of the first transistor is connected with the first input end of the two-stage operational amplifier circuit, and the control end of the second transistor is connected with the second input end of the two-stage operational amplifier circuit; the ripple calibration module is connected with the first output end and the second output end of the two-stage operational amplifier circuit, samples signals of the first output end and the second output end of the two-stage operational amplifier circuit, and controls the access number of the first transistor and the second transistor according to the sampled signals; ripple waves generated by the chopping instrument amplifier circuit are reduced. The problem that a capacitor coupling chopping instrument amplifier circuit generates ripples due to offset voltage is solved.

The invention belongs to the technical field of amplifiers. The invention provides a floating inverting amplifier circuit with high gain and wide swing. According to the embodiment of the invention, a first-stage amplifier of the multi-layer sleeve type FIA is cascaded with a second-stage amplifier (conventional FIA) serving as an output stage, and the input end and the output end of the output stage are connected through a first feedback network and a second feedback network to form a closed-loop negative feedback form. A feedback resistor and a feedback capacitor are connected in series to serve as a feedback network, and output stages are connected into a closed-loop negative feedback mode, so that the cascade connection stability of the first-stage amplifier and the second-stage amplifier of the multilayer sleeve type FIA can be effectively improved. While the advantages of low power consumption and high energy efficiency of full-dynamic design are kept, the problem that high gain and wide swing design of an existing floating inverting amplifier cannot be achieved at the same time is solved.

The present invention discloses an operational amplifier structure using dynamic compensation in a ΣΔ modulator switched capacitor integrator, comprising a reference voltage input terminal, a feedback DAC capacitor, a sampling capacitor, a signal input terminal, an integrating capacitor, a fully differential folded cascode two-stage operational amplifier, a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a sixth control switch, and a seventh control switch. The structure has low power consumption.