31 results about "Bicmos circuits" patented technology

Deep isolation trenches having sides and a bottom are formed in a semiconductor substrate. The sides and the bottom are coated with an electrically insulating material that delimits an empty cavity, and forms a plug to close the cavity. The sides of the trench are configured with a neck that determines the depth of the plug, and a first portion that tapers outwards from the neck as the distance from the bottom increases. Deep isolation trenches may be applied, in particular, to bipole and BiCMOS circuits.

The invention discloses a vertical parasitic type precision navigation processor (PNP) device in a bipolar complementary metal oxide semiconductor (BiCMOS) technology, which comprises a collector region, a base region, an emitter region, a counterfeit burying layer and a N-type polycrystalline silicon. The counterfeit burying layer is arranged at the bottom of shallow groove field oxygen at two sides of the collector region and transversely extends into an active area so as to be contacted with the collector region, and a collector electrode is led out due to the deep hole contact formed in the shallow groove field oxygen at the top of the counterfeit burying layer. The N-type polycrystalline silicon is formed at the upper part of the base region to be contacted with the base region, and a base electrode is lead out due to the metal contact on the N-type polycrystalline silicon. The invention further discloses a manufacture method of the vertical parasitic type PNP device in the BiCMOS technology. The device disclosed by the intention can be taken as an output device in a high-speed and high-grain BiCMOS circuit, so that one more device selection can be provided to a circuit, the area of the device can be effectively reduced, the electric resistance of the collector electrode of the PNP pipe can be reduced, and the performance of the device can be improved. The production costcan be reduced without needing an extra technical condition.

The invention discloses a vertical parasitic PNP device in the BiCMOS (bipolar complementary metal oxide semiconductor) process, which comprises a collector region, a base region, an emitter region, a buried layer and N-shaped polycrystalline silicon. The collector region is formed in a first active region, the buried layer is formed at the bottom of shallow trench field oxides on two sides of the collector region and transversely extends to enter the first active region and contact with the collector region, the collector region is connected with an adjacent second active region and an adjacent third active region through the buried layer, and collectors are led out by metallic contacts formed at the tops of the second active region and the third active region. The N-shaped polycrystalline silicon is formed on the upper portion of the base region and contacts with the base region, and bases are led out by metallic contacts formed on the N-shaped polycrystalline silicon. The inventionfurther discloses a manufacturing method for the vertical parasitic PNP device in the BiCMOS process. The vertical parasitic PNP device can be used as an output device in a high-speed and high-gain BiCMOS circuit so as to provide one more choice for the circuit, and the resistance of the collectors can be decreased and the performance of the devices is improved without increasing the area of the device.

The invention discloses a vertical parasitic type precision navigation processor (PNP) device in bipolar complementary metal-oxide-semiconductor transistor (BiCMOS) technology. The vertical parasitic type PNP device in the BiCMOS technology comprises a collector region, a base region, an emitter region and an artifact buried layer. The artifact buried layer is formed on the bottom of shallow groove field oxide on two sides of the collector region, expands horizontally into an active region and contacts with the collector region. A collector is led out by contacting with a deep hole which is formed in the shallow groove field oxide on the top of the artifact buried layer. The emitter region is constituted of a P type silicon epitaxy epitaxial layer which is formed on the upper portion of the base region, and the emitter region is placed on one side which deviates from the center of the active region. N type polycrystalline silicon which is placed on the other side of the active region is arranged at a leading-out end of the base region. The invention further discloses a manufacturing method of the vertical parasitic type PNP device in the BiCMOS technology. The vertical parasitic type PNP device in the BiCMOS technology can be used as an output device in a high speed and high gain (HG) BiCMOS circuit, and thus one more device option is supplied to circuits, the area of the device can be effectively reduced, the collector resistance of a PNP tube is decreased, and the performance of the device is improved.

The invention discloses a tri-strain tri-polycrystal-plane BiCMOS (Bipolar complementary metal oxide semiconductor) integrated device and a preparation method thereof. The method comprises the following steps: preparing an embedded layer on a substrate plate, growing N-type Si epitaxy, preparing a deep channel isolator, preparing a collecting electrode contact area, preparing a base area and a transmission area, and forming a SiGe HBT (Heterojunction bipolar transistor) device; etching deep channels in the active areas of an NMOS (N-channel metal oxide semiconductor) device and a PMOS (P-channel metal oxide semiconductor) device, selectively epitaxially growing the following layers in the channel: a P-type Si layer, a P-type SiGe gradient layer, a P-type SiGe layer, a P-type strain Si layer as the active area of the NMOS device, an N-type Si layer, an N-type strain SiGe layer, and an N-type Si cap layer as the active area of the PMOS device; preparing a virtual grid, performing MOS (Metal oxide semiconductor) device light doped source / drain (LDD) injection, preparing a spacer, and self-aligning to form an MOS device source / drain; and etching the virtual grid, and sedimentating an SiON grid dielectric layer and a W-TiN composite grid to form a CMOS structure, and finally forming a BiCMOS circuit. According to the method, a tensile strain Si with high electron mobility and a compressive strain SiGe with high hole mobility are fully utilized as the conductive channels of the NMOS device and the PMOS device respectively, thus the performances of a BiCMOS integrated circuit are effectively improved.

The invention discloses a vertical parasitic PNP (plug-and-play) triode in a BiCMOS (bipolar complementary metal oxide semiconductor) process, a collector region is formed in a first active area; a pseudo buried layer is formed at the bottom of a shallow groove field oxide, transversely extends, enters into the first active area and is in contact with the collector region; the connection between the collector region and the adjacent active area is realized through the pseudo buried layer, and a collector is led out by forming metal contact at the top of the adjacent active area. N type polysilicon is formed at the upper part of a base region and a base is led out. An emitter region comprises a P type ion-implanted layer and a P type polysilicon formed above the base region. The invention further discloses a manufacturing method of the vertical parasitic PNP triode in the BiCMOS process. The vertical parasitic PNP triode disclosed by the invention can be used as an output device in a high-speed and high-gain BiCMOS circuit, one more device choice is provided for a circuit, the resistance of the collector of the PNP triode can be reduced, the frequency performance of the device can be improved, a polysilicon emitter can improve the gain of the device, and the production cost can also be reduced.

The invention discloses a vertical parasitic PNP device in a BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor) process. The vertical parasitic PNP device comprises a collector region, a base region, an emitter region, a P type buried layer and N type polycrystalline silicon, wherein the buried layer is formed at a shallow trench filed oxide bottom surrounding the collector region and is in contact with the collector region through a deep hole formed at the top of the buried layer to lead out a collector electrode; the N type polycrystalline silicon is formed at the upper part of the base region and is used for leading out a base electrode; and the emitter region is composed of a P type shallow junction formed in the base region and P type polycrystalline silicon arranged above the base region. The invention also discloses a preparation method of the vertical parasitic PNP device in the BiCMOS process. The device disclosed by the invention can serve as an output device in a high-speed high-gain BiCMOS circuit, and therefore another device choice is provided for the circuit. According to the invention, the area of the device can be reduced effectively, the resistance of the collector electrode of a PNP transistor can be lowered, the frequency performance of the device can be improved and the gain of the device can be enhanced. No extra process condition is required in the preparation method disclosed by the invention, thereby reducing the production cost.