Vertically parasitic PNP device in germanium-silicon HBT (heterojunction bipolar transistor) process and fabrication method thereof

A technology of vertical parasitic and process conditions, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of large device area, device size reduction, large collector connection resistance, etc., and achieve high current amplification factor, Effect of increasing current gain and reducing area

Active Publication Date: 2012-04-11
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage is that the device area is large and the connection resistance of the collector is large
Since the extraction of the collector electrode in the prior art is realized through another active region adjacent to the collector region, and the other active region and the collector region need to be isolated by STI or other field oxygen, such This greatly limits the further reduction of the device size

Method used

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  • Vertically parasitic PNP device in germanium-silicon HBT (heterojunction bipolar transistor) process and fabrication method thereof
  • Vertically parasitic PNP device in germanium-silicon HBT (heterojunction bipolar transistor) process and fabrication method thereof
  • Vertically parasitic PNP device in germanium-silicon HBT (heterojunction bipolar transistor) process and fabrication method thereof

Examples

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Embodiment Construction

[0030] like figure 1 Shown is a schematic diagram of the structure of a vertical parasitic PNP device in the silicon germanium HBT process of the embodiment of the present invention. The vertical parasitic PNP device in the silicon germanium HBT process of the embodiment of the present invention is formed on a P-type silicon substrate 1 and placed on the N-type deep well 2 is formed on the P-type silicon substrate 1, and the active region is isolated by shallow trench field oxygen 3, which is shallow trench isolation (STI). The vertical parasitic PNP device includes:

[0031] A collector region 7, composed of a P-type ion implantation region formed in the active region, the depth of the collector region 7 is greater than or equal to the depth of the bottom of the shallow trench field oxygen 3; the collector The P-type ion implantation area in area 7 is the P well in the CMOS process, and the implanted impurity is boron, which is implemented in two steps: the first implantation...

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Abstract

The invention discloses a vertically parasitic PNP device in a germanium-silicon HBT process. The vertically parasitic PNP device comprises a collector region, a base region, an emitter region, a P-type pseudo-buried layer and N-type polysilicon, wherein, the pseudo-buried layer is formed at the bottom of a shallow trench field oxide around the collector region and is in contact with the collector region, and a collector is led through a deep hole contact formed at the top of the pseudo-buried layer; the N-type polysilicon is formed at the upper part of the base region, and is used for leading out a base; and the emitter region consists of a P-type germanium-silicon epitaxial layer and P-type polysilicon which are formed on the base region. The invention also discloses a fabrication method of the vertically parasitic PNP device in the germanium-silicon HBT process. The vertically parasitic PNP device can be used as an output device in a high-speed and high-gain BiCMOS (bipolar complementary metal oxide semiconductor) circuit, thereby providing another device option for the circuit. The vertically parasitic PNP device has the beneficial effects that the area of the device is effectively decreased, the collector resistance of a PNP transistor is reduced, and the frequency performance of the device is enhanced. By adopting the fabrication method, additional process conditions are not required, thereby reducing the production cost.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a vertical parasitic PNP device in the silicon-germanium HBT process, and also relates to a method for manufacturing the vertical parasitic PNP device in the silicon-germanium HBT process. Background technique [0002] In RF applications, higher and higher device characteristic frequencies are required. In BiCMOS process technology, NPN transistors, especially silicon-germanium heterojunction transistors (HBT) or silicon-germanium carbon heterojunction transistors (SiGeC HBT) are good choices for UHF devices. And the SiGe process is basically compatible with the silicon process, so the silicon germanium HBT has become one of the mainstreams of UHF devices. In this context, the requirements for the output device are correspondingly increased, such as having a current gain coefficient and a cutoff frequency not less than 15. [0003] In the prior art,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/73H01L29/417H01L29/06H01L29/08H01L21/331
CPCH01L29/0821H01L29/66242H01L21/76237H01L29/7371H01L29/16
Inventor 陈帆陈雄斌
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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