Vertically parasitic PNP device in germanium-silicon HBT (heterojunction bipolar transistor) process and fabrication method thereof
A technology of vertical parasitic and process conditions, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of large device area, device size reduction, large collector connection resistance, etc., and achieve high current amplification factor, Effect of increasing current gain and reducing area
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[0030] like figure 1 Shown is a schematic diagram of the structure of a vertical parasitic PNP device in the silicon germanium HBT process of the embodiment of the present invention. The vertical parasitic PNP device in the silicon germanium HBT process of the embodiment of the present invention is formed on a P-type silicon substrate 1 and placed on the N-type deep well 2 is formed on the P-type silicon substrate 1, and the active region is isolated by shallow trench field oxygen 3, which is shallow trench isolation (STI). The vertical parasitic PNP device includes:
[0031] A collector region 7, composed of a P-type ion implantation region formed in the active region, the depth of the collector region 7 is greater than or equal to the depth of the bottom of the shallow trench field oxygen 3; the collector The P-type ion implantation area in area 7 is the P well in the CMOS process, and the implanted impurity is boron, which is implemented in two steps: the first implantation...
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