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Vertical parasitic PNP device in BiCMOS (bipolar complementary metal oxide semiconductor) process and manufacturing method

A vertical parasitic and process technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of large device area, shrinking device size, and large collector connection resistance, and achieve high current amplification factor, reduce resistance, the effect of reducing production costs

Active Publication Date: 2012-04-04
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage is that the device area is large and the connection resistance of the collector is large
Since the extraction of the collector electrode in the prior art is realized through another active region adjacent to the collector region, and the other active region and the collector region need to be isolated by STI or other field oxygen, such This greatly limits the further reduction of the device size

Method used

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  • Vertical parasitic PNP device in BiCMOS (bipolar complementary metal oxide semiconductor) process and manufacturing method
  • Vertical parasitic PNP device in BiCMOS (bipolar complementary metal oxide semiconductor) process and manufacturing method
  • Vertical parasitic PNP device in BiCMOS (bipolar complementary metal oxide semiconductor) process and manufacturing method

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Embodiment B

[0027] Such as figure 1 Shown is a schematic structural view of the vertical parasitic PNP device in the BiCMOS process of the embodiment of the present invention. The vertical parasitic PNP device in the BiCMOS process of the embodiment of the present invention is formed on a silicon substrate 1, and the active region is composed of a shallow trench field oxygen 3 isolation, wherein the active region comprises a plurality, the vertical parasitic PNP device comprises:

[0028] A collector region, a P-type ion implantation region 7 is formed in each of the active regions, and the depth of the P-type ion implantation region 7 in each of the active regions is greater than or equal to the depth of the bottom of the shallow groove field oxygen 3 and connected to each other, the collector region is composed of a P-type ion implantation region 7 formed in the first active region. The impurity implanted in the P-type ion implantation region 7 of each active region is boron, which is ...

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PUM

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Abstract

The invention discloses a vertical parasitic PNP device in the BiCMOS (bipolar complementary metal oxide semiconductor) process, which comprises a collector region, a base region, an emitter region, a buried layer and N-shaped polycrystalline silicon. The collector region is formed in a first active region, the buried layer is formed at the bottom of shallow trench field oxides on two sides of the collector region and transversely extends to enter the first active region and contact with the collector region, the collector region is connected with an adjacent second active region and an adjacent third active region through the buried layer, and collectors are led out by metallic contacts formed at the tops of the second active region and the third active region. The N-shaped polycrystalline silicon is formed on the upper portion of the base region and contacts with the base region, and bases are led out by metallic contacts formed on the N-shaped polycrystalline silicon. The inventionfurther discloses a manufacturing method for the vertical parasitic PNP device in the BiCMOS process. The vertical parasitic PNP device can be used as an output device in a high-speed and high-gain BiCMOS circuit so as to provide one more choice for the circuit, and the resistance of the collectors can be decreased and the performance of the devices is improved without increasing the area of the device.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a vertical parasitic PNP device in a BiCMOS process, and also relates to a method for manufacturing the vertical parasitic PNP device in the BiCMOS process. Background technique [0002] In RF applications, higher and higher device characteristic frequencies are required. In the BiCMOS process technology, NPN transistors, especially silicon-germanium heterojunction transistors (SiGe) or silicon-germanium carbon heterojunction transistors (SiGeC HBT) are good choices for UHF devices. And the SiGe process is basically compatible with the silicon process, so SiGe HBT has become one of the mainstreams of UHF devices. In this context, the requirements for the output device are correspondingly increased, such as having a certain current gain coefficient and cut-off frequency. [0003] In the prior art, the output device can adopt a vertical parasitic PNP ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/73H01L29/06H01L21/331
Inventor 刘冬华钱文生
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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