Vertical parasitic PNP device in BiCMOS technology and manufacturing method

A vertical parasitic and manufacturing method technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of device size reduction, large device area, and large collector connection resistance, etc., to achieve reduced area and high current The effect of magnification factor and reduction of production cost
CN102569370BActive Publication Date: 2014-12-10SHANGHAI HUAHONG GRACE SEMICON MFG CORP
3 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN ยท China
Patent Type
Patents(China)
Current Assignee / Owner
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
Publication Date
2014-12-10

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

The invention discloses a vertical parasitic PNP device in the BiCMOS technology, which includes a current collection region, a base region, an emitter region, a pseudo buried layer and an N-type polycrystalline silicon, wherein the pseudo buried layer is formed at shallow slot field oxide bottoms on the two sides of the current collection region, transversely extends to an active region, is contacted with the current collection region, and forms deep hole contact in the shallow slot field oxide at the top of the pseudo buried layer to lead out collector electrodes; the emitter region is formed in a P-type ion injection region at the upper part of the base region; and the N-type polycrystalline silicon is formed at the upper part of the base region, is contacted with the base region, and leads out base electrodes through metal contacts connected with the N-type polycrystalline silicon. The invention further discloses a manufacturing method for the vertical parasitic PNP device in the BiCMOS technology. The device provided by the invention can be used as an output device in a high-speed and high-gain BiCMOS circuit, can effectively reduce the area as well as the resistance of the collector electrodes of a PNP tube, and improve the performance. The method provided by the invention needs no additional technology condition, and can reduce the manufacturing cost.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a vertical parasitic PNP device in a BiCMOS process, and also relates to a method for manufacturing the vertical parasitic PNP device in the BiCMOS process. Background technique

[0002] In RF applications, higher and higher device characteristic frequencies are required. In the BiCMOS process technology, NPN transistors, especially silicon-germanium heterojunction transistors (SiGe) or silicon-germanium carbon heterojunction transistors (SiGeC HBT) are good choices for UHF devices. And the SiGe process is basically compatible with the silicon process, so SiGe HBT has become one of the mainstreams of UHF devices. In this context, the requirements for the output device are correspondingly increased, such as having a certain current gain coefficient and cut-off frequency.

[0003] In the prior art, the output device can adopt a vertical parasitic PNP ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More