225results about "Amplifiers with semiconductor devices only" patented technology

A circuit includes a high-side driver having a high-side slew control input, a high-side drive input and a high-side drive output. A low-side driver has a low-side slew control input, a low-side drive input and a low-side drive output. Drive control circuitry has a high-side drive control output, a low-side drive control output, and a slew control output. The high-side drive control output is coupled to the high-side drive input, the low-side drive control output is coupled to the low-side drive input. The slew control output is coupled to at least one of the high-side slew control input and the low-side slew control input, and the drive control circuitry is configured to provide a slew control signal at the slew control output. The high-side and / or low-side driver is configured to modulate a slew rate of a drive signal at a respective drive output thereof based on the slew control signal.

A reference system is provided for generating a clock signal with a tunable noise pedestal for driving a signal generator. The reference system includes a reference source configured to generate a reference signal and a multiplier chain, including a noise pedestal generator. The noise pedestal generator includes a noise pedestal attenuator configured to attenuate the reference signal to degrade a noise floor of the reference signal, a VGA configured to adjust the attenuated reference signal to a desired signal level, a bandpass filter configured to filter out excess noise from the adjusted reference signal to form a noise pedestal, and a switch arrangement configured to selectively input the reference signal to a first path including the noise pedestal attenuator and the VGA, and a second path bypassing the noise pedestal attenuator and the VGA. The clock signal includes the noise pedestal when the first path is selected.

An integrated circuit (IC), comprising: a first gain stage configured to apply a first gain to a first signal to generate a first amplified signal; a first converter configured to convert the first signal to a first output signal; a first output pin for outputting the first output signal; gain update circuitry configured to: output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, subsequently output a first external gain control signal to a second output pin of the IC, wherein output of the first external gain control signal is delayed relative to output of the first internal gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first gain stage and the first output pin.

An amplifier circuit includes a first input stage with a differential input transistor pair and a second gain stage having an output node coupled to a load. A node in the first gain stage is coupled to the output node in the second gain stage. A feedback line couples the output node to the control node of a first transistor of the differential input transistor pair. Current mirror circuitry is coupled to a current flow path through a further transistor in the second gain stage and includes a sensing node configured to produce a sensing signal indicative of the current supplied to the load. The sensing signal at the sensing node is directly fed back to the control node of the first transistor of the differential input transistor pair to provide a zero in the loop transfer function that is matched to and tracks and cancels out a load-dependent pole.

A virtual radio frequency (VRF) equalizer for an envelope tracking integrated circuit (ETIC) is disclosed. In one aspect, an ETIC provides envelope tracking (ET) for a barely Doherty (BD) power amplifier stage. The VRF equalizer includes circuitry that provides ripple cancelation that is caused by load modulation of the BD power amplifier stage. Additional circuitry is included to compensate for an amplifier within the ETIC. By canceling the ripple within the ETIC, the overall performance and efficiency of the BD power amplifier stage is improved, resulting in better performance of a transmitter in a wireless communication device.

Signal processing circuitry configured to receive an input signal and to output a processed output signal, wherein the signal processing circuitry is configured to: receive an indication of a temporal location of a transient in the input signal; and provide, in the processed output signal, a masking signal bridging the temporal location of the transient to mask the transient.

A current leakage mitigation circuit is provided. The circuit includes a charge storage circuit for receiving a control signal output, and a correction circuit connected to a bottom plate of the charge storage device. The control signal is output by an amplifier circuit connected to the current leakage mitigation circuit. The correction circuit samples the control signal, applies a filter to the control signal for to extracting a predefined frequency component, amplifies the filtered control signal, and applies the amplified control signal to the bottom plate of the current storage device.

A power electronic assembly is described which comprises an electrically insulating first substrate, which has a metallization layer on its top and bottom surfaces, and a semiconductor assembly mounted on the first substrate, which has at least one first connection that is thermally and electrically connected to at least one area of ​​the metallization layer of the first substrate facing the semiconductor assembly.Furthermore, the power electronic assembly comprises an electrically insulating second substrate mounted on the semiconductor assembly, which has a metallization layer on its upper and lower surfaces, wherein the semiconductor assembly has at least one second terminal that is thermally and electrically connected to at least one region of the metallization layer of the second substrate facing the semiconductor assembly, a first heat sink that is thermally connected to the metallization layer of the first substrate facing away from the semiconductor assembly, wherein the first heat sink has at least one first cooling channel through which coolant can flow, and a second heat sink that is thermally connected to the metallization layer of the second substrate facing away from the semiconductor assembly, wherein the second heat sink has at least one second cooling channel through which coolant can flow.Also disclosed is an electrical power converter for an industrial process arrangement, preferably a plasma process arrangement or a heating arrangement, in particular designed for generating an RF output power, comprising such a power electronic component.

A semiconductor device may include: a plurality of cell blocks, each cell block including: a high electron mobility transistor; and an amplification circuit configured to apply a gate signal to a gate electrode of the high electron mobility transistor. The semiconductor device also includes a signal generator configured to provide a pull-up signal and a pull-down signal to the amplification circuit of each of the plurality of cell blocks. The high electron mobility transistors of the plurality of cell blocks are connected in parallel.

The invention discloses a biasing circuit, an array substrate and detection equipment. The biasing circuit comprises a coupling module and an equivalent resistance module, the first end of the coupling module is connected with an input signal, and the second end of the coupling module serves as the output end of the biasing circuit; the first end of the equivalent resistance module is connected with the second end of the coupling module, the second end of the equivalent resistance module is connected with bias voltage, and the control end of the equivalent resistance module is connected with control voltage; wherein the equivalent resistance module comprises at least one transistor, and the control voltage is used for controlling the working state of the transistor in the equivalent resistance module and adjusting the resistance value of the transistor in the equivalent resistance module. According to the technical scheme, the use performance of the detection equipment is improved.

This semiconductor device is provided with: a first substrate (100) on which a first semiconductor element (10) is mounted, the first substrate (100) having a plurality of first front-surface-side pads disposed around the front surface; a second substrate (200) on which the first semiconductor element (20) is mounted, the second substrate (200) having a plurality of second front-surface-side pads disposed around the front surface; a third substrate (300) disposed between the first substrate (100) and the second substrate (200) so as to face the front surface of the first substrate (100) and the front surface of the second substrate (200), the third substrate (300) having a plurality of third rear-surface-side pads on the periphery of the rear surface, and a plurality of third front-surface-side pads on the periphery of the front surface; a plurality of first connection members (50) that electrically connect the corresponding first front-surface-side pads of the first substrate (100) and the corresponding third back-surface-side pads of the third substrate (300), respectively; a plurality of second connection members (70) that electrically connect the corresponding second front-surface-side pads of the second substrate (200) and the corresponding third front-surface-side pads of the third substrate (300); a first resin layer (400) that is in contact with the periphery of the front surface of the first substrate (100) and the periphery of the rear surface of the third substrate (300), and that has a hollow section; and a second resin layer (500) which is in contact with the periphery of the front surface of the second substrate (200) and the periphery of the back surface of the third substrate (300), and which has a hollow portion.

The invention discloses a cascading signal processing circuit based on separation components, and belongs to the technical field of signal processing circuits. The cascading signal processing circuit comprises a first circuit, a second circuit, a cascading convergence point J1, a third circuit and a cascading convergence point J2. The circuit is composed of three circuit parts which are all designed by using separation elements, based on the cost and flexible layout advantages of the separation elements, parameter matching under the requirements of signal anti-shake and signal latching flexibility is achieved, and the circuit can respond to high-speed abrupt change signals and can also adapt to anti-interference application of conventional level or pulse signals. On the premise that the circuit topology is not changed, grouping cascading of multiple intra-group signals and multi-path cascading of multiple paths of signals are supported, and meanwhile infinite cascading of interrupt signals corresponding to the multiple paths of signals and time division multiplexing summarizing access of the interrupt signals are achieved; and the effects of reducing the circuit cost, the PCB layout flexibility, the function and performance adaptation flexibility and the cascade expansibility are obvious.

The invention relates to a low-noise short-offset transient electromagnetic receiving conditioning circuit and a receiver. The conditioning circuit comprises a first power supply filter circuit, a second power supply filter circuit, an active filter circuit, a power frequency noise suppression circuit and a low-noise amplification circuit, the first power supply filter circuit and the second power supply filter circuit are respectively used for filtering a first power supply and a second power supply so as to reduce noise; the active filter circuit is used for filtering interference signals; the power frequency noise suppression circuit is used for filtering power frequency noise; the low-noise amplifying circuit comprises an input-stage amplifying circuit, an intermediate-stage amplifying circuit and an output-stage amplifying circuit. According to the technical scheme, various filter circuits are arranged, noise is filtered out, and noise reduction is facilitated.

A semiconductor device includes a substrate; a gate electrode, a source electrode, and a drain electrode, the gate electrode, the source electrode and the drain electrode being formed on the substrate; a plurality of nonconductive nanowires formed two-dimensionally on an upper surface of the substrate so as to extend perpendicularly to the upper surface of the substrate; an electrode pad formed at upper ends of the plurality of nanowires so as to have a gap between the electrode pad and the substrate, the electrode pad being supported by the plurality of nanowires; and an extraction electrode connecting the electrode pad and the gate electrode.

The utility model discloses a packaging carrier and a Doherty amplifier comprising the packaging carrier. The packaging carrier comprises a first input interface and a second input interface, a first output interface and a second output interface; a substrate; the first transistor is located on the substrate, the control end of the first transistor is coupled to the first input interface, and the output end of the first transistor is coupled to the first output interface; the second transistor is located on the substrate, the control end of the second transistor is coupled to the second input interface, the output end of the second transistor is coupled to the second output interface, the first transistor comprises a silicon carbide-based transistor, and the second transistor comprises a silicon-based transistor; and the bias circuit is configured to provide corresponding bias voltages for the first transistor and the second transistor.

The proximity sensor includes a detection coil, a metal head housing, and a power supply cable. The detection coil generates a detection current. The metal head housing houses the detection coil. The power supply cable has an electrical connection with the detection coil and is connected to the metal head housing. At least a part of an internal space of the metal head housing is filled with a filler so as to bury the detection coil. As the filler, an adhesive and an additive having a relative permittivity lower than that of the adhesive are mixed.

An amplifying circuit includes a transistor that includes an input terminal receiving a high frequency signal and an output terminal outputting an amplified high frequency signal, an inductor connected in parallel to the transistor between the input terminal and the output terminal, and a capacitor connected in parallel to the transistor and connected in series to the inductor between the input terminal and the output terminal.

A bias compensation circuit includes a detection circuit comprising a diode-connected transistor circuit having a first terminal for receiving a first current and a second terminal; and a first diode circuit having a first terminal for receiving a second current and a second terminal; wherein the detection circuit provides a first voltage level based on the diode-connected transistor circuit and provides a second voltage level based on the first diode circuit; a voltage-to-current conversion circuit coupled to the detection circuit for generating a first reference current based on the first voltage level and the second voltage level; and a bias circuit coupled to the voltage-to-current conversion circuit for receiving the first reference current to provide a bias level based on the first reference current.

The utility model provides a biasing circuit and an amplifier. The bias circuit comprises a programmable current source which generates bias current with adjustable magnitude based on a first control signal; the amplification transistor is used for receiving bias voltage; a transistor unit for an input transistor of the first current mirror; the transistor unit comprises a plurality of first transistors, and when the control ends of the first transistors receive bias current, and the first ends and the control ends of the first transistors are short-circuited and connected to an output node, the first transistors provide voltage for the output node; and the first switch units change the quantity of the bias current received by the control end of the first transistor and / or change the quantity of the output nodes connected to the first end of the first transistor based on the second control signal. Therefore, the adjusting range is further widened while the adjusting precision is guaranteed.

A display device includes a display panel including a pixels, a timing controller configured to generate output control information based on an output timing of image data to be written to the pixels, and a plurality of amplifiers configured to output a target data voltage corresponding to the image data to output channels connected to the pixels. Each of the plurality of amplifiers includes one or more transistors configured to apply a preset rising current or falling current to an output node connected to one of the channels to output the target data voltage, and a compensation capacitance adjuster configured to adjust compensation capacitance of the output node according to the output control information.

The invention discloses a phase noise adjustable crystal triode wide dynamic output amplifier circuit, including a triode collector amplifier narrowband passband circuit and a triode emitter follower drive circuit; the triode collector amplifier narrowband passband circuit includes an input matching unit, a triode amplifier unit and a first LC resonance unit; the triode emitter follower drive circuit includes a triode emitter follower unit and a second LC resonance unit. The invention has the following advantages and effects: having a greater linear dynamic output capability; realizing low phase noise large signal amplification; the input matching unit can reduce the reflection of the input circuit; the first LC resonance unit realizes narrowband high gain amplification; the triode emitter follower drive circuit realizes the conversion of the circuit low output impedance; the second LC resonance unit greatly improves the large signal emitter output capability, and improves the large signal output capability of the entire output circuit.

A display device includes a display panel including a pixels, a timing controller configured to generate output control information based on an output timing of image data to be written to the pixels, and a plurality of amplifiers configured to output a target data voltage corresponding to the image data to output channels connected to the pixels. Each of the plurality of amplifiers includes one or more transistors configured to apply a preset rising current or falling current to an output node connected to one of the channels to output the target data voltage, and a compensation capacitance adjuster configured to adjust compensation capacitance of the output node according to the output control information.

The present disclosure provides a semiconductor device. The semiconductor device includes a first transistor and a second transistor. The first transistor is configured to conduct in a first enable period. The second transistor is configured to conduct in a second enable period. The first transistor and the second transistor are coupled in series. The first enable period includes a first delay period, the second enable period and a second delay period that are arranged sequentially.

A system configured as part of an integrated circuit to block DC components from an amplifier comprising a matching network and an emitter follower circuit. The matching comprises an input configured to receive an input signal having a DC component. A voltage divider network comprises at least one resistor, and at least one capacitor. The network receives the signal and DC component and the voltage divider network blocks the DC component to generate a network output signal. The emitter follower (EF) circuit with EF devices configured to process the network output signal to generate an EF circuit output signal on an EF output. A biasing circuit generates a bias signal for the EF device. The bias signal has a value that is controlled by a bias control signal. Aias control signal generator compares the EF circuit output signal to a reference voltage, and generates the bias control signal.

An apparatus for removing noise due to a DC offset voltage from the frequency band of interest of a signal. Input noise errors are moved out of the band of interest by changing the noise gain of the system without placing a switch in the signal path. The resistance through which an input signal passes to the amplifier remains unchanged, but the noise gain is selectively changed by use of a single switch that inserts an additional resistance from a zero signal source in response to a switching signal, thus switching the amplifier between two states with different noise gains. The output signal may be passed through a sigma-delta modulator and an exclusive-or gate clocked at a duty cycle such that the signal gain of the amplifier is unchanged while the different noise gain states cancel out, thus relocating the input noise errors to harmonic frequencies of the switching signal.

The invention provides a rail-to-rail input and output source follower circuit and an instrumentation amplifier. The rail-to-rail input and output source follower circuit comprises a first following unit, a second following unit and a third following unit, wherein the first following unit at least comprises a first common drain source follower, a first flip source follower and a first compensation circuit; the second following unit at least comprises a second common drain source follower, a second flip source follower and a second compensation circuit. According to the invention, low output impedance under low power consumption is realized by using the turnover source follower, and close following between an input signal and an output signal is realized by combining the cascaded common drain source follower and the turnover source follower, so that a level transfer effect is formed; and meanwhile, rail-to-rail input and output are realized by utilizing the symmetrical arrangement of the first following unit and the second following unit and matching with the design of the compensating circuit.

This semiconductor device comprises: a substrate; a gate electrode, a source electrode and a drain electrode which are positioned on the substrate; a plurality of non-conductive nanowires which are arranged two-dimensionally on the top surface of the substrate so as to extend in a direction which is perpendicular to the top surface of the substrate; an electrode pad which is supported by the plurality of nanowires and is positioned at the top end of the plurality of nanowires in a manner such that a gap exists between the pad and the substrate; and an extraction electrode which connects the electrode pad and the gate electrode to one another.

The error amplifier circuit of the present invention includes: a plurality of error amplifiers that respectively obtain outputs of errors regarding two input signals; and a multiplexer that selects or deselects the outputs of the plurality of error amplifiers and outputs the output of the selected error amplifier as a control signal for a controlled circuit. In the multiplexer, for one of the plurality of error amplifiers whose output is not selected, a delay element provided on the input path of the one error amplifier is short-circuited to expand the frequency band of the error amplifier.

An amplifier comprises a signal input end, a signal output end, an amplifying circuit and at least one variable voltage generating circuit. The signal input end is used for receiving an input signal. The signal output end is used for outputting an amplified signal. A transistor of the amplifying circuit comprises a first end, a second end, a control end and a substrate end, the control end is coupled to the signal input end, the second end is coupled to the signal output end, and the connection state of the substrate end is a floating connection state. The at least one variable voltage generating circuit is coupled to the transistor of the amplifying circuit. During a transient period, a first voltage difference exists between the second end and the first end of the transistor, and during a steady state period, a second voltage difference exists. The first voltage difference is greater than the second voltage difference.

A reference voltage controlled equalization input data buffer circuit includes a first amplifier, a second amplifier, a feedback signal generator, a reference voltage converter, a reference voltage multiplexing circuit, and a gain control unit. The first amplifier includes a first input terminal for receiving a data signal, a second input terminal for receiving a reference voltage, a first output terminal, and a second output terminal. The second amplifier is coupled to the first amplifier. The feedback signal generator is coupled to the second amplifier. The reference voltage converter is used for receiving the reference voltage. The reference voltage multiplexing circuit is coupled to the second amplifier and the reference voltage converter. The gain control unit is coupled to the feedback signal generator, the first output terminal of the first amplifier, the second output terminal of the first amplifier, and the reference voltage multiplexing circuit.