114results about "Amplifiers with semiconductor devices only" patented technology

Signal processing circuitry configured to receive an input signal and to output a processed output signal, wherein the signal processing circuitry is configured to: receive an indication of a temporal location of a transient in the input signal; and provide, in the processed output signal, a masking signal bridging the temporal location of the transient to mask the transient.

A current leakage mitigation circuit is provided. The circuit includes a charge storage circuit for receiving a control signal output, and a correction circuit connected to a bottom plate of the charge storage device. The control signal is output by an amplifier circuit connected to the current leakage mitigation circuit. The correction circuit samples the control signal, applies a filter to the control signal for to extracting a predefined frequency component, amplifies the filtered control signal, and applies the amplified control signal to the bottom plate of the current storage device.

The invention discloses a biasing circuit, an array substrate and detection equipment. The biasing circuit comprises a coupling module and an equivalent resistance module, the first end of the coupling module is connected with an input signal, and the second end of the coupling module serves as the output end of the biasing circuit; the first end of the equivalent resistance module is connected with the second end of the coupling module, the second end of the equivalent resistance module is connected with bias voltage, and the control end of the equivalent resistance module is connected with control voltage; wherein the equivalent resistance module comprises at least one transistor, and the control voltage is used for controlling the working state of the transistor in the equivalent resistance module and adjusting the resistance value of the transistor in the equivalent resistance module. According to the technical scheme, the use performance of the detection equipment is improved.

This semiconductor device is provided with: a first substrate (100) on which a first semiconductor element (10) is mounted, the first substrate (100) having a plurality of first front-surface-side pads disposed around the front surface; a second substrate (200) on which the first semiconductor element (20) is mounted, the second substrate (200) having a plurality of second front-surface-side pads disposed around the front surface; a third substrate (300) disposed between the first substrate (100) and the second substrate (200) so as to face the front surface of the first substrate (100) and the front surface of the second substrate (200), the third substrate (300) having a plurality of third rear-surface-side pads on the periphery of the rear surface, and a plurality of third front-surface-side pads on the periphery of the front surface; a plurality of first connection members (50) that electrically connect the corresponding first front-surface-side pads of the first substrate (100) and the corresponding third back-surface-side pads of the third substrate (300), respectively; a plurality of second connection members (70) that electrically connect the corresponding second front-surface-side pads of the second substrate (200) and the corresponding third front-surface-side pads of the third substrate (300); a first resin layer (400) that is in contact with the periphery of the front surface of the first substrate (100) and the periphery of the rear surface of the third substrate (300), and that has a hollow section; and a second resin layer (500) which is in contact with the periphery of the front surface of the second substrate (200) and the periphery of the back surface of the third substrate (300), and which has a hollow portion.

The utility model discloses a packaging carrier and a Doherty amplifier comprising the packaging carrier. The packaging carrier comprises a first input interface and a second input interface, a first output interface and a second output interface; a substrate; the first transistor is located on the substrate, the control end of the first transistor is coupled to the first input interface, and the output end of the first transistor is coupled to the first output interface; the second transistor is located on the substrate, the control end of the second transistor is coupled to the second input interface, the output end of the second transistor is coupled to the second output interface, the first transistor comprises a silicon carbide-based transistor, and the second transistor comprises a silicon-based transistor; and the bias circuit is configured to provide corresponding bias voltages for the first transistor and the second transistor.

The proximity sensor includes a detection coil, a metal head housing, and a power supply cable. The detection coil generates a detection current. The metal head housing houses the detection coil. The power supply cable has an electrical connection with the detection coil and is connected to the metal head housing. At least a part of an internal space of the metal head housing is filled with a filler so as to bury the detection coil. As the filler, an adhesive and an additive having a relative permittivity lower than that of the adhesive are mixed.

A bias compensation circuit includes a detection circuit comprising a diode-connected transistor circuit having a first terminal for receiving a first current and a second terminal; and a first diode circuit having a first terminal for receiving a second current and a second terminal; wherein the detection circuit provides a first voltage level based on the diode-connected transistor circuit and provides a second voltage level based on the first diode circuit; a voltage-to-current conversion circuit coupled to the detection circuit for generating a first reference current based on the first voltage level and the second voltage level; and a bias circuit coupled to the voltage-to-current conversion circuit for receiving the first reference current to provide a bias level based on the first reference current.

A display device includes a display panel including a pixels, a timing controller configured to generate output control information based on an output timing of image data to be written to the pixels, and a plurality of amplifiers configured to output a target data voltage corresponding to the image data to output channels connected to the pixels. Each of the plurality of amplifiers includes one or more transistors configured to apply a preset rising current or falling current to an output node connected to one of the channels to output the target data voltage, and a compensation capacitance adjuster configured to adjust compensation capacitance of the output node according to the output control information.

An amplifier comprises a signal input end, a signal output end, an amplifying circuit and at least one variable voltage generating circuit. The signal input end is used for receiving an input signal. The signal output end is used for outputting an amplified signal. A transistor of the amplifying circuit comprises a first end, a second end, a control end and a substrate end, the control end is coupled to the signal input end, the second end is coupled to the signal output end, and the connection state of the substrate end is a floating connection state. The at least one variable voltage generating circuit is coupled to the transistor of the amplifying circuit. During a transient period, a first voltage difference exists between the second end and the first end of the transistor, and during a steady state period, a second voltage difference exists. The first voltage difference is greater than the second voltage difference.

A reference voltage controlled equalization input data buffer circuit includes a first amplifier, a second amplifier, a feedback signal generator, a reference voltage converter, a reference voltage multiplexing circuit, and a gain control unit. The first amplifier includes a first input terminal for receiving a data signal, a second input terminal for receiving a reference voltage, a first output terminal, and a second output terminal. The second amplifier is coupled to the first amplifier. The feedback signal generator is coupled to the second amplifier. The reference voltage converter is used for receiving the reference voltage. The reference voltage multiplexing circuit is coupled to the second amplifier and the reference voltage converter. The gain control unit is coupled to the feedback signal generator, the first output terminal of the first amplifier, the second output terminal of the first amplifier, and the reference voltage multiplexing circuit.

The invention relates to the technical field of amplifiers, and discloses a high-reliability low-noise amplifier chip, the circuit comprises an active bias circuit, a cascode low-noise amplifier circuit, a feedback circuit and a large input power protection circuit, a first diode D1 is added in the active bias circuit of the low-noise amplifier, and a second diode D2 is added in the active bias circuit of the low-noise amplifier. The Vgs of the fourth transistor M4 in the cascode low-noise amplification circuit is raised due to the existence of the first diode D1, and after the Vgs are increased, the output power 1dB compression point of the circuit is increased, so that the low-noise amplifier chip can realize high output 1dB compression point and low noise coefficient. When a high-power signal is input, the existence of the high-input-power protection circuit provides a power discharge path for the fourth transistor M4, so that the dynamic voltage swing of the fourth transistor M4 is within a normal range, and the fourth transistor M4 is prevented from being burnt out due to overhigh input power; due to the existence of the twelfth resistor R12, the branch current of the high-input-power protection circuit is reduced, a post-stage diode is protected from being burnt out due to overlarge current, and therefore the reliability of the low-noise amplifier chip is improved.

A sensing and amplifying circuit includes a driving voltage control circuit configured to control a voltage level of a driving voltage based on a surrounding temperature of the sensing and amplifying circuit, a delay control circuit configured to generate a line connection signal and an inverted line connection signal in response to a delay start signal by being supplied with the driving voltage, and a sense amplifier configured to perform a sensing and amplifying operation in response to the line connection signal and the inverted line connection signal. An interval between enable timing of the line connection signal and enable timing of the inverted line connection signal is adjusted as the surrounding temperature changes.

Disclosed are a low-noise, short-offset transient electromagnetic receiving conditioning circuit and a receiver. The conditioning circuit includes: a first power supply filtering circuit, a second power supply filtering circuit, an active filtering circuit, a power frequency noise suppression circuit, and a low-noise amplification circuit. The first and second power supply filtering circuits are used to filter the first and second power supplies, respectively, to reduce noise. The active filtering circuit is designed to filter out interference signals. The power frequency noise suppression circuit is used to eliminate power frequency noise. The low-noise amplification circuit includes an input-stage amplification circuit, an intermediate-stage amplification circuit, and an output-stage amplification circuit. The technical solution of this disclosure incorporates multiple filtering circuits to remove noise, thereby facilitating noise reduction.

The application discloses a kind of RRAM memory and computing integrated chip of hybrid analog-digital converter and electronic equipment, belong to memory and computing integrated chip technical field, including RRAM array module, gating module and hybrid analog-digital converter module, the word line, bit line and source line of gating module and RRAM array module are connected, and receive digital control signal, the specific address of RRAM array module is gated, read-write and matrix-vector multiplication operation;Hybrid analog-digital converter is connected on the source line of RRAM array module by gating module, digital control signal is input voltage to the bit line and word line of RRAM array module by controlling gating switch, the source line of RRAM array module generates corresponding convergent current, the current is transmitted to hybrid analog-digital converter by gating module, and the analog-digital converter completes quantization, and output calculation result.The application can greatly improve the computing power of chip, and be more favorable to the storage and matrix-vector multiplication calculation of data.

An electronic package is provided. The electronic package includes an amplifier component, a control component, and a first circuit layer. The control component is disposed above the amplifier component. The first circuit layer is disposed between the amplifier component and the control component. The control component is configured to transmit a first signal to the amplifier component and to output a second signal amplified by the amplifier component.

A module has two portions, each portion has two units provides an analog-type attenuator-tuning approach having digital control. Each of the units includes an input, an output, three selectable conductive paths, and an input switching element for selectably connecting the unit input to the unit output via one of the three selectable conductive paths. The first and second paths have attenuation elements. The unit output of the first unit of each portion is connected to the unit input of the second unit thereof and the unit output of the via one of the three selectable conductive paths, the unit output of the first unit of each portion is connected to the unit input of the second unit thereof, and the unit output of the second unit of the first portion is connected to the unit input of the first unit of the second portion.

A dynamic amplifier includes a power supply circuit and first to fourth transistors. The power supply circuit is configured to provide power voltages. The first transistor is configured to be biased by a first auxiliary signal and to receive a first power voltage in the power voltages. The second transistor is configured to be biased by a second auxiliary signal and to receive the first power voltage. The third transistor is configured to receive the power voltages and generate a first output signal according to a first input signal. The fourth transistor is configured to receive the power voltages and generate a second output signal according to a second input signal, in which the third transistor is configured to receive the first power voltage via the first transistor, and the fourth transistor is configured to receive the first power voltage via the second transistor.

A gain control device comprises a sign bit identification device and a gain determination device. The sign bit identification device is used to receive a data, identify a sign bit, and obtain a position of a time slot corresponding to the sign bit. Also, the data comprises a plurality of bits, wherein the most significant bit of the bits is designed to be a sign bit which is used to represent a positive or negative value of the data. The gain determination device is electrically connected to the sign bit identification device, and the gain determination device is used to determine a gain value for amplifying the data based on the position of the time slot corresponding to the sign bit identified through the sign bit identification device.

The invention provides an operational amplifier with a built-in capacitance multiplier. The operational amplifier comprises an input transistor, a current mirror circuit and a capacitor. The input transistor generates an input current according to an input signal, and the current mirror circuit generates a current mirror output current at a current output terminal of the current mirror circuit according to a current mirror input current corresponding to the input current received by a current input terminal of the current mirror circuit. Wherein the current output terminal is coupled to an amplifier output terminal of the operational amplifier. Furthermore, a first terminal of the capacitor is coupled to the amplifier output terminal, and a second terminal of the capacitor is coupled to the current input terminal, such that an equivalent capacitance value of the capacitor at the amplifier output terminal is multiplied by the current mirror circuit.

An ion detection current conversion circuit includes: a conversion amplifier coupled to a conversion resistor assembly to convert an ion detection current generated by an ion detector into an ion detection voltage, the conversion resistor assembly including a resistor with high resistance and a capacitor compensation element; and a compensation voltage circuit for obtaining a compensation voltage from the ion detection voltage and feeding the compensation voltage to the capacitor compensation element, the compensation voltage circuit including a variable resistor for adjusting the compensation voltage. The conversion circuit may further include: a voltage reduction circuit for obtaining a reduced voltage from the ion detection voltage; and a neutralization amplifier unit for at least partially neutralizing the voltage reduction of the voltage reduction circuit. The reduced voltage allows the use of low-voltage components, such as digital variable resistors.

The present invention provides a linear amplifier comprising: an amplifier stage, configured to generate a first signal and a second signal; a DC-shifting stage, configured to adjust a DC voltage of the first signal and a DC voltage of the second signal to generate an adjusted first signal and an adjusted second signal, wherein a DC voltage of the adjusted first signal is higher than a DC voltage of the first signal, and a DC voltage of the adjusted second signal is lower than a DC voltage of the second signal; a compensation network, configured to generate a first driving signal and a second driving signal according to the first signal, the second signal, the adjusted first signal and the adjusted second signal; and a power stage comprising a P-type transistor and an N-type transistor, wherein the P-type transistor and the N-type transistor are driven by the first driving signal and the second driving signal, respectively.

A source amplifier includes: an input circuit for receiving an input signal from an input terminal and an output signal having a complementary relationship with the input signal, and outputting a first intermediate signal and a second intermediate signal to a first intermediate node and a second intermediate node, respectively, based on the input signal and the output signal; an amplifier for amplifying the first intermediate signal and the second intermediate signal to output a third intermediate signal and a fourth intermediate signal; an output circuit configured to output an output signal as a data voltage to an output terminal based on the third intermediate signal and the fourth intermediate signal; a compensator including a first capacitor connected between the output terminal and the first intermediate node, and a second capacitor connected between the output terminal and the second intermediate node; and a feed-forward circuit.

According to the pre-amplification stage circuit and the micro-processing chip provided by the embodiment of the invention, the first end of a first input module and the first end of a second input module are electrically connected with a first power supply, and the second end of the first input module is electrically connected with the first end of a first load module; the second end of the second input module is electrically connected with the first end of the second load module; the second end of the first load module and the second end of the second load module are electrically connected with the second power supply; the first switch module is arranged between the first end of the first load module and the first end of the second load module; in the first state, the first switch module conducts electric connection between the first end of the first load module and the first end of the second load module. When the first state is switched to the second state, the first switch module disconnects the electrical connection between the first end of the first load module and the first end of the second load module. The amplification efficiency is improved.

An enhanced current mirror can be utilized to accurately control a bias current associated with an amplifier. A current controller component (CCC) can employ the enhanced current mirror and can be associated with the amplifier. The CCC can comprise a comparator that can compare an adjusted supply voltage level to a reference voltage level, the adjusted supply voltage level relating to a supply voltage level of a supply voltage supplied to the amplifier and CCC. The CCC can control switching of an operational state of a transistor of the comparator to switch in or out a resistance of a reference resistor component associated with the supply voltage, based on a result of the comparison of the adjusted supply voltage level to the reference voltage level, to facilitate accurately controlling an amount of bias current associated with the amplifier. The CCC and amplifier can be situated on the same die.

A feedforward circuitry system for regulating voltage includes a voltage regulator for generating a regulated voltage, a bias generator operatively connected to the voltage regulator for generating a sub-threshold gate bias, a plurality of coupling capacitors, at least one of the coupling capacitors operatively connected to the bias generator for reading the sub-threshold gate bias and a feedforward amplifier operatively coupled with at least one of the coupling capacitors, characterized in that the plurality of coupling capacitors being configured to direct AC-couple an output transition of CMOS logic gates. A method for regulating voltage in a feedforward circuitry system through a direct AC-coupling is also provided.

An ion detection current conversion circuit (153) comprises: - a conversion amplifier (152) coupled with a conversion resistor assembly for converting an ion detection current produced by an ion detector into an ion detection voltage, the conversion resistor assembly comprising a resistor (151) having a high resistance and a capacitive compensation element (157), and - a compensation voltage circuit (158) for deriving a compensation voltage (Vcomp) from the ion detection voltage (Vout) and feeding the compensation voltage to the capacitive compensation element (157), the compensation voltage circuit comprising a variable resistor (201) for adjusting the compensation voltage. The conversion circuit may further comprise a voltage reduction circuit (R15, R16, 220) for deriving a reduced voltage (Vred) from the ion detection voltage (Vout) and a neutralizing amplifier unit (211) for at least partially neutralizing the voltage reduction of the voltage reduction circuit. The reduced voltage allows low-voltage components, such as digital variable resistors, to be used.

An impedance measurement device of the present disclosure includes: an electrochemical energy device; an amplifier connected to each connection terminal of the electrochemical energy device and configured to amplify a signal introduced into a wiring; and a main board configured to receive the signal from the amplifier and measure an impedance. Accordingly, the present invention has advantages in that high resistance to electromagnetic interference may be achieved by disposing a preamplifier close to a terminal of an electrochemical energy device to amplify only the signal without amplifying a noise introduced into a wiring.

The invention discloses a single-stage amplification circuit and a gain high and low temperature compensation method thereof. The single-stage amplification circuit comprises an input matching network and a grid electrode feed temperature compensation network which are connected with a grid electrode of a pHEMT tube; the drain electrode of the pHEMT tube and the drain electrode feed network are respectively connected with the output matching network; the input end of the input matching network is used for inputting a radio frequency signal and converting input impedance into grid input impedance of the pHEMT tube to play a role in impedance matching; the pHEMT tube is used for amplifying a signal input into the pHEMT tube and then outputting the amplified signal to the output matching network; the output matching network is used for converting the drain impedance of the pHEMT tube into output impedance so as to realize matching of the single-stage amplification circuit and an external system, and the output impedance is equal to the input impedance; the grid feed temperature compensation network is used for providing grid voltage for the pHEMT tube; the drain electrode feed network is used for providing drain electrode voltage for the pHEMT tube. According to the invention, the consistency of high and low temperature gain of the single-stage amplification circuit is realized.

A bias supply circuit includes a first inductor connected between a bias supply terminal that supplies a bias voltage to an amplifier and a power supply terminal connected to a power supply, a second inductor connected in series with the first inductor between the bias supply terminal and the power supply terminal and connected between the first inductor and the power supply terminal, a first capacitor shunt-connected to a first node between the first inductor and the second inductor, and a second capacitor shunt-connected to a second node between the second inductor and the power supply terminal.

An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage.