168results about "Amplifiers with semiconductor devices only" patented technology

An integrated circuit (IC), comprising: a first gain stage configured to apply a first gain to a first signal to generate a first amplified signal; a first converter configured to convert the first signal to a first output signal; a first output pin for outputting the first output signal; gain update circuitry configured to: output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, subsequently output a first external gain control signal to a second output pin of the IC, wherein output of the first external gain control signal is delayed relative to output of the first internal gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first gain stage and the first output pin.

A virtual radio frequency (VRF) equalizer for an envelope tracking integrated circuit (ETIC) is disclosed. In one aspect, an ETIC provides envelope tracking (ET) for a barely Doherty (BD) power amplifier stage. The VRF equalizer includes circuitry that provides ripple cancelation that is caused by load modulation of the BD power amplifier stage. Additional circuitry is included to compensate for an amplifier within the ETIC. By canceling the ripple within the ETIC, the overall performance and efficiency of the BD power amplifier stage is improved, resulting in better performance of a transmitter in a wireless communication device.

Signal processing circuitry configured to receive an input signal and to output a processed output signal, wherein the signal processing circuitry is configured to: receive an indication of a temporal location of a transient in the input signal; and provide, in the processed output signal, a masking signal bridging the temporal location of the transient to mask the transient.

A current leakage mitigation circuit is provided. The circuit includes a charge storage circuit for receiving a control signal output, and a correction circuit connected to a bottom plate of the charge storage device. The control signal is output by an amplifier circuit connected to the current leakage mitigation circuit. The correction circuit samples the control signal, applies a filter to the control signal for to extracting a predefined frequency component, amplifies the filtered control signal, and applies the amplified control signal to the bottom plate of the current storage device.

A semiconductor device may include: a plurality of cell blocks, each cell block including: a high electron mobility transistor; and an amplification circuit configured to apply a gate signal to a gate electrode of the high electron mobility transistor. The semiconductor device also includes a signal generator configured to provide a pull-up signal and a pull-down signal to the amplification circuit of each of the plurality of cell blocks. The high electron mobility transistors of the plurality of cell blocks are connected in parallel.

The invention discloses a biasing circuit, an array substrate and detection equipment. The biasing circuit comprises a coupling module and an equivalent resistance module, the first end of the coupling module is connected with an input signal, and the second end of the coupling module serves as the output end of the biasing circuit; the first end of the equivalent resistance module is connected with the second end of the coupling module, the second end of the equivalent resistance module is connected with bias voltage, and the control end of the equivalent resistance module is connected with control voltage; wherein the equivalent resistance module comprises at least one transistor, and the control voltage is used for controlling the working state of the transistor in the equivalent resistance module and adjusting the resistance value of the transistor in the equivalent resistance module. According to the technical scheme, the use performance of the detection equipment is improved.

This semiconductor device is provided with: a first substrate (100) on which a first semiconductor element (10) is mounted, the first substrate (100) having a plurality of first front-surface-side pads disposed around the front surface; a second substrate (200) on which the first semiconductor element (20) is mounted, the second substrate (200) having a plurality of second front-surface-side pads disposed around the front surface; a third substrate (300) disposed between the first substrate (100) and the second substrate (200) so as to face the front surface of the first substrate (100) and the front surface of the second substrate (200), the third substrate (300) having a plurality of third rear-surface-side pads on the periphery of the rear surface, and a plurality of third front-surface-side pads on the periphery of the front surface; a plurality of first connection members (50) that electrically connect the corresponding first front-surface-side pads of the first substrate (100) and the corresponding third back-surface-side pads of the third substrate (300), respectively; a plurality of second connection members (70) that electrically connect the corresponding second front-surface-side pads of the second substrate (200) and the corresponding third front-surface-side pads of the third substrate (300); a first resin layer (400) that is in contact with the periphery of the front surface of the first substrate (100) and the periphery of the rear surface of the third substrate (300), and that has a hollow section; and a second resin layer (500) which is in contact with the periphery of the front surface of the second substrate (200) and the periphery of the back surface of the third substrate (300), and which has a hollow portion.

The invention discloses a cascading signal processing circuit based on separation components, and belongs to the technical field of signal processing circuits. The cascading signal processing circuit comprises a first circuit, a second circuit, a cascading convergence point J1, a third circuit and a cascading convergence point J2. The circuit is composed of three circuit parts which are all designed by using separation elements, based on the cost and flexible layout advantages of the separation elements, parameter matching under the requirements of signal anti-shake and signal latching flexibility is achieved, and the circuit can respond to high-speed abrupt change signals and can also adapt to anti-interference application of conventional level or pulse signals. On the premise that the circuit topology is not changed, grouping cascading of multiple intra-group signals and multi-path cascading of multiple paths of signals are supported, and meanwhile infinite cascading of interrupt signals corresponding to the multiple paths of signals and time division multiplexing summarizing access of the interrupt signals are achieved; and the effects of reducing the circuit cost, the PCB layout flexibility, the function and performance adaptation flexibility and the cascade expansibility are obvious.

The utility model discloses a packaging carrier and a Doherty amplifier comprising the packaging carrier. The packaging carrier comprises a first input interface and a second input interface, a first output interface and a second output interface; a substrate; the first transistor is located on the substrate, the control end of the first transistor is coupled to the first input interface, and the output end of the first transistor is coupled to the first output interface; the second transistor is located on the substrate, the control end of the second transistor is coupled to the second input interface, the output end of the second transistor is coupled to the second output interface, the first transistor comprises a silicon carbide-based transistor, and the second transistor comprises a silicon-based transistor; and the bias circuit is configured to provide corresponding bias voltages for the first transistor and the second transistor.

The proximity sensor includes a detection coil, a metal head housing, and a power supply cable. The detection coil generates a detection current. The metal head housing houses the detection coil. The power supply cable has an electrical connection with the detection coil and is connected to the metal head housing. At least a part of an internal space of the metal head housing is filled with a filler so as to bury the detection coil. As the filler, an adhesive and an additive having a relative permittivity lower than that of the adhesive are mixed.

A bias compensation circuit includes a detection circuit comprising a diode-connected transistor circuit having a first terminal for receiving a first current and a second terminal; and a first diode circuit having a first terminal for receiving a second current and a second terminal; wherein the detection circuit provides a first voltage level based on the diode-connected transistor circuit and provides a second voltage level based on the first diode circuit; a voltage-to-current conversion circuit coupled to the detection circuit for generating a first reference current based on the first voltage level and the second voltage level; and a bias circuit coupled to the voltage-to-current conversion circuit for receiving the first reference current to provide a bias level based on the first reference current.

The utility model provides a biasing circuit and an amplifier. The bias circuit comprises a programmable current source which generates bias current with adjustable magnitude based on a first control signal; the amplification transistor is used for receiving bias voltage; a transistor unit for an input transistor of the first current mirror; the transistor unit comprises a plurality of first transistors, and when the control ends of the first transistors receive bias current, and the first ends and the control ends of the first transistors are short-circuited and connected to an output node, the first transistors provide voltage for the output node; and the first switch units change the quantity of the bias current received by the control end of the first transistor and / or change the quantity of the output nodes connected to the first end of the first transistor based on the second control signal. Therefore, the adjusting range is further widened while the adjusting precision is guaranteed.

A display device includes a display panel including a pixels, a timing controller configured to generate output control information based on an output timing of image data to be written to the pixels, and a plurality of amplifiers configured to output a target data voltage corresponding to the image data to output channels connected to the pixels. Each of the plurality of amplifiers includes one or more transistors configured to apply a preset rising current or falling current to an output node connected to one of the channels to output the target data voltage, and a compensation capacitance adjuster configured to adjust compensation capacitance of the output node according to the output control information.

A display device includes a display panel including a pixels, a timing controller configured to generate output control information based on an output timing of image data to be written to the pixels, and a plurality of amplifiers configured to output a target data voltage corresponding to the image data to output channels connected to the pixels. Each of the plurality of amplifiers includes one or more transistors configured to apply a preset rising current or falling current to an output node connected to one of the channels to output the target data voltage, and a compensation capacitance adjuster configured to adjust compensation capacitance of the output node according to the output control information.

A system configured as part of an integrated circuit to block DC components from an amplifier comprising a matching network and an emitter follower circuit. The matching comprises an input configured to receive an input signal having a DC component. A voltage divider network comprises at least one resistor, and at least one capacitor. The network receives the signal and DC component and the voltage divider network blocks the DC component to generate a network output signal. The emitter follower (EF) circuit with EF devices configured to process the network output signal to generate an EF circuit output signal on an EF output. A biasing circuit generates a bias signal for the EF device. The bias signal has a value that is controlled by a bias control signal. Aias control signal generator compares the EF circuit output signal to a reference voltage, and generates the bias control signal.

This semiconductor device comprises: a substrate; a gate electrode, a source electrode and a drain electrode which are positioned on the substrate; a plurality of non-conductive nanowires which are arranged two-dimensionally on the top surface of the substrate so as to extend in a direction which is perpendicular to the top surface of the substrate; an electrode pad which is supported by the plurality of nanowires and is positioned at the top end of the plurality of nanowires in a manner such that a gap exists between the pad and the substrate; and an extraction electrode which connects the electrode pad and the gate electrode to one another.

The error amplifier circuit of the present invention includes: a plurality of error amplifiers that respectively obtain outputs of errors regarding two input signals; and a multiplexer that selects or deselects the outputs of the plurality of error amplifiers and outputs the output of the selected error amplifier as a control signal for a controlled circuit. In the multiplexer, for one of the plurality of error amplifiers whose output is not selected, a delay element provided on the input path of the one error amplifier is short-circuited to expand the frequency band of the error amplifier.

An amplifier comprises a signal input end, a signal output end, an amplifying circuit and at least one variable voltage generating circuit. The signal input end is used for receiving an input signal. The signal output end is used for outputting an amplified signal. A transistor of the amplifying circuit comprises a first end, a second end, a control end and a substrate end, the control end is coupled to the signal input end, the second end is coupled to the signal output end, and the connection state of the substrate end is a floating connection state. The at least one variable voltage generating circuit is coupled to the transistor of the amplifying circuit. During a transient period, a first voltage difference exists between the second end and the first end of the transistor, and during a steady state period, a second voltage difference exists. The first voltage difference is greater than the second voltage difference.

A reference voltage controlled equalization input data buffer circuit includes a first amplifier, a second amplifier, a feedback signal generator, a reference voltage converter, a reference voltage multiplexing circuit, and a gain control unit. The first amplifier includes a first input terminal for receiving a data signal, a second input terminal for receiving a reference voltage, a first output terminal, and a second output terminal. The second amplifier is coupled to the first amplifier. The feedback signal generator is coupled to the second amplifier. The reference voltage converter is used for receiving the reference voltage. The reference voltage multiplexing circuit is coupled to the second amplifier and the reference voltage converter. The gain control unit is coupled to the feedback signal generator, the first output terminal of the first amplifier, the second output terminal of the first amplifier, and the reference voltage multiplexing circuit.

The invention relates to the technical field of amplifiers, and discloses a high-reliability low-noise amplifier chip, the circuit comprises an active bias circuit, a cascode low-noise amplifier circuit, a feedback circuit and a large input power protection circuit, a first diode D1 is added in the active bias circuit of the low-noise amplifier, and a second diode D2 is added in the active bias circuit of the low-noise amplifier. The Vgs of the fourth transistor M4 in the cascode low-noise amplification circuit is raised due to the existence of the first diode D1, and after the Vgs are increased, the output power 1dB compression point of the circuit is increased, so that the low-noise amplifier chip can realize high output 1dB compression point and low noise coefficient. When a high-power signal is input, the existence of the high-input-power protection circuit provides a power discharge path for the fourth transistor M4, so that the dynamic voltage swing of the fourth transistor M4 is within a normal range, and the fourth transistor M4 is prevented from being burnt out due to overhigh input power; due to the existence of the twelfth resistor R12, the branch current of the high-input-power protection circuit is reduced, a post-stage diode is protected from being burnt out due to overlarge current, and therefore the reliability of the low-noise amplifier chip is improved.

A multistage Doherty power amplifier and a transmitter are provided, and the multistage Doherty power amplifier includes: a generalized carrier amplifier, which is a nested 2-way inverted Doherty sub amplifier, and a generalized peaking amplifier, connected to the generalized carrier amplifier, which is a nested single ended sub amplifier or a nested 2-way normal Doherty sub amplifier, the generalized carrier amplifier and the generalized peaking amplifier are arranged in a generalized 2-way inverted Doherty power amplifier form. With the multistage Doherty power amplifier, signal power probability distribution function (PDF) oriented for a cost-effective multi stage Doherty PA design is applied, and 2-way normal and inverted Doherty PA cells are used as basic units to construct multistage Doherty PA with gain extension effect.

A sensing and amplifying circuit includes a driving voltage control circuit configured to control a voltage level of a driving voltage based on a surrounding temperature of the sensing and amplifying circuit, a delay control circuit configured to generate a line connection signal and an inverted line connection signal in response to a delay start signal by being supplied with the driving voltage, and a sense amplifier configured to perform a sensing and amplifying operation in response to the line connection signal and the inverted line connection signal. An interval between enable timing of the line connection signal and enable timing of the inverted line connection signal is adjusted as the surrounding temperature changes.

Disclosed are a low-noise, short-offset transient electromagnetic receiving conditioning circuit and a receiver. The conditioning circuit includes: a first power supply filtering circuit, a second power supply filtering circuit, an active filtering circuit, a power frequency noise suppression circuit, and a low-noise amplification circuit. The first and second power supply filtering circuits are used to filter the first and second power supplies, respectively, to reduce noise. The active filtering circuit is designed to filter out interference signals. The power frequency noise suppression circuit is used to eliminate power frequency noise. The low-noise amplification circuit includes an input-stage amplification circuit, an intermediate-stage amplification circuit, and an output-stage amplification circuit. The technical solution of this disclosure incorporates multiple filtering circuits to remove noise, thereby facilitating noise reduction.

The application discloses a kind of RRAM memory and computing integrated chip of hybrid analog-digital converter and electronic equipment, belong to memory and computing integrated chip technical field, including RRAM array module, gating module and hybrid analog-digital converter module, the word line, bit line and source line of gating module and RRAM array module are connected, and receive digital control signal, the specific address of RRAM array module is gated, read-write and matrix-vector multiplication operation;Hybrid analog-digital converter is connected on the source line of RRAM array module by gating module, digital control signal is input voltage to the bit line and word line of RRAM array module by controlling gating switch, the source line of RRAM array module generates corresponding convergent current, the current is transmitted to hybrid analog-digital converter by gating module, and the analog-digital converter completes quantization, and output calculation result.The application can greatly improve the computing power of chip, and be more favorable to the storage and matrix-vector multiplication calculation of data.

An electronic package is provided. The electronic package includes an amplifier component, a control component, and a first circuit layer. The control component is disposed above the amplifier component. The first circuit layer is disposed between the amplifier component and the control component. The control component is configured to transmit a first signal to the amplifier component and to output a second signal amplified by the amplifier component.

The present invention provides a linear amplifier including an amplifier stage, a DC-shifting stage, a compensation network and a power stage. The amplifier stage is configured to generate a first signal and a second signal. The DC-shifting stage is configured to adjust a DC voltage of the first signal and a DC voltage of the second signal to generate an adjusted first signal and an adjusted second signal. The compensation network is configured to generate a first driving signal and a second driving signal according to the first signal, the second signal, the adjusted first signal and the adjusted second signal. The power stage is configured to generate an output signal according to the first driving signal and the second driving signal.

A module has two portions, each portion has two units provides an analog-type attenuator-tuning approach having digital control. Each of the units includes an input, an output, three selectable conductive paths, and an input switching element for selectably connecting the unit input to the unit output via one of the three selectable conductive paths. The first and second paths have attenuation elements. The unit output of the first unit of each portion is connected to the unit input of the second unit thereof and the unit output of the via one of the three selectable conductive paths, the unit output of the first unit of each portion is connected to the unit input of the second unit thereof, and the unit output of the second unit of the first portion is connected to the unit input of the first unit of the second portion.

A dynamic amplifier includes a power supply circuit and first to fourth transistors. The power supply circuit is configured to provide power voltages. The first transistor is configured to be biased by a first auxiliary signal and to receive a first power voltage in the power voltages. The second transistor is configured to be biased by a second auxiliary signal and to receive the first power voltage. The third transistor is configured to receive the power voltages and generate a first output signal according to a first input signal. The fourth transistor is configured to receive the power voltages and generate a second output signal according to a second input signal, in which the third transistor is configured to receive the first power voltage via the first transistor, and the fourth transistor is configured to receive the first power voltage via the second transistor.

A semiconductor device may include: a plurality of unit blocks comprising switching circuits, each of the switching circuits including: a high electron mobility transistor; and an amplification circuit configured to apply a gate signal to a gate electrode of the high electron mobility transistor. The semiconductor device further includes a signal generator configured to provide a pull-up signal and a pull-down signal to the amplification circuit of each of the switching circuits. The high electron mobility transistors of the switching circuits are connected in parallel.

A gain control device comprises a sign bit identification device and a gain determination device. The sign bit identification device is used to receive a data, identify a sign bit, and obtain a position of a time slot corresponding to the sign bit. Also, the data comprises a plurality of bits, wherein the most significant bit of the bits is designed to be a sign bit which is used to represent a positive or negative value of the data. The gain determination device is electrically connected to the sign bit identification device, and the gain determination device is used to determine a gain value for amplifying the data based on the position of the time slot corresponding to the sign bit identified through the sign bit identification device.