76 results about "Bicmos integrated circuits" patented technology

Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P₁-N₂-P₂-N₁//N₁-P₃-N₃-P₁ lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC). The ESD protection cells are tested using the TLP (Transmission Line Pulse) technique, and ESD standards including HBM (Human Body Model), MM (Machine Model), and IEC (International Electrotechnical Commission) IEC 1000-4-2 standard for ESD immunity. ESD protection performance is demonstrated also at high temperature (140° C.). The unique high ratio of dual-polarity ESD protection level per unit area, allows for integration of fast-response and compact protection cells optimized for the current tendency of the semiconductor industry toward low cost and high density-oriented IC design. Symmetric/asymmetric dual polarity ESD protection performance is demonstrated for over 15 kV HBM, 2 kV MM, and 16.5 kV IEC for sub-micron technology.

Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a bird's beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the bird's beak region and terminating at the inner edge of the bird's beak region, a gate crossing the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the guard region. A variation of a local oxidation of silicon process is used with an additional bird's beak implantation mask as well as minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density.

Trench-generated device structures fabricated using a semiconductor-on-insulator (SOI) wafer, design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, as well as methods for fabricating trench-generated device structures. The device structure includes a trench extending through the semiconductor and insulator layers of the SOI wafer and into the underlying semiconductor substrate, and a first doped region in the semiconductor substrate. The doped region, which extends about the trench, has a second conductivity type opposite to the first conductivity type. The device structure further includes a first contact extending from the top surface through the semiconductor and insulator layers to a portion of the semiconductor substrate outside of the doped region, and a second contact extending from the top surface through the semiconductor and insulator layers to the doped region in the semiconductor substrate.

A vertical NPNP structure fabricated using a triple well CMOS process, as well as methods of making the vertical NPNP structure, methods of providing electrostatic discharge (ESD) protection, and design structures for a BiCMOS integrated circuit. The vertical NPNP structure may be used to provide on-chip protection to an input/output (I/O) pad from negative-voltage ESD events. A vertical PNPN structure may be also used to protect the same I/O pad from positive-voltage ESD events.

The invention discloses an integrated microphone offset voltage control method and an offset circuit. The method is implemented based on the CMOS (complementary metal-oxide-semiconductor) or BiCMOS (bipolar complementary metal oxide semiconductor) integrated circuit production process, and is applied to an offset voltage generating circuit of a silicon microphone which comprises a charge pump booster circuit, a rectifier circuits and a filter circuits. According to the method, the relationship between output voltages and input currents of the offset voltage generating circuit is controlled, so that the circuit is within a neighboring region with zero current, the input currents of output nodes of the circuit are increased with the increase of output voltages, and the increasing slope rises rapidly with the increase in voltage. The circuit is implemented by connecting a compensation circuit in parallel between the output terminal and the ground terminal of the rectifier circuit; and the compensation circuit has the following functions: in the region of almost zero current and close to the voltage of offset voltage working points of the microphone, the input currents of the output nodes are increased with the increase of voltages applied to the two ends of the compensation circuit, and the current increase rate is higher than the voltage increase rate.

Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a Bird's Beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the Bird's Beak region and terminating at the inner edge of the Bird's Beak region, a gate included in the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the Bird's Beak and guard regions. A variation of minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density.

The invention discloses a double-polycrystal and double-strain mixed crystal face Si-base Bi CMOS (complementary metal-oxide-semiconductor transistor) integrated device and a manufacturing method of the double-polycrystal and double-strain mixed crystal face Si-base Bi CMOS integrated device. The method provided by the invention comprises the following steps of: manufacturing an SOI (silicon on insulator) substrate with a crystal face (110) being as an upper base material and a crystal face (100) being as a lower base material; growing N-Si to be as a bipolar device collector region; growing P-SiGe/i-Si/i-Poly-Si in a base region in a photoetching region, manufacturing an emission electrode, a base electrode and a collector electrode, and forming an SiGe Hbt device; manufacturing a deep groove for isolation; selectively growing a PMOS (P-channel metal oxide semiconductor) device active region with the crystal face (110) in a PMOS device region and manufacturing a compression strain Si vertical channel PMOS device; etching a deep groove in an NMOS (N-channel metal oxide semiconductor) device region, selectively growing an NMOS device active region with the crystal face (100) and manufacturing an Si channel NMOS device; and manufacturing the Si-base Bi CMOS integrated device and circuit. According to the invention, the characteristics that electronic mobility of a tensile strain Si is higher than that of a body Si material, the hole mobility of a compression strain Si material is higher than that of the body Si material and mobility is anisotropic are fully used to manufacture the double-polycrystal and double-strain mixed crystal face Si-base Bi CMOS integrated circuit.

The invention discloses a mixed crystal plane silicon-on-insulator (SOI) bipolar complementary metal oxide semiconductor (BiCMOS) integrated device based on a square channel process and a preparation method. The method comprises the following steps of: preparing an SOI substrate, continuously growing N-Si, P-SiGe and N-Si layers on the SOI substrate, preparing an deep groove isolator, forming a collector, a base and an emitter contact area, and forming a SiGe heterojunction bipolar transistor (HBT) device; photo-etching an active area of a p-channel metal oxide semiconductor (PMOS) device, continuously growing 7 layers of materials in the active area, preparing a drain and a grid, and forming the PMOS device; photo-etching a groove of an active area of an n-channel metal oxide semiconductor (NMOS) device, continuously growing 4 layers of materials in the active area, preparing a grid dielectric layer and grid polycrystalline, and forming the NMOS device; and photo-etching lead holes, alloying, photo-etching leads, and thus forming the mixed crystal plane SOI BiCMOS integrated device and a mixed crystal plane SOI BiCMOS integrated circuit of which CMOS conductive channels are 22 to 45 nanometers based on the square channel process. By fully using the characteristic of mobility anisotropy of a strain Si material, the mixed crystal plane SOI BiCMOS integrated circuit with enhanced performance is prepared at the temperature between 600 and 800 DEG C.

The invention discloses a SiGe base vertical channel strain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and a manufacturing method. The method comprises the following steps of: manufacturing a SiGe HBT (Heterojunction Vipolar Transistor) device at a bipolar device area on a Si substrate sheet; etching an active area of an NMOS (N-Channel Metal Oxide Semiconductor) device; extensionally growing five layers of materials at the area so as to form the active area of the NMOS device; manufacturing the NMOS device; etching an active area of the PMOS (P-Channel Metal Oxide Semiconductor) device; extensionally growing three layers of materials at the area so as to form the active area of the PMOS device; forming a virtual grid and accomplishing the manufacturing of the PMOS device; and forming the SiGe base vertical channel strain BiCMOS integrated device and a circuit. The characteristics that the electronic mobility rate at the vertical direction and the hole mobility rate at the horizontal direction of the SiGe material are higher than that of the relaxation Si are utilized; and through a low temperature process, a circuit of the performance-enhanced SiGe base vertical channel strain BiCMOS integrated device is manufactured.

The invention discloses a vertical-channel mixed-lattice-strain BiCMOS integrated device and a preparation method. The preparation method comprises preparing an SOI (silicon on insulator) substrate, epitaxially growing a Si layer on the substrate as a collector region, preparing deep trench isolation, and preparing a double-polysilicon SiGe HBT (heterojunction bipolar transistor) device on the active region of the bipolar device by self-alignment process; etching an active region of a PMOS (p-channel metal oxide semiconductor) device by lithography, continuously growing seven material layers on the active region, andpreparing a drain and a gate to obtain the PMOS device; etching a trench in the active region of an NMOS (n-channel metal oxide semiconductor) device by lithography, continuously growing four material layers on the active region, preparing a gate dielectric layer and gate polysilicon to obtain the NMOS device, etching lead holes by lithography, alloying, and etching leads by lithography to obtain the vertical-channel mixed-lattice-strain BiCMOS integrated device and circuit with a CMOS conductive channel of 22 to 45nm. The preparation method provided by the invention can prepare the performance-enhanced vertical-channel mixed-lattice-strain BiCMOS integrated device at 600 to 800 DEG C by fully utilizing the characteristics of mobility anisotropy of the tensile strained Si material.

The invention discloses a three-polycrystalline SiGe HBT (Heterojunction Bipolar Transistor)-based hybrid crystal face strain BiCOMS integrated device and a preparation method thereof. The preparation method comprises the steps of: preparing an SOI (Silicon On Insulator) substrate, wherein an upper-layer matrix material is a crystal face (100) and a lower-layer matrix material is a crystal face (110); etching a bipolar device active region, growing an N type Si epitaxial layer, preparing a collector region, and preparing a base region and an emitter region to form a SiGe HBT device; etching an NMOS (N-channel Metal Oxide Semiconductor) device region to form a deep channel, and growing the active region of an NMOS device with the crystal face (100) selectively to prepare a strain Si channel NMOS device; and growing a SiGe epitaxial layer selectively along the crystal face (110) on a PMOS (P-channel Metal Oxide Semiconductor) device region, and preparing a compressive strain SiGe channel PMOS device on the SiGe epitaxial layer; and forming the three-polycrystalline SiGe HBT-based hybrid crystal face strain BiCOMS integrated device and a circuit. According to the invention, by using the characteristics that a mobility of a strain Si material is higher than that of a body Si material and the migration is anisotropic, the three-polycrystalline SiGe HBT-based hybrid crystal face strain BiCOMS integrated circuit with enhanced property is prepared on the basis of the SOI substrate.

The invention relates to special equipment and a method for diffusing an antimony latex source buried layer. According to the special equipment, a quartz diffusion tube is arranged in a diffusion high-temperature furnace; a gas inlet is formed at the front part of the quartz diffusion tube and connected with a uniform-flow quartz device; an exhaust port is formed at the rear part of the quartz diffusion tube; and the diffusion high-temperature furnace is divided into three areas, and a three-area temperature control device is arranged outside the furnace. According to the antimony latex source buried layer diffusion method, a low-resistance buried layer is prepared by use of a thermal diffusion method generally used on a process line, wherein the gluing speed is 2500-5000rpm; the diffusion conditions are that the optimal diffusion temperature is 1250 DEG C, the constant temperature time is 7 hours and the heating/cooling speed is 5 DEG C per minute; and the ratio of N2 to O2 in the protection atmosphere (diffusion atmosphere) is 8.8:1.8. According to the invention, the bipolar integrated circuit buried layer diffusion technology is optimized and can be popularized and applied to the diffusion of other bipolar discrete device buried layers, and can also be applied to a BiCMOS integrated circuit production line focusing on bipolar technology.

The invention discloses a bi-polycrystal SOI (Silicon On Insulator) Bi CMOS (Complementary Metal Oxide Semiconductor) integrated device with a SiGe clip-shaped channel and a preparation method of the device. The preparation method comprises the steps of conducting epitaxy on a collector region of a bipolar device on an SOI substrate, preparing a deep-trench isolator, a base window and base polycrystal, conducting epitaxy on a SiGe base region and a Poly-Si emitter region to form a SiGe HBT (Heterojuntion Bipolar Transistor) device; conducting photoetching on an active region of an NMOS (N-Channel Metal Oxide Semiconductor) device, growing five layers of materials on the region in an epitaxial manner to form the active region of the NMOS device so as to prepare an NMOS device; conducting photoetching on an active region of a PMOS (P-Channel Metal Oxide Semiconductor) device, growing three layers of materials in an epitaxial manner in the region to form the active region of the PMOS device, preparing a virtual grid electrode, and injecting by utilizing a self alignment process so as to form the drain electrode and the source electrode of the PMOS device; etching a virtual grid to prepare the PMOS device, and thus forming the Bi CMOS integrated with a conducting channel being 22-45nm and a circuit of an MOS (Metal Oxide Semiconductor) device, wherein the device and the circuit are based on the self alignment process. According to the preparation method, the self alignment process is adopted, and the characteristic of the anisotropism of the mobility ratio of strain SiGe material is utilized sufficiently, so that a bi-polycrystal SOI strain Bi COMOS integrated circuit with SiGe clip-shaped channel is prepared, and the performance of the circuit is enhanced.

The invention discloses a strain Si BiCMOS (Bipolar-Complementary Metal-Oxide-Semiconductor) integrated device based on an SOI (Silicon on Insulator) substrate and a preparation method thereof. The preparation method comprises the following steps: growing N-type Si epitaxy on the SOI substrate, preparing trench isolation, and manufacturing a conventional Si bipolar transistor in a bipolar device region; respectively photoetching the ditch grooves of the active regions of an NMOS (Negative-channel Metal Oxide Semiconductor) and a PMOS (Positive-channel Metal Oxide Semiconductor) devices, continuously growing an Si buffer layer, a gradually varied SiGe layer, a fixed component SiGe layer and an N-type strain Si channel layer in the ditch groove of the active region of the NMOS device and continuously growing an Si buffer layer, a gradually varied SiGe layer, a fixed component SiGe layer, a strain Si P-LDD layer, a strain Si channel layer, a strain Si P-LDD layer and a fixed component SiGe layer in the ditch groove of the active region of the PMOS device, and preparing a drain and a grid on the active region of the PMOS device to form the PMOS device; preparing a gate dielectric layer and a gate polycrystal in the active region of the NMOS device to form the NMOS device; and photoetching leads to form an Si BICMOS integrated circuit in which an MOS (Metal Oxide Semiconductor) conducting channel is 22-45nm. According to the invention, based on the full use of the characteristic that tension strain Si material has mobility anisotropism, the strain Si BiCMOS integrated device with strengthened performance based on SOI substrate and the circuit thereof are prepared at the temperature of 600-800 DEG C.

The invention discloses a stress silicon (Si) vertical-groove silicon-on-insulator bipolar complementary metal-oxide semiconductor (SOI BICMOS) integrated device and a preparation method. The preparation method comprises following steps of continuously growing n-type silicon (N-Si), p-type silicon germanium (P-SiGe), amorphous silicon (i-Si), amorphous poly silicon (i-Poly-Si) on an SOI substrate to prepare deep-groove isolation, preparing base-region shallow-groove isolation, photo-etching a base region, injecting boron ions, photo-etching a transmitting region, injecting phosphonium ions to form a collector electrode, and forming a SiGe heterojunction bipolar transistor (HBT) device; respectively photo-etching a N-channel metal-oxide semiconductor (NMOS) device active region groove and a P-channel metal-oxide semiconductor (PMOS) device active region groove, preparing a drain electrode and a grid electrode on the PMOS device active region to form a PMOS device; preparing a grid medium layer and grid polycrystal on the NMOS device active region to form an NMOS device; and photo-etching a lead to form the stress Si vertical-groove SOI BiCMOS integrated device and a circuit. The characteristics of mobility ratio anisotropy of a stress Si material are adequately utilized to prepare a stress Si vertical-groove SOI BiCMOS integrated circuit with enhanced performance under the temperature of 600 to 800 DEG C.