Vertical-channel mixed-lattice-strain BiCMOS (bipolar complementary metal oxide semiconductor) integrated device and preparation method

An integrated device, vertical channel technology, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problem that the mobility cannot be optimized at the same time

Inactive Publication Date: 2012-10-17
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At the same time, NMOS devices and PMOS devices are prepared on the same crystal plane, and their mobility cannot be optimal at the same time.

Method used

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  • Vertical-channel mixed-lattice-strain BiCMOS (bipolar complementary metal oxide semiconductor) integrated device and preparation method

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0137] Embodiment 1: Preparation of a vertical channel with a channel length of 22nm, a mixed crystal plane strained BiCMOS integrated device and a circuit, the specific steps are as follows:

[0138] Step 1, SOI substrate material preparation.

[0139] (1a) Select the P-type doping concentration as 1×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0140] (1b) Select the N-type doping concentration as 1×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the lower layer;

[0141] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;

[0142] (1d) SiO on the surf...

Embodiment 2

[0214] Embodiment 2: The preparation of a vertical channel with a channel length of 30nm, a mixed crystal plane strain BiCMOS integrated device and a circuit, the specific steps are as follows:

[0215] Step 1, SOI substrate material preparation.

[0216] (1a) Select the P-type doping concentration as 3×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0217] (1b) Select the N-type doping concentration as 3×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the lower layer;

[0218] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the substrate material of the lower layer and the upper layer of the active layer after injecting hydrogen, re...

Embodiment 3

[0291] Embodiment 3: The preparation of a vertical channel with a channel length of 45nm, a mixed crystal plane strained BiCMOS integrated device and a circuit, the specific steps are as follows:

[0292] Step 1, SOI substrate material preparation.

[0293] (1a) Select the P-type doping concentration as 5×10 15 cm -3 Si wafers with a crystal plane of (100) are oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0294] (1b) Select the N-type doping concentration as 5×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on its surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower layer;

[0295] (1c) Using a chemical mechanical polishing (CMP) process to polish the lower layer and the surface of the upper substrate material after hydrogen injection;

[0296] (1d) SiO on the surface of the ...

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PUM

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Abstract

The invention discloses a vertical-channel mixed-lattice-strain BiCMOS integrated device and a preparation method. The preparation method comprises preparing an SOI (silicon on insulator) substrate, epitaxially growing a Si layer on the substrate as a collector region, preparing deep trench isolation, and preparing a double-polysilicon SiGe HBT (heterojunction bipolar transistor) device on the active region of the bipolar device by self-alignment process; etching an active region of a PMOS (p-channel metal oxide semiconductor) device by lithography, continuously growing seven material layers on the active region, andpreparing a drain and a gate to obtain the PMOS device; etching a trench in the active region of an NMOS (n-channel metal oxide semiconductor) device by lithography, continuously growing four material layers on the active region, preparing a gate dielectric layer and gate polysilicon to obtain the NMOS device, etching lead holes by lithography, alloying, and etching leads by lithography to obtain the vertical-channel mixed-lattice-strain BiCMOS integrated device and circuit with a CMOS conductive channel of 22 to 45nm. The preparation method provided by the invention can prepare the performance-enhanced vertical-channel mixed-lattice-strain BiCMOS integrated device at 600 to 800 DEG C by fully utilizing the characteristics of mobility anisotropy of the tensile strained Si material.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, in particular to a vertical channel mixed crystal plane strain BiCMOS integrated device and a preparation method. Background technique [0002] The integrated circuit, which appeared in 1958, is one of the most influential inventions of the 20th century. Microelectronics, which was born based on this invention, has become the basis of existing modern technology, accelerating the process of knowledge and informationization of human society, and at the same time changing the way of thinking of human beings. It not only provides humans with a powerful tool to transform nature, but also opens up a broad space for development. [0003] In the contemporary era of highly developed information technology, microelectronic technology represented by integrated circuits is the key to information technology. As the fastest-growing, most influential and most widely used technology i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/06H01L21/8249
Inventor 胡辉勇宋建军张鹤鸣宣荣喜周春宇舒斌戴显英郝跃
Owner XIDIAN UNIV
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