380results about How to "Reduce process complexity" patented technology

The invention discloses an automatic testing method oriented to a large industrial system RPC API (Remote Procedure Call Application Program Interface). According to the method, API documents and historical calling data of tenants are used as input, and automatic API testing is achieved. The method mainly comprises three stages of API dependency model construction, API test sequence generation and API sequence parameter rendering. The construction of the API dependency model is realized based on an API document and historical calling data of tenants, and comprises three steps: static analysis of the API document, parameter clustering based on a large model, and dependency relationship filtering based on the historical calling data of the tenants. The generation of the API test sequence is based on an API dependency graph generated in the previous stage, a to-be-tested API is taken as a starting point, a front dependency API is searched for continuously in an iteration mode to generate the sequence, and finally filtering is carried out through CRUD semantics. The rendering of the API sequence parameters is realized by constructing a dynamic dictionary and recommending large model parameters aiming at the API sequence generated in the previous stage.

The invention relates to the field of semiconductors, in particular to a heat dissipation structure, a preparation method thereof and an IGBT (Insulated Gate Bipolar Translator) module. The preparation method of the heat dissipation structure provided by the invention comprises the steps of obtaining a to-be-combined heat sink based on a blind groove formed in one surface of the heat sink in the thickness direction; laminating and laminating the metal sheet and the ceramic substrate, firing, and metalizing the ceramic substrate; patterning processing is carried out based on the surface of the metal layer in the thickness direction, so that an exposed surface is formed on the ceramic layer in the thickness direction, and a metal boss capable of being matched with the blind groove is formed on the metal layer on the exposed surface; and the metal boss on the to-be-combined substrate is installed in the blind groove of the to-be-combined heat sink, the exposed face is attached to the surface of the to-be-combined heat sink to form a combined body, the combined body is sintered and cured, and the heat dissipation structure is obtained. The heat dissipation structure prepared by the preparation method can effectively reduce the number of thermal resistance interface layers, improve the heat dissipation efficiency of the IGBT chip, and significantly reduce the production cost and the process complexity.

The invention discloses a method for preparing a low-temperature flue gas denitration catalyst by utilizing electrolytic manganese anode mud, comprising the following steps: step one, material selection; step two, drying and grinding; step three, leaching; step four, solid-liquid separation; step five, multiple washing and filtering; wherein in the above step one, firstly, electrolytic manganese anode mud is selected as the raw material for preparing the low-temperature flue gas denitration catalyst; wherein in the above step two, the electrolytic manganese anode mud selected in step one is placed in a drying box for drying treatment. The invention has a simple synthesis method, and the raw materials used are from industrial waste residues, thereby reducing the impact on the environment. At the same time, the synthesized catalyst is conducive to efficient operation at ultra-low temperature, expanding the application scenarios of the catalyst, and at the same time, the electrolytic manganese anode mud is modified by soluble chloride salt, and the modification treatment of the electrolytic manganese anode mud is utilized, thereby greatly reducing the complexity of the subsequent process for preparing the catalyst.

The invention discloses a manufacturing method of a wireless charging coil and the wireless charging coil. The manufacturing method comprises the following steps: laminating a photosensitive adhesive film on a first surface of a pure copper foil; pressing a dry film with a coil pattern on the second surface of the pure copper foil; etching the pure copper foil from the second surface of the pure copper foil, and removing the pure copper foil outside the dry film coverage area; removing the dry film, and laminating a first flexible protective film on the second surface of the pure copper foil; and removing the photosensitive adhesive film, and laminating a second flexible protective film on the first surface of the pure copper foil. According to the technical scheme of the embodiment of the invention, the abnormal risk of subsequent processing of the product can be effectively reduced, the pure copper foil is protected in the manufacturing process, the production efficiency and the yield can be effectively improved, and the cost and the process complexity are effectively reduced.

The invention discloses a display panel and a manufacturing method thereof, and relates to the field of display, and the display panel comprises a first array chip, a second array chip and a third array chip which are arranged in the direction perpendicular to the plane where the display panel is located; the first array chip comprises a plurality of first light-emitting units; the third array chip is located on the light emitting side of the first array chip, the third array chip comprises a plurality of second light emitting units, and the side, away from the first array chip, of the third array chip is the light emitting side of the display panel; the second array chip is located between the first array chip and the third array chip and used for providing display driving signals for the first light-emitting unit and the second light-emitting unit; a light processing layer is arranged between the layer where the first light-emitting unit is located and the layer where the second light-emitting unit is located, and the light processing layer is used for forming light of a third color based on part of light emitted by the first light-emitting unit to be emitted. The display panel can realize higher integration level, higher performance, higher reliability and lower power consumption.

The utility model discloses a battery shell and a single battery, the battery shell comprises a metal main shell and a metal cover body, and the metal main shell is provided with an accommodating cavity for accommodating a core package and an opening communicated with the accommodating cavity; the metal cover body is inserted into the containing cavity through the opening and abuts against the bottom of the containing cavity to seal the opening, and the metal main shell and the metal cover body are connected at the opening in a welded mode. According to the utility model, by arranging the battery shell into the metal main shell and the metal cover body which are separated from each other, when the metal main shell is connected with the metal cover body, the metal cover body is partially inserted into the accommodating cavity, so that the metal cover body is partially propped against the bottom of the accommodating cavity for positioning; and then the metal cover body and the metal main shell are welded through the welding head. The welding positions of the metal cover body and the metal main shell are on the same plane, so that the metal main shell does not need to be turned over by a welding clamp in the welding process of the welding head, the process complexity of the battery shell is further reduced, and the reject ratio of the single battery can be reduced.

The invention discloses a neodymium-iron-boron magnetic ring forming device, a neodymium-iron-boron magnetic ring and a preparation method of the neodymium-iron-boron magnetic ring. The neodymium iron boron magnetic ring forming device comprises an upper punch, a female die, a lower outer punch and a lower inner punch. The neodymium-iron-boron magnetic ring forming device can complete multiple procedures such as cold pressing, hot pressing, pre-deformation and thermal deformation extrusion at a time, the process complexity is reduced, repeated heating is avoided, and the performance of the thermal deformation neodymium-iron-boron magnetic ring is improved.

The present invention provides a memory device and a manufacturing method thereof. The memory device includes a substrate and an electronic fuse structure. The substrate includes an array area and an electronic fuse area, and the electronic fuse area of ​​the substrate has an electronic fuse groove. The electronic fuse structure includes a first gate oxide layer, a plurality of doped regions, a dummy buried word line and an electronic fuse gate. The first gate oxide layer is formed on the surface of the electronic fuse groove. These doped regions are respectively formed in the substrate on opposite sides outside the electronic fuse groove and are in contact with the first gate oxide layer. The dummy buried word line is formed on the first gate oxide layer. The electronic fuse gate is formed on the dummy buried word line and is in contact with the first gate oxide layer. The dummy buried word line is electrically isolated from the electronic fuse gate.

The invention discloses a high-specific-strength multistage twin-crystal martensite structure titanium alloy and a preparation method thereof. Wherein the component system of the titanium alloy is as follows: Ti, Al, Mo, Nb, V, Cr and Fe; the alloy comprises the following elements in percentage by weight: 6-9% of Al; 0.5%-2% of Mo; 0.5%-2% of Nb; 0.2% to 1.5% of V; 0.2% to 1.5% of Cr; 0.2%-1.5% of Fe, and the balance Ti and inevitable trace impurities. The obtained titanium alloy is of a multistage twin-crystal martensite structure and has high specific strength, the room-temperature tensile yield strength of the titanium alloy can reach 1320 MPa or above, the room-temperature tensile strength of the titanium alloy can reach 1400 MPa or above, and the preparation method of the titanium alloy is simple, short in period and low in cost.

The invention discloses a preparation method of a strain channel FinFET, and belongs to the technical field of integrated circuit manufacturing. According to the method, after the Fin line is manufactured, amorphous silicon is generated through an injection amorphization method, the amorphous silicon is recrystallized after a strain medium layer is adopted for covering and high-temperature annealing is conducted, at the moment, tensile stress / compressive stress needed by an N / PMOS can be formed between the crystalline silicon and a strain medium, and then the strain medium material is selectively removed, so that preparation of the strain channel FinFET is achieved. According to the invention, lattice mismatch between the strain dielectric material and the crystalline silicon is utilized to generate tensile stress or compressive stress required by a FinFET device, N / PMOS channel strain is realized by using a single strain material, the process of channel stress engineering is simplified, the process complexity is reduced, and the method has the potential of being applied to technical nodes of 14 nm and above.

The invention provides a sound wave resonator, a preparation method thereof and a filter, and aims at sound waves with strong dispersion characteristics in a target mode, the influence of the thickness of a piezoelectric film on sound velocity far exceeds the duty ratio 2W / lambda of an interdigital transducer electrode. The thickness of a piezoelectric film corresponding to the lower part from a certain area at the tail end of an electrode finger overlapping area of the interdigital transducer to the tail end part of a bus bar is increased, so that the thickness of the piezoelectric film is thicker than that of a piezoelectric film corresponding to the middle part of the electrode finger overlapping area; therefore, the sound velocity of the target mode in the piezoelectric film in the thicker area is lower than the sound velocity of the target mode in the piezoelectric film in the thinner area, so that the transverse high-order mode is effectively inhibited, and the performance of the device is improved. Besides, the structure can suppress the transverse high-order mode only by increasing the thickness of the partial area of the piezoelectric film, the structure is simple, the preparation is easy, the requirement on the process precision is low, and the process complexity and the manufacturing cost can be effectively reduced on the premise of effectively ensuring the performance of the resonator.

The invention provides a power consumption optimization method, an integrated circuit and a chip. The method comprises the following steps: acquiring a first endpoint register with a time sequence violation in a load register based on a time sequence report of EDA (Electronic Design Automation); obtaining all first load registers driven by the ICG; acquiring a second endpoint register driven by the ICG and limiting the overall performance of the circuit according to the first load register and the first endpoint register; dividing each load register into a plurality of register files which are not mutually coherent logically according to combinational logic; and copying one ICG for each register file to drive the CP end of each load register in the register file. According to the scheme, the ICG copying function of the EDA tool is utilized, ICG copying and placement of the key registers influencing the overall performance of the circuit are achieved, and the time sequence of the path between the load registers can be optimized to the limit on the premise that the process complexity is not increased and the power consumption of the integrated circuit is saved.

The invention discloses an optical coupling packaging device, and belongs to the technical field of optoelectronic integration. The optical coupling packaging device comprises an interposer which comprises an optical device, a cavity, a first alignment structure and a first coupling structure, the first alignment structure and the first coupling structure are located in the cavity, and the first coupling structure is connected with the optical device; and the first optical chip is at least partially located in the cavity, the first optical chip comprises a second alignment structure and a second coupling structure, the second alignment structure and the first alignment structure are mutually embedded, and the second coupling structure and the first coupling structure are in coupling connection. According to the invention, high-precision alignment can be realized, the alignment error is reduced, the process complexity is reduced, the cost is reduced, the stability of optical signal transmission is improved, and the optical signal transmission loss is reduced.

The invention discloses a manufacturing method of a super junction device. The manufacturing method comprises the following steps: growing a first epitaxial layer; a plurality of trench gates are formed in a first epitaxial layer, gate conductive material layers outside gate trenches of the trench gates are all removed, and the top surfaces of the gate conductive material layers in the gate trenches are flat, so that the formation process of a subsequent second trench is ensured to be realized. And forming a well region and performing annealing. And performing photoetching and etching to form a plurality of second grooves, wherein the first epitaxial layer between the second grooves is used as a first conductive type column. And growing a second conductive type doped second epitaxial layer in the second groove, completely removing the second epitaxial layer outside the second groove, flattening the surface of the second epitaxial layer in the second groove, and forming a second conductive type column by the second epitaxial layer filled in the second groove. And a subsequent front process is completed, and a thermal process is set according to the requirement for controlling mutual diffusion of PN impurities of the super junction structure. And completing a back process. According to the invention, mutual diffusion of PN impurities of the super junction structure can be effectively controlled.

The embodiment of the invention discloses a traveling wave tube high-frequency assembly and an assembling method thereof, the traveling wave tube high-frequency assembly comprises a traveling wave tube high-frequency assembly, the high-frequency assembly comprises a composite tube shell and an all-metal slow wave structure arranged in the composite tube shell, the composite tube shell comprises an electron gun welding disc, a pole shoe, a spacer ring and a collector welding disc, and the electron gun welding disc, the pole shoe and the spacer ring are brazed together. The all-metal slow-wave structure is composed of a plurality of radial sub-cavities, and the radial sub-cavities are fixed in the composite tube shell through high-temperature diffusion welding. The high-frequency assembly does not need to use a thin-wall tube shell, is simple to assemble, can reduce the inner diameter of a magnetic system, increases bunching current, and further increases the output power under the condition that the voltage is not changed. The composite tube shell and the all-metal slow wave structure are matched through a circle, and the machining precision error can be 0.08 mm. The multiple radial sub-cavities can be fixed in the composite tube shell only through high-temperature diffusion welding, the technological process is simple, the assembly efficiency and precision are high, and the problem that the matching degree becomes poor due to the fact that welding flux flows into the slow-wave structure is solved.

The utility model discloses a pressure sensing composite current collector, a pole piece and a battery. The pressure sensing composite current collector comprises a pressure sensing layer, packaging layers and a metal layer, the pressure sensing layer comprises a pressure sensitive material layer and a lead, and the packaging layers are arranged on the two sides of the pressure sensitive material layer and wrap the pressure sensitive material layer. The pressure sensitive material layer is arranged on the packaging layer, the metal layer is arranged on one side, far away from the pressure sensitive material layer, of the packaging layer, the packaging layer is coated with the metal layer, one end of the lead is connected with the pressure sensitive material layer, and the other end of the lead penetrates through the packaging layer and the metal layer. According to the pressure sensing composite current collector, a sensing device is implanted in a lossless manner, the process complexity is reduced, the service life of a battery is prolonged, meanwhile, the charging and discharging operation states of the battery can be effectively monitored, abnormity can be effectively monitored, early warning can be performed in time, and the safety of the battery is ensured.

The invention belongs to the technical field of synthesis and application of organic semiconductor materials, and particularly relates to conjugated small molecule photoresist, a preparation method thereof and application of the conjugated small molecule photoresist in an organic thin film transistor. A compound of an alkyl chain with a photoreaction functional group is introduced to benzothienobenzothiophene, a polymerization reaction can be carried out under the assistance of a cross-linking agent by introducing an acetylene group, the polymerization reaction can be carried out by introducing diacetylene, meanwhile, the overall stacking structure of a BTBT core is not changed, and a channel is provided for efficient transmission of current carriers. Therefore, the material combines the functions of organic semiconductor molecules and traditional photoresist, and a new thought is provided for the design of the conjugated small-molecule semiconductor photoresist.

The invention provides a piezoelectric vibration sensor module. The piezoelectric vibration sensor module comprises a damping substrate cover plate, a damping substrate base, a mass block, a piezoelectric cantilever arm, a fixed frame and a charge (voltage) amplifier, wherein the mass block is suspended between the damping substrate cover plate and the damping substrate base through the piezoelectric cantilever arm, and the mass block receives an external vibration signal, drives the piezoelectric cantilever arm to vibrate and generates a piezoelectric induction signal, so that a vertical piezoelectric vibration sensor module is formed, and a vertical stopping function is realized; the impact resistance of the piezoelectric vibration sensor module is improved; and meanwhile, a plurality of opening module units are overlapped and combined with the damping substrate base, a plurality of piezoelectric induction signals are overlapped, and the signals are amplified through a charge (voltage) amplifier, so that the sensitivity and the reliability of the piezoelectric vibration sensor module are improved exponentially, the process complexity is reduced, and the tape-out cost is saved.

The invention discloses a manipulator for electrophoretic coating of a magnesium alloy hub, and belongs to the technical field of manipulators. In order to solve the problems of complex process and high equipment manufacturing cost in the conventional product, the invention provides the following technical scheme: the hub electrophoretic coating device comprises a motor mounting frame, and a butt clamp driving mechanism for fixing a hub and driving the hub to rotate and a coating positioning mechanism for electrophoretic coating of the hub are mounted on the motor mounting frame; the butt-clamping driving mechanism is composed of a butt-clamping assembly, an included angle adjusting assembly and a hub driving assembly, and the included angle adjusting assembly is located at the corner of the butt-clamping assembly and used for adjusting the fixed included angle of the butt-clamping assembly in advance. By arranging the butt clamp driving mechanism and the coating positioning mechanism, the manipulator capable of specially performing electrophoretic coating on the magnesium alloy hub is realized, comprehensive spraying can be completed only by one set of equipment, the process complexity is reduced, the efficiency of electrophoretic coating is improved, and the manufacturing cost is low.

The invention discloses a nanoscale lithium oxalate / carbon composite lithium supplement agent, a preparation method and application of the nanoscale lithium oxalate / carbon composite lithium supplement agent in a lithium ion battery. The lithium oxalate powder is prepared into the lithium oxalate saturated aqueous solution, then the amphiphilic surfactant is added, overgrowth of crystals of the lithium oxalate in the drying process can be limited, the particle size of the lithium oxalate is effectively reduced, and therefore the ion transmission path is shortened. Besides, after the carbon material is added, the polar group of the amphiphilic surfactant promotes the uniform distribution of the carbon material, so that a three-dimensional conductive network structure is constructed, the electron transmission path is effectively shortened by the structure, and the conductivity of the material is remarkably improved. The lithium supplement agent prepared by the invention has remarkable electrochemical performance, and the decomposition potential of the lithium supplement agent is successfully reduced to about 4.33 V, which conforms to the working voltage range of a positive electrode material and an electrolyte of a commercial lithium ion battery. The method provided by the invention has the advantages of simple operation and no need of additional introduction of a metal catalyst, and can effectively reduce the raw material cost.

The embodiment of the invention discloses a manufacturing method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a substrate which comprises an NMOS (N-channel Metal Oxide Semiconductor) device region and a PMOS (P-channel Metal Oxide Semiconductor) device region; forming a high dielectric constant dielectric layer covering the NMOS device region and the PMOS device region above the substrate; forming a gate stack structure above the high dielectric constant dielectric layer, wherein the gate stack structure is located in the NMOS device region and the PMOS device region; patterning the high-dielectric-constant dielectric layer to reserve the high-dielectric-constant dielectric layer in the NMOS device region and the high-dielectric-constant dielectric layer covered by the gate stack structure in the PMOS device region; and after isolation side walls are formed on the side walls of the gate stack structure to define boundaries of sigma trenches, forming the sigma trenches between the isolation side walls of the gate stack structure in the PMOS device region by using an etching process by taking the patterned high-dielectric-constant dielectric layer as a mask. According to the embodiment of the invention, the height difference between the pseudo gate of the PMOS device region and the pseudo gate of the NMOS device region is eliminated.

The utility model provides a pressure sensor riveting device for pressure sensor's shell and base connection fixed, the one end of shell is connected with base, including the top post, drives linear movement through drive assembly, the lateral wall of base and shell junction is provided with the clamping hole, the top post is coaxial with clamping hole, the top post applies pressure to the outside surface of shell, makes shell form the convex block that protrudes inwards, the convex block is clamped with clamping hole. Adopt mechanical riveting to replace high accuracy laser welding, need not to depend on high power laser equipment and precision alignment system, significantly reduce equipment investment and process complexity, solved the problem that traditional full welding led, more fit the working condition characteristics of supermicro sensor low intensity demand.

The invention belongs to the field of solid electrolytes of all-solid-state lithium ion batteries, and particularly relates to a fluoride solid electrolyte, a preparation method of the fluoride solid electrolyte and application of the fluoride solid electrolyte in all-solid-state lithium ion batteries and composite positive electrodes of the all-solid-state lithium ion batteries, and the fluoride solid electrolyte is obtained by one-step synthesis of LiCl, Li2O and FeF3 through high-energy ball milling reaction; the ionic conductivity of the fluoride solid-state electrolyte reaches 2.8 mS cm <-1 >, and the fluoride solid-state electrolyte is used as a positive electrode supporting electrolyte in an all-solid-state lithium battery, so that the energy density of an electrode layer is improved; the fluoride solid electrolyte material has reversible capacity exceeding 250 mAh g <-1 > at the same time; when the fluoride solid electrolyte capable of contributing capacity is used as a positive electrode supporting electrolyte to be matched with a ternary positive electrode material, the specific capacity of the positive electrode layer of the all-solid-state lithium battery is improved by 20% or above, the energy density is improved by 15% or above, and the cycling stability of the all-solid-state lithium battery under high cut-off voltage is remarkably improved.

The invention provides an electrolytic capacitor, a circuit board, a remote controller, an air conditioning system and a circuit board preparation technology, the electrolytic capacitor is used for being installed on the circuit board, and the circuit board is provided with an installation groove; the electrolytic capacitor comprises an extension pin, and the extension pin is mounted in the mounting groove; wherein the electrolytic capacitor is used for being identified and sucked by the chip mounter and is inversely erected on the circuit board. The electrolytic capacitor is inversely erected on the circuit board through the extension pins, the body height of the electrolytic capacitor on the front face of the circuit board is reduced, the electrolytic capacitor can be suitable for more application scenes, and the electrolytic capacitor can be identified and sucked by a chip mounter and is erected on the circuit board in a chip mounting mode, so that the chip mounting efficiency is improved. Compared with the prior art, full automation and manufacturability are improved, labor and maintenance cost is reduced, wave soldering procedures caused by plug-in electrolytic capacitors are reduced, resources can be saved, preparation procedures and process complexity are reduced, quality problems caused by welding are avoided, and the quality of the circuit board is improved.

The application discloses a packaging material, which comprises a weather-resistant layer, a supporting layer, a conductive layer and a buffer layer. The supporting layer is connected to one side of the weather-resistant layer, and the conductive layer is connected to the side of the supporting layer away from the weather-resistant layer. The conductive layer is a patterned layer, and the conductive layer comprises a hollow part. The projection of the hollow part on the supporting layer is defined as a hollow projection. The buffer layer is a patterned layer, and the buffer layer is configured to be at least partially inlaid in the hollow part of the conductive layer. The buffer layer is configured to be at least partially protruded from the conductive layer. The projection of the buffer layer on the supporting layer is defined as a buffer projection. The hollow projection and the buffer projection substantially coincide. By using the packaging material to package a photovoltaic module, the structure of the photovoltaic module and the process complexity during packaging can be simplified.

A method for manufacturing high-strength, hydrogen-embrittlement-resistant bolts based on microsphere shot peening, and the bolts themselves, are disclosed. The manufacturing method includes: S1, cold heading and thread rolling of alloy structural steel billets to obtain bolt forming parts; S2, surface cleaning of the bolt forming parts, followed by overall surface peening with microspheres driven by high-pressure air; after overall peening, targeted strengthening peening treatment is performed on stress concentration areas such as thread roots, undercut grooves, and flange transition corners to obtain reinforced bolt parts; S3, the reinforced bolt parts are cleaned, dried, and phosphated to obtain finished bolt parts. This design, through a "overall + targeted" composite microsphere shot peening strategy, introduces a uniform residual compressive stress field and a micron-level fine-grained plastic deformation layer on the bolt surface, forming a thicker strengthening layer in stress concentration areas, significantly improving the fatigue strength and delayed fracture resistance of high-strength bolts, while ensuring uniform surface roughness and stable assembly friction coefficient.

The embodiment of the invention discloses a preparation method of a semiconductor structure, relates to the technical field of semiconductors, and can reduce the manufacturing process complexity and cost of a mask layer and improve the product performance of the semiconductor structure prepared based on the mask layer. The preparation method comprises the following steps: providing a semiconductor substrate; forming a sacrificial structure on one side of the semiconductor substrate; the surface of one side, far away from the semiconductor substrate, of the sacrificial structure is higher than the surface of the semiconductor substrate in the direction perpendicular to and far away from the semiconductor substrate. And forming an initial hard mask layer on the side, away from the semiconductor substrate, of the sacrificial structure. And grinding one side of the initial hard mask layer away from the semiconductor substrate until the surface of one side of the sacrificial structure away from the semiconductor substrate is exposed. And removing the sacrificial structure, and reserving a part of the initial hard mask layer which does not cover the sacrificial structure to form a hard mask layer with an opening. The semiconductor substrate is etched using the hard mask layer.

The invention belongs to the technical field of synthesis and preparation of aluminum nitride, and discloses a controllable and extensible preparation method of a one-dimensional aluminum nitride nanowire / nanotube, which comprises the following steps: (1) uniformly mixing a solid aluminum source and a solid nitrogen source, transferring the mixture into a rotatable crucible, transferring the crucible into a tubular furnace, sealing the tubular furnace, and carrying out heat preservation for 2-3 hours; vacuumizing and then introducing protective gas; (2) under the condition that protective gas is continuously introduced, the tubular furnace is heated to a preset target temperature for a nitridation reaction, and the nitridation reaction is carried out under the condition that a crucible rotates at a constant rotating speed; and after the reaction is finished, cooling the tubular furnace and stopping the rotation of the crucible to obtain a one-dimensional aluminum nitride nanowire or nanotube product. According to the method, the solid aluminum source and the solid nitrogen source are used as raw materials, and the crucible rotation is introduced during the nitridation reaction to carry out dynamic enabling improvement, so that the single-crystal aluminum nitride nanowire or nanotube with high purity and uniform morphology can be efficiently synthesized.

The utility model relates to the technical field of kitchen utensils, and discloses a fire distributor, a burner and a stove, the fire distributor comprises a fire distributor main body and a shielding piece, the fire distributor main body comprises a fire distributor inner ring and a fire distributor outer ring, the fire distributor outer ring is arranged on the periphery of the fire distributor inner ring at intervals, and the shielding piece is arranged between the fire distributor inner ring and the fire distributor outer ring. The shielding part comprises an inner shielding part and an outer shielding part, the inner shielding part is arranged on the outer wall of the inner ring of the fire distributor, the outer shielding part is arranged on the inner wall of the outer ring of the fire distributor, the inner shielding part and the outer shielding part are oppositely arranged and form a shielding cavity, and the tip end of the ignition needle extends out of the shielding cavity. The shielding pieces are beneficial to enhancing the grounding conduction capacity of the ignition needle, when the ignition needle leaks electricity or ignites intermittently, the ignition needle always discharges electricity at the point, namely, the electricity is discharged above the inner fire cover and the outer fire cover, in addition, the inner shielding piece and the outer shielding piece are arranged on the inner ring of the fire distributor and the outer ring of the fire distributor respectively, and installation is easy and convenient.

The application provides a method for determining the type of defects in a single crystal silicon wafer, comprising the following steps: measuring the particles in the As-Grown state silicon wafer by LST to obtain a first measurement result, and determining a V-rich region according to the first measurement result and a first preset density value; and performing heat treatment on the silicon wafer, and again measuring the particles in the silicon wafer by LST to obtain a second measurement result, and determining a Pv region, an I-rich region and a Pi region according to the second measurement result, a second preset density value and a third preset density value, so as to accurately and effectively distinguish the four region types of the V-rich region, the Pv region, the Pi region and the I-rich region in the single crystal silicon wafer by using the particle density, the test result is obviously distinguished, the test stability is high and the repeatability is high, and the requirement of the defect partition type on the silicon wafer is reduced.