155results about How to "Reduce process complexity" patented technology

The invention discloses an automatic testing method oriented to a large industrial system RPC API (Remote Procedure Call Application Program Interface). According to the method, API documents and historical calling data of tenants are used as input, and automatic API testing is achieved. The method mainly comprises three stages of API dependency model construction, API test sequence generation and API sequence parameter rendering. The construction of the API dependency model is realized based on an API document and historical calling data of tenants, and comprises three steps: static analysis of the API document, parameter clustering based on a large model, and dependency relationship filtering based on the historical calling data of the tenants. The generation of the API test sequence is based on an API dependency graph generated in the previous stage, a to-be-tested API is taken as a starting point, a front dependency API is searched for continuously in an iteration mode to generate the sequence, and finally filtering is carried out through CRUD semantics. The rendering of the API sequence parameters is realized by constructing a dynamic dictionary and recommending large model parameters aiming at the API sequence generated in the previous stage.

The invention discloses a method for preparing a low-temperature flue gas denitration catalyst by utilizing electrolytic manganese anode mud, comprising the following steps: step one, material selection; step two, drying and grinding; step three, leaching; step four, solid-liquid separation; step five, multiple washing and filtering; wherein in the above step one, firstly, electrolytic manganese anode mud is selected as the raw material for preparing the low-temperature flue gas denitration catalyst; wherein in the above step two, the electrolytic manganese anode mud selected in step one is placed in a drying box for drying treatment. The invention has a simple synthesis method, and the raw materials used are from industrial waste residues, thereby reducing the impact on the environment. At the same time, the synthesized catalyst is conducive to efficient operation at ultra-low temperature, expanding the application scenarios of the catalyst, and at the same time, the electrolytic manganese anode mud is modified by soluble chloride salt, and the modification treatment of the electrolytic manganese anode mud is utilized, thereby greatly reducing the complexity of the subsequent process for preparing the catalyst.

The invention discloses a manufacturing method of a wireless charging coil and the wireless charging coil. The manufacturing method comprises the following steps: laminating a photosensitive adhesive film on a first surface of a pure copper foil; pressing a dry film with a coil pattern on the second surface of the pure copper foil; etching the pure copper foil from the second surface of the pure copper foil, and removing the pure copper foil outside the dry film coverage area; removing the dry film, and laminating a first flexible protective film on the second surface of the pure copper foil; and removing the photosensitive adhesive film, and laminating a second flexible protective film on the first surface of the pure copper foil. According to the technical scheme of the embodiment of the invention, the abnormal risk of subsequent processing of the product can be effectively reduced, the pure copper foil is protected in the manufacturing process, the production efficiency and the yield can be effectively improved, and the cost and the process complexity are effectively reduced.

The utility model discloses a battery shell and a single battery, the battery shell comprises a metal main shell and a metal cover body, and the metal main shell is provided with an accommodating cavity for accommodating a core package and an opening communicated with the accommodating cavity; the metal cover body is inserted into the containing cavity through the opening and abuts against the bottom of the containing cavity to seal the opening, and the metal main shell and the metal cover body are connected at the opening in a welded mode. According to the utility model, by arranging the battery shell into the metal main shell and the metal cover body which are separated from each other, when the metal main shell is connected with the metal cover body, the metal cover body is partially inserted into the accommodating cavity, so that the metal cover body is partially propped against the bottom of the accommodating cavity for positioning; and then the metal cover body and the metal main shell are welded through the welding head. The welding positions of the metal cover body and the metal main shell are on the same plane, so that the metal main shell does not need to be turned over by a welding clamp in the welding process of the welding head, the process complexity of the battery shell is further reduced, and the reject ratio of the single battery can be reduced.

The invention discloses a neodymium-iron-boron magnetic ring forming device, a neodymium-iron-boron magnetic ring and a preparation method of the neodymium-iron-boron magnetic ring. The neodymium iron boron magnetic ring forming device comprises an upper punch, a female die, a lower outer punch and a lower inner punch. The neodymium-iron-boron magnetic ring forming device can complete multiple procedures such as cold pressing, hot pressing, pre-deformation and thermal deformation extrusion at a time, the process complexity is reduced, repeated heating is avoided, and the performance of the thermal deformation neodymium-iron-boron magnetic ring is improved.

The present invention provides a memory device and a manufacturing method thereof. The memory device includes a substrate and an electronic fuse structure. The substrate includes an array area and an electronic fuse area, and the electronic fuse area of ​​the substrate has an electronic fuse groove. The electronic fuse structure includes a first gate oxide layer, a plurality of doped regions, a dummy buried word line and an electronic fuse gate. The first gate oxide layer is formed on the surface of the electronic fuse groove. These doped regions are respectively formed in the substrate on opposite sides outside the electronic fuse groove and are in contact with the first gate oxide layer. The dummy buried word line is formed on the first gate oxide layer. The electronic fuse gate is formed on the dummy buried word line and is in contact with the first gate oxide layer. The dummy buried word line is electrically isolated from the electronic fuse gate.

The invention provides a power consumption optimization method, an integrated circuit and a chip. The method comprises the following steps: acquiring a first endpoint register with a time sequence violation in a load register based on a time sequence report of EDA (Electronic Design Automation); obtaining all first load registers driven by the ICG; acquiring a second endpoint register driven by the ICG and limiting the overall performance of the circuit according to the first load register and the first endpoint register; dividing each load register into a plurality of register files which are not mutually coherent logically according to combinational logic; and copying one ICG for each register file to drive the CP end of each load register in the register file. According to the scheme, the ICG copying function of the EDA tool is utilized, ICG copying and placement of the key registers influencing the overall performance of the circuit are achieved, and the time sequence of the path between the load registers can be optimized to the limit on the premise that the process complexity is not increased and the power consumption of the integrated circuit is saved.

The invention discloses an optical coupling packaging device, and belongs to the technical field of optoelectronic integration. The optical coupling packaging device comprises an interposer which comprises an optical device, a cavity, a first alignment structure and a first coupling structure, the first alignment structure and the first coupling structure are located in the cavity, and the first coupling structure is connected with the optical device; and the first optical chip is at least partially located in the cavity, the first optical chip comprises a second alignment structure and a second coupling structure, the second alignment structure and the first alignment structure are mutually embedded, and the second coupling structure and the first coupling structure are in coupling connection. According to the invention, high-precision alignment can be realized, the alignment error is reduced, the process complexity is reduced, the cost is reduced, the stability of optical signal transmission is improved, and the optical signal transmission loss is reduced.

The invention discloses a manufacturing method of a super junction device. The manufacturing method comprises the following steps: growing a first epitaxial layer; a plurality of trench gates are formed in a first epitaxial layer, gate conductive material layers outside gate trenches of the trench gates are all removed, and the top surfaces of the gate conductive material layers in the gate trenches are flat, so that the formation process of a subsequent second trench is ensured to be realized. And forming a well region and performing annealing. And performing photoetching and etching to form a plurality of second grooves, wherein the first epitaxial layer between the second grooves is used as a first conductive type column. And growing a second conductive type doped second epitaxial layer in the second groove, completely removing the second epitaxial layer outside the second groove, flattening the surface of the second epitaxial layer in the second groove, and forming a second conductive type column by the second epitaxial layer filled in the second groove. And a subsequent front process is completed, and a thermal process is set according to the requirement for controlling mutual diffusion of PN impurities of the super junction structure. And completing a back process. According to the invention, mutual diffusion of PN impurities of the super junction structure can be effectively controlled.

The utility model discloses a pressure sensing composite current collector, a pole piece and a battery. The pressure sensing composite current collector comprises a pressure sensing layer, packaging layers and a metal layer, the pressure sensing layer comprises a pressure sensitive material layer and a lead, and the packaging layers are arranged on the two sides of the pressure sensitive material layer and wrap the pressure sensitive material layer. The pressure sensitive material layer is arranged on the packaging layer, the metal layer is arranged on one side, far away from the pressure sensitive material layer, of the packaging layer, the packaging layer is coated with the metal layer, one end of the lead is connected with the pressure sensitive material layer, and the other end of the lead penetrates through the packaging layer and the metal layer. According to the pressure sensing composite current collector, a sensing device is implanted in a lossless manner, the process complexity is reduced, the service life of a battery is prolonged, meanwhile, the charging and discharging operation states of the battery can be effectively monitored, abnormity can be effectively monitored, early warning can be performed in time, and the safety of the battery is ensured.

The invention belongs to the technical field of synthesis and application of organic semiconductor materials, and particularly relates to conjugated small molecule photoresist, a preparation method thereof and application of the conjugated small molecule photoresist in an organic thin film transistor. A compound of an alkyl chain with a photoreaction functional group is introduced to benzothienobenzothiophene, a polymerization reaction can be carried out under the assistance of a cross-linking agent by introducing an acetylene group, the polymerization reaction can be carried out by introducing diacetylene, meanwhile, the overall stacking structure of a BTBT core is not changed, and a channel is provided for efficient transmission of current carriers. Therefore, the material combines the functions of organic semiconductor molecules and traditional photoresist, and a new thought is provided for the design of the conjugated small-molecule semiconductor photoresist.

The invention provides a piezoelectric vibration sensor module. The piezoelectric vibration sensor module comprises a damping substrate cover plate, a damping substrate base, a mass block, a piezoelectric cantilever arm, a fixed frame and a charge (voltage) amplifier, wherein the mass block is suspended between the damping substrate cover plate and the damping substrate base through the piezoelectric cantilever arm, and the mass block receives an external vibration signal, drives the piezoelectric cantilever arm to vibrate and generates a piezoelectric induction signal, so that a vertical piezoelectric vibration sensor module is formed, and a vertical stopping function is realized; the impact resistance of the piezoelectric vibration sensor module is improved; and meanwhile, a plurality of opening module units are overlapped and combined with the damping substrate base, a plurality of piezoelectric induction signals are overlapped, and the signals are amplified through a charge (voltage) amplifier, so that the sensitivity and the reliability of the piezoelectric vibration sensor module are improved exponentially, the process complexity is reduced, and the tape-out cost is saved.

The invention discloses a nanoscale lithium oxalate / carbon composite lithium supplement agent, a preparation method and application of the nanoscale lithium oxalate / carbon composite lithium supplement agent in a lithium ion battery. The lithium oxalate powder is prepared into the lithium oxalate saturated aqueous solution, then the amphiphilic surfactant is added, overgrowth of crystals of the lithium oxalate in the drying process can be limited, the particle size of the lithium oxalate is effectively reduced, and therefore the ion transmission path is shortened. Besides, after the carbon material is added, the polar group of the amphiphilic surfactant promotes the uniform distribution of the carbon material, so that a three-dimensional conductive network structure is constructed, the electron transmission path is effectively shortened by the structure, and the conductivity of the material is remarkably improved. The lithium supplement agent prepared by the invention has remarkable electrochemical performance, and the decomposition potential of the lithium supplement agent is successfully reduced to about 4.33 V, which conforms to the working voltage range of a positive electrode material and an electrolyte of a commercial lithium ion battery. The method provided by the invention has the advantages of simple operation and no need of additional introduction of a metal catalyst, and can effectively reduce the raw material cost.

The embodiment of the invention discloses a manufacturing method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a substrate which comprises an NMOS (N-channel Metal Oxide Semiconductor) device region and a PMOS (P-channel Metal Oxide Semiconductor) device region; forming a high dielectric constant dielectric layer covering the NMOS device region and the PMOS device region above the substrate; forming a gate stack structure above the high dielectric constant dielectric layer, wherein the gate stack structure is located in the NMOS device region and the PMOS device region; patterning the high-dielectric-constant dielectric layer to reserve the high-dielectric-constant dielectric layer in the NMOS device region and the high-dielectric-constant dielectric layer covered by the gate stack structure in the PMOS device region; and after isolation side walls are formed on the side walls of the gate stack structure to define boundaries of sigma trenches, forming the sigma trenches between the isolation side walls of the gate stack structure in the PMOS device region by using an etching process by taking the patterned high-dielectric-constant dielectric layer as a mask. According to the embodiment of the invention, the height difference between the pseudo gate of the PMOS device region and the pseudo gate of the NMOS device region is eliminated.

The utility model provides a pressure sensor riveting device for pressure sensor's shell and base connection fixed, the one end of shell is connected with base, including the top post, drives linear movement through drive assembly, the lateral wall of base and shell junction is provided with the clamping hole, the top post is coaxial with clamping hole, the top post applies pressure to the outside surface of shell, makes shell form the convex block that protrudes inwards, the convex block is clamped with clamping hole. Adopt mechanical riveting to replace high accuracy laser welding, need not to depend on high power laser equipment and precision alignment system, significantly reduce equipment investment and process complexity, solved the problem that traditional full welding led, more fit the working condition characteristics of supermicro sensor low intensity demand.

The invention provides an electrolytic capacitor, a circuit board, a remote controller, an air conditioning system and a circuit board preparation technology, the electrolytic capacitor is used for being installed on the circuit board, and the circuit board is provided with an installation groove; the electrolytic capacitor comprises an extension pin, and the extension pin is mounted in the mounting groove; wherein the electrolytic capacitor is used for being identified and sucked by the chip mounter and is inversely erected on the circuit board. The electrolytic capacitor is inversely erected on the circuit board through the extension pins, the body height of the electrolytic capacitor on the front face of the circuit board is reduced, the electrolytic capacitor can be suitable for more application scenes, and the electrolytic capacitor can be identified and sucked by a chip mounter and is erected on the circuit board in a chip mounting mode, so that the chip mounting efficiency is improved. Compared with the prior art, full automation and manufacturability are improved, labor and maintenance cost is reduced, wave soldering procedures caused by plug-in electrolytic capacitors are reduced, resources can be saved, preparation procedures and process complexity are reduced, quality problems caused by welding are avoided, and the quality of the circuit board is improved.

The application discloses a packaging material, which comprises a weather-resistant layer, a supporting layer, a conductive layer and a buffer layer. The supporting layer is connected to one side of the weather-resistant layer, and the conductive layer is connected to the side of the supporting layer away from the weather-resistant layer. The conductive layer is a patterned layer, and the conductive layer comprises a hollow part. The projection of the hollow part on the supporting layer is defined as a hollow projection. The buffer layer is a patterned layer, and the buffer layer is configured to be at least partially inlaid in the hollow part of the conductive layer. The buffer layer is configured to be at least partially protruded from the conductive layer. The projection of the buffer layer on the supporting layer is defined as a buffer projection. The hollow projection and the buffer projection substantially coincide. By using the packaging material to package a photovoltaic module, the structure of the photovoltaic module and the process complexity during packaging can be simplified.

A method for manufacturing high-strength, hydrogen-embrittlement-resistant bolts based on microsphere shot peening, and the bolts themselves, are disclosed. The manufacturing method includes: S1, cold heading and thread rolling of alloy structural steel billets to obtain bolt forming parts; S2, surface cleaning of the bolt forming parts, followed by overall surface peening with microspheres driven by high-pressure air; after overall peening, targeted strengthening peening treatment is performed on stress concentration areas such as thread roots, undercut grooves, and flange transition corners to obtain reinforced bolt parts; S3, the reinforced bolt parts are cleaned, dried, and phosphated to obtain finished bolt parts. This design, through a "overall + targeted" composite microsphere shot peening strategy, introduces a uniform residual compressive stress field and a micron-level fine-grained plastic deformation layer on the bolt surface, forming a thicker strengthening layer in stress concentration areas, significantly improving the fatigue strength and delayed fracture resistance of high-strength bolts, while ensuring uniform surface roughness and stable assembly friction coefficient.

The invention belongs to the technical field of synthesis and preparation of aluminum nitride, and discloses a controllable and extensible preparation method of a one-dimensional aluminum nitride nanowire / nanotube, which comprises the following steps: (1) uniformly mixing a solid aluminum source and a solid nitrogen source, transferring the mixture into a rotatable crucible, transferring the crucible into a tubular furnace, sealing the tubular furnace, and carrying out heat preservation for 2-3 hours; vacuumizing and then introducing protective gas; (2) under the condition that protective gas is continuously introduced, the tubular furnace is heated to a preset target temperature for a nitridation reaction, and the nitridation reaction is carried out under the condition that a crucible rotates at a constant rotating speed; and after the reaction is finished, cooling the tubular furnace and stopping the rotation of the crucible to obtain a one-dimensional aluminum nitride nanowire or nanotube product. According to the method, the solid aluminum source and the solid nitrogen source are used as raw materials, and the crucible rotation is introduced during the nitridation reaction to carry out dynamic enabling improvement, so that the single-crystal aluminum nitride nanowire or nanotube with high purity and uniform morphology can be efficiently synthesized.

The application provides a method for determining the type of defects in a single crystal silicon wafer, comprising the following steps: measuring the particles in the As-Grown state silicon wafer by LST to obtain a first measurement result, and determining a V-rich region according to the first measurement result and a first preset density value; and performing heat treatment on the silicon wafer, and again measuring the particles in the silicon wafer by LST to obtain a second measurement result, and determining a Pv region, an I-rich region and a Pi region according to the second measurement result, a second preset density value and a third preset density value, so as to accurately and effectively distinguish the four region types of the V-rich region, the Pv region, the Pi region and the I-rich region in the single crystal silicon wafer by using the particle density, the test result is obviously distinguished, the test stability is high and the repeatability is high, and the requirement of the defect partition type on the silicon wafer is reduced.

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and aims to solve the problem of non-uniform display of the display panel. The display panel is provided with a fan-out area; the fan-out area comprises a first area and second areas located on the two opposite sides of the first area. The first area and the second area are arranged in the first direction; the display panel comprises a plurality of fan-out lines; the plurality of fan-out lines comprise a plurality of first-type fan-out lines and a plurality of second-type fan-out lines; the plurality of first-type fan-out lines are located in the first area, and the plurality of second-type fan-out lines are located in the second area; each first-type fan-out line in the plurality of first-type fan-out lines comprises a first winding part, and the size of the area occupied by the first winding part in the second direction is smaller than the line length of the first winding part; every two adjacent first fan-out lines in the first direction are arranged on different layers. In the thickness direction of the display panel, orthographic projections of the first winding parts of every two adjacent first fan-out lines on the plane where the display panel is located are at least partially overlapped.

The present disclosure relates to a method for manufacturing a photovoltaic module and a photovoltaic module. The method includes: providing a front packaging structure, a photovoltaic cell, and a back sheet, the front packaging structure including a cover plate and a packaging layer; forming an insulating layer and forming through holes on a surface of at least one side of the photovoltaic cell, so that positions of the through holes correspond to electrode lines of the photovoltaic cell; forming a conductive layer on the back sheet; applying a conductive adhesive in the through holes and / or on the conductive layer; connecting the back sheet to the photovoltaic cell so that the insulating layer fits the conductive layer and the conductive adhesive electrically connects the electrode lines and the conductive layer through the through holes; forming the packaging layer on a side of the photovoltaic cell away from the back sheet; arranging the cover plate on a side of the packaging layer away from the photovoltaic cell; and laminating the cover plate, the packaging layer, the photovoltaic cell, and the back sheet to form the photovoltaic module. According to the method for manufacturing a photovoltaic module provided in the present disclosure, process complexity of the photovoltaic module can be reduced, so that process steps are easier to implement.

The invention relates to the technical field of photoresist film-forming resin preparation, and discloses KrF photoresist film-forming resin and a preparation method and application thereof.The preparation method comprises the steps that 4-acetoxystyrene monomers or 4-acetoxystyrene monomers and other comonomers are filtered and then added into a dispersing agent, stirring is conducted, and the KrF photoresist film-forming resin is obtained; adding an organic photocatalyst and a chain transfer agent, and mixing to obtain a mixed solution; introducing inert gas into the mixed solution, irradiating the mixed solution under the condition of visible light, and reacting to obtain a polymer solution; and separating out the polymerization liquid, drying, adding ammonia water or a hydrazine hydrate solution, and reacting to obtain the KrF photoresist film-forming resin of which the molecular weight distribution is less than 1.2. By adopting a photo-initiation mode, on one hand, the energy consumption in the polymerization process can be reduced, and the reaction conditions are mild; on the other hand, the preparation process of the polymer can be well controlled in time and space, and the inter-batch stability is ensured.

This application provides a semiconductor laser with a ridge-side integrated PN junction temperature control layer and its fabrication method, relating to the field of semiconductor laser technology. The semiconductor laser includes a substrate; an epitaxial structure formed on one side of the substrate along a first direction; the epitaxial structure having a first surface facing away from the substrate; a ridge waveguide layer formed on the first surface and extending along a second direction; a temperature control region formed on the first surface and located on one side of the ridge waveguide layer along a third direction; the temperature control region includes a P-type control layer and an N-type control layer, which form a PN junction. In this application embodiment, because the PN junction has high resistance and small footprint under static operation, it is possible to achieve efficient thermal tuning while reducing the process complexity of the thermal tuning scheme, improving structural reliability, and reducing the footprint, thereby meeting the industrial demands for high integration, low cost, and high reliability.

The embodiment of the invention discloses an optical waveguide and augmented reality equipment. According to one specific embodiment, the optical waveguide comprises a grating, a first substrate and a second substrate, wherein the grating is arranged on at least one surface of the first substrate, and the second substrate is arranged on at least one surface of the first substrate; the refractive index of the second substrate is lower than that of the first substrate. According to the embodiment, secondary diffraction of light in the optical waveguide is avoided, and the brightness loss of the optical waveguide is reduced.

The application discloses a kind of without heating regeneration carbon dioxide normal temperature removal process and system, belong to natural gas decarburization field;A kind of without heating regeneration carbon dioxide normal temperature removal process, comprising the following steps:S1, raw material gas pretreatment;S2, CO2 absorption;S3, rich liquid flash evaporation;S4, lean liquid regeneration;S5, material circulation;The application is effectively solved by the absorption part of being set, the pain point that edge filler reaction is not sufficient, the low life of central filler;Can shake and scatter adhesion filler ball, clean filter hole impurity, avoid filter hole blockage, further improve gas-liquid mass transfer efficiency;Can buffer knock impact force, prevent that filler plate is damaged;Can effectively protect electric telescopic rod, and maintenance is convenient, need not to disassemble whole tower body, shorten maintenance cycle, guarantee production continuity;Can avoid liquid flooding, channeling phenomenon.

The application discloses a three-core UTP cable, a three-core UTP wire harness and a camera module, comprising a differential signal line pair, a ground signal line, a filler and an outer insulation layer, the outer insulation layer wrapping the differential signal line pair, the ground signal line and the filler, and the filler being located between the differential signal line pair, the ground signal line and the outer insulation layer; the differential signal line pair comprises a first differential signal line and a second differential signal line, and the first differential signal line and the second differential signal line are twisted by a double-twisted wire structure; and the differential signal line pair and the ground signal line are arranged at intervals. The application provides a more stable and reliable grounding path, can effectively conduct electrostatic charges, avoids accumulation of static electricity on the camera module, and can effectively solve the ESD failure problem of the camera module based on the UTP wire harness.

The invention discloses a manufacturing method of a super junction device. The manufacturing method comprises the following steps: growing a first epitaxial layer; and injecting a first P-type impurity into a surface region of the first epitaxial layer in a first selected region, wherein the first selected region at least comprises a partial region, close to the transition region, of the terminal region. And forming a trench gate. And forming a well region and performing annealing. And forming a second groove. And growing a P-type doped second epitaxial layer in the second groove, removing the second epitaxial layer outside the second groove, and flattening the surface of the second epitaxial layer in the second groove. And completing a subsequent front process and setting a thermal process according to the requirement of controlling PN impurity mutual diffusion of the super junction structure, wherein the subsequent front process comprises the step of forming a protective epoxy film covering the inner side region of a cut-off region of the transition region and the terminal region. And completing a back process. According to the invention, mutual diffusion of PN impurities of the super junction structure can be effectively controlled, the reliability of a product can be improved, PN balance of a terminal region can be improved, BVdss of a device and consistency of the BVdss are improved, and the EAS capability is improved.

A PCB and a processing method thereof, the method comprising: processing through holes on at least two PCB sub-boards respectively, the through holes passing through the PCB sub-boards to which they belong and including first-type through holes and second-type through holes; forming solder plate layers on adjacent surfaces of every two adjacent PCB sub-boards respectively, the pads in the solder plate layers corresponding one-to-one with the first-type through holes on the PCB sub-boards to which they belong and realizing electrical connection; performing welding processing on the solder plate layers of the adjacent PCB sub-boards; wherein the first-type through holes are used to form electrical connections between adjacent PCB sub-boards, and the second-type through holes are used to form electrical connections inside and on the surface of the PCB sub-boards to which they belong. The present invention can effectively reduce process complexity and production costs, and combine the various PCB sub-boards through welding processing.