143 results about "Process patterns" patented technology

A system for intelligent monitoring and management of an electrical system is disclosed. The system includes a data acquisition component, a power analytics server and a client terminal. The data acquisition component acquires real-time data output from the electrical system. The power analytics server is comprised of a real-time energy pricing engine, virtual system modeling engine, an analytics engine, a machine learning engine and a schematic user interface creator engine. The real-time energy pricing engine generates real-time utility power pricing data. The virtual system modeling engine generates predicted data output for the electrical system. The analytics engine monitors real-time data output and predicted data output of the electrical system. The machine learning engine stores and processes patterns observed from the real-time data output and the predicted data output to forecast an aspect of the electrical system.

A method for fabricating an interference display unit is provided. A first plate and a sacrificial layer are formed in order on a substrate and at least two openings are formed in the first plate and the sacrificial layer. A photoresist layer is spin-coated on the sacrificial layer and fills the openings. A photolithographic process patterns the photoresist layer to define a support with an arm. A second plate is formed on the sacrificial layer and posts. The arm's stress is released through a thermal process. The position of the arm is shifted and the distance between the first plate and the second plate is therefore defined. Finally, The sacrificial layer is removed.

A system for real-time modeling of electrical system performance is disclosed. The system includes a data acquisition component, a power analytics server and a client terminal. The power analytics server is comprised of a virtual system modeling engine, an analytics engine and a power system simulation engine. The virtual system modeling engine is configured to generate predicted data output utilizing a first virtual system model. The analytics engine is configured to synchronize the first virtual system model when a difference between the real-time data output and the predicted data output exceeds a threshold. The power system simulation engine is configured to store and process patterns and facilitate modification of parameters on the first virtual system model to create a second virtual system model; and forecast an aspect of the electrical system operating under parameters of the second virtual system model. The client terminal displays the forecasted aspects.

A system for conducting performing real-time harmonics analysis of an electrical power distribution and transmission system is disclosed. The system includes a data acquisition component, a power analytics server and a client terminal. The data acquisition component is communicatively connected to a sensor configured to acquire real-time data output from the electrical system. The power analytics server is communicatively connected to the data acquisition component and is comprised of a virtual system modeling engine, an analytics engine and a machine learning engine. The machine learning engine is configured to store and process patterns observed from the real-time data output and the predicted data output, forecasting harmonic distortions in the electrical system subjected to a simulated contingency event.

The invention provides a double-workbench drive laser processing machine and a processing method thereof, and relates to the technical field of laser precision processing equipment. The double-workbench drive laser processing machine is provided with a first workbench, a second workbench, a laser beam transfer device (LBDS), a vacuum adsorption chuck and an image acquisition device. The processing method comprises the following steps: carrying out P1 non-contraposition and P2 contraposition on the basis of a unified affine transformation model; mapping a workpiece coordinate space to a processing coordinate space, i.e. a first workbench processing coordinate and a second workbench processing coordinate; and transferring a CAD data pattern to the workpiece, thereby controlling a feature position error of the processed pattern within an ideal accuracy range. By using the invention, the working efficiency of the P1 procedure can be effectively enhanced and the problem of automatic visual contraposition accuracy caused by workpiece deformation in the P2 procedure can be effectively solved, thereby reducing the cost and enhancing the productive capacity. The invention has the advantages of simple structure, and unique principle and method. The invention is especially suitable to be used on a large-scale LTCC/HTCC production line of processing technology.

The invention relates to a method for preparing a micro-nano-scale patterned electrospun fiber membrane. The method comprises the following steps: A) using a computer to draw a required pattern through layout design software; B) inputting the pattern into a micro-electrical mechanical system and using the micro-electrical mechanical system to deposit metal onto a non-metal base material according to the input pattern so as to get a receiving plate with the micro-nano-scale pattern; and C) taking the receiving plate with the micro-nano-scale pattern as the receiving plate of an electrospinning device and performing electrostatic spinning so as to get the micro-nano-scale patterned electrospun fiber membrane. By adopting the method, the patterned electrospun fiber membrane with micro-nano-scale minimal unit size of the pattern can be prepared, and the patterned electrospun fiber membrane has good application prospects in repair and manufacturing of micro-electronic devices, sensors, ultrafine filters and human tissues. Furthermore, the preparation process is simple and convenient, the degree of automation is high and the processed pattern is precise, controllable and good in repeatability.

An image of an integrated circuit chip and optical kerf and their mirror image are formed within a single optical field. When a substrate pattern using this process is flipped over or reversed, the processed pattern appears the same as on the first side, equal to its own mirror image. Prior to the backside lithography, a portion of the second side is removed to allow detection of alignment marks on the first side from the second side of the substrate. Once the alignment marks are detected, the lithography continues as though the substrate was not flipped over at all.

The invention discloses a workflow static planning method based on a process mode, belonging to the technical field of middleware. The method is realized in one computer by the following steps: 1, analyzing a service target and an application scene from input information of a user; 2, carrying out service target- process mode to find a process mode which is most suitable for the current service target and the application scene; 3, if the process mode obtained in the step 2 contains a service target, invoking a matcher to match the process mode to obtain complete workflow definition without containing the service target; 4, adapting a planned process definition list; 5, optimizing the process definition; and 6, deploying the workflow definition to a workflow execution engine and starting the workflow execution engine. By utilizing the planning method, the workflow definition meeting the requirement is automatically planned according to the information submitted by the user so as to reduce the modeling difficulty of the service process and realize the multiplexing of the service process.

A method for calibrating photomask pattern includes providing a test photomask and transferring original pattern on test photomask to the first photoresist layer for obtaining multiple developed pattern then measuring out their first size, carrying out pattern micro process on developed pattern to obtain micro processed pattern then measuring out their second size, calculate out deviate of two said sizes and utilizing two said sizes and deviate as well as original plotting data to form a databank, using databank to set up optical near effect revision model then utilizing said model to calibrate original plotting data for obtaining calibrated plotting data.

There is disclosed a method of correcting a design pattern considering a process margin between layers of a semiconductor integrated circuit, including calculating a first pattern shape corresponding to a processed pattern shape of a first layer based on a first design pattern, calculating a second pattern shape corresponding to a processed pattern shape of a second layer based on a second design pattern, calculating a third pattern shape using a Boolean operation between the first and second pattern shapes, determining whether or not an evaluation value obtained from the third pattern shape satisfies a predetermined value, and correcting at least one of the first and second design patterns if it is determined that the evaluation value does not satisfy the predetermined value.

A synaptic connection element for connecting neuron elements inputs a plurality of pulsed signals from different neuron elements N1 through N4, effects a common modulation (time window integration or pulse phase/width modulation) on a plurality of predetermined signals among the plurality of pulse signals, and outputs the modulated pulse signals to different signal lines to a neuron element M1. A neural network for representing and processing pattern information by the pulse modulation is thereby downsized in scale.

The invention discloses a manufacturing method of a pattern ring of a segmented mold of a radial tyre. The manufacturing method comprises the following steps of: performing a CAD design on the pattern ring, establishing a 3D model of the pattern ring, then dividing the 3D model into corresponding single pattern blocks according to requirements, and simultaneously customizing a pattern ring blank, finishing preliminary works such as rough machining, heat treatment, reference plane machining and the like of the pattern ring; configuring a plurality of machine tools and completing the preparation work before production; establishing part processing cutter tracks required by each machine tool, generating semi-finishing, finishing and corner cleaning procedures of each pattern block according to the configured condition of the machine tools, and establishing a procedure list; executing the processing procedures according to a procedure list sequence; and assembling and debugging the plurality of processed pattern blocks. The manufacturing method has the advantages of simple process, difficult generation of thermal deformation on a workpiece during production, short production cycle, high production efficiency and high accuracy, and ensures the assembly accuracy of the a tyre mold.

Disclosed is a method for combining two plates in the fabrication process of an enclosure baseplate of a printed circuit or an integrated circuit. The method includes the following steps: splicing two chip plates through a bonding sheet so as to make a machining plate which is big in thickness, higher in rigidity and can satisfy common equipment machining requirements; processing pattern transfer to the spliced machining plate and developing a necessary circuit diagram of a conductor on the surface of the machining plate; developing an insulating medium layer and a conducting copper layer on the surface of the newly developed circuit diagram of the conductor through the method of lamination; repeating above processes so as to form a multilayer machining plate; separating the machining plate at two sides of the splicing sheet from the splicing sheet after the machining plate reaches certain thickness and rigidity, thus forming two machining plates; and respectively processing the two machining plates through regular lamination, boring, electroplating and pattern transfer techniques until the necessary circuit board and the enclosure baseplate are finished. The method requires no special equipment or machining tools and can reduce cost by a large margin and improve production efficiency and yield.

A method of generating a mask for use in an imaging process pattern. The method includes the steps of: (a) obtaining a desired target pattern having a plurality of features to be imaged on a substrate; (b) simulating a wafer image utilizing the target pattern and process parameters associated with a defined process; (c) defining at least one feature category; (d) identifying features in the target pattern that correspond to the at least one feature category, and recording an error value for each feature identified as corresponding to the at least one feature category; and (e) generating a statistical summary which indicates the error value for each feature identified as corresponding to the at least one feature category.

The invention discloses a method for preparing a periodic nanostructure with high aspect ratio. The method is characterized by comprising the following steps of: selecting a polished substrate; coating a layer of photoresist with the thickness of greater than or equal to 300 nm on the surface of the polished substrate by a spin-coating method; depositing a SiO2 film with the thickness of 20 nm on the surface of the photoresist by a magnetron sputtering method; coating a layer of high-resolution photoresist with the thickness of 50 to 100 nm on the surface of the SiO2 film by the spin-coating method; exposing and developing the surface high-resolution photoresist by utilizing laser interference photolithography; hardening the three-layer adhesive structure in a heating plate or a baking oven; selecting a fluorine-base gas; transferring a surface photoresist pattern to the SiO2 layer by utilizing reactive ion etching; selecting and using oxygen; taking the SiO2 layer as a hard mask layer; and transferring a pattern on the SiO2 layer to the bottom photoresist by utilizing the reactive ion etching to obtain a photoresist pattern with high resolution and high aspect ratio. The method has low cost, large area of processed pattern area, and a broad application prospect in the aspects of the manufacturing and the application research of sub-wavelength gratings and photonic crystals.

A direct-write system is provided which includes a stage for holding a substrate, a processing module for processing pattern data and generating instructions associated with the pattern data, and an exposure module that includes beams that are focused onto the substrate and a beam controller that controls the beams in accordance with the instructions. The processing module includes vertex pair processors each having bit inverters. Each vertex pair processor is operable to process a respective vertex pair of an input scan line to generate an output scan line. Each bit inverter is operable to invert a respective input bit of the input scan line to generate a respective output bit of the output scan line if a bit position is located between the respective vertex pair, otherwise the respective input bit is copied to the respective output bit. The instructions correspond to the output bits for each beam.