2244results about "Conductive material chemical/electrolytical removal" patented technology

A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires that may be embedded in a matrix. The conductive layer is optically clear, patternable and is suitable as a transparent electrode in visual display devices such as touch screens, liquid crystal displays, plasma display panels and the like.

A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires that may be embedded in a matrix. The conductive layer is optically clear, patternable and is suitable as a transparent electrode in visual display devices such as touch screens, liquid crystal displays, plasma display panels and the like.

A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.

An apparatus for detecting the end-point of an electropolishing process of a metal layer formed on a wafer includes an end-point detector. The end-point detector is disposed adjacent the nozzle used to electropolish the wafer. In one embodiment, the end-point detector is configured to measure the optical reflectivity of the portion of the wafer being electropolished.

A method and apparatus are provided for planarizing a material layer on a substrate. In one aspect, a method is provided for processing a substrate including forming a passivation layer on a substrate surface, polishing the substrate in an electrolyte solution, applying an anodic bias to the substrate surface, and removing material from at least a portion of the substrate surface. In another aspect, an apparatus is provided which includes a partial enclosure, polishing article, a cathode, a power source, a substrate carrier movably disposed above the polishing article, and a computer based controller to position a substrate in an electrolyte solution to form a passivation layer on a substrate surface, to polish the substrate in the electrolyte solution with the polishing article, and to apply an anodic bias to the substrate surface or polishing article to remove material from at least a portion of the substrate surface.

A front-and-back electrically conductive substrate includes a plurality of posts composed of a material that can be anisotropically etched and having an electrically conductive portion that has at least a first surface and a second surface that communicate with each other, and an insulative substrate that supports the plurality of posts.

Methods for forming a support frame for flexible leaflet heart valves from a starting blank include converting a two-dimensional starting blank into the three-dimensional support frame. The material may be superelastic, such as NITINOL, and the method may include bending the 2-D blank into the 3-D form and shape setting it. A merely elastic material such as ELGILOY may be used and plastically deformed in stages, possibly accompanied by annealing, to obtain the 3-D shape. Alternatively, a tubular blank could be formed to define a non-tubular shape, typically conical. A method for calculating the precise 2-D blank shape is also disclosed. A mandrel assembly includes a mandrel and ring elements for pressing the blank against the external surface of the mandrel prior to shape setting.

A patterned transparent conductor including a conductive layer coated on a substrate is described. More specifically, the transparent conductor can be patterned by screen-printing an acidic etchant formulation on the conductive layer. A screen-printable etchant formulation is also disclosed.

A touch panel is made by forming a routing and pad pattern group on a substrate to include first and second routing lines, first pad electrodes connected to the first routing line, and second pad electrodes connected to the second routing line, by using a first mask; forming a sensor electrode pattern group on the substrate having the routing and pad pattern group formed thereon to include first sensor electrodes formed in a first direction, second sensor electrodes formed in a second direction, and connection portions that each connects adjacent first sensor electrodes, by using a second mask; forming a first insulating layer to include contact holes to expose portions of the second sensor electrodes, respectively, by using a third mask; and forming bridges that each connects adjacent second sensor electrodes through the contact holes and a second insulating layer on the bridges, by using a fourth mask.

Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.

Improved stretchable printed circuit boards, and fabrication methods thereof, are described. The improved stretchable printed circuit boards include a serpentine conductive trace enclosed by stretchable dielectric material. The stretchable dielectric material has a serpentine shape itself, realized by crenulated edges. The crenulated edges reduce torsional strain on the conductive trace and are formed, for example, by cutting away sections of the stretchable dielectric material proximate segments of the serpentine conductive trace where the serpentine conductive trace changes direction.

A flexible circuit electrode array with more than one layer of metal traces comprising: a polymer base layer; more than one layer of metal traces, separated by polymer layers, deposited on said polymer base layer, including electrodes suitable to stimulate neural tissue; and a polymer top layer deposited on said polymer base layer and said metal traces. Polymer materials are useful as electrode array bodies for neural stimulation. They are particularly useful for retinal stimulation to create artificial vision, cochlear stimulation to create artificial hearing, or cortical stimulation many purposes. The pressure applied against the retina, or other neural tissue, by an electrode array is critical. Too little pressure causes increased electrical resistance, along with electric field dispersion. Too much pressure may block blood flow.

Articles containing fine-grained and/or amorphous metallic coatings/layers on at least part of their exposed surfaces are imprinted with surface structures to raise the contact angle for water in the imprinted areas at room temperature by equal to or greater than 10°, when compared to the flat and smooth metallic material surface of the same composition.

In an electrochemical reactor used for electrochemical treatment of a substrate, for example, for electroplating or electropolishing the substrate, one or more of the surface area of a field-shaping shield, the shield's distance between the anode and cathode, and the shield's angular orientation is varied during electrochemical treatment to screen the applied field and to compensate for potential drop along the radius of a wafer. The shield establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film of conductive metal on the wafer.

A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line and a pillar, a connection joint that electrically connects the routing line and the pad, and an encapsulant. The routing line extends laterally from the pillar towards the chip, the pillar includes tapered sidewalls, and the chip and the pillar are embedded in the encapsulant and extend vertically beyond the routing line in the same direction.

A producing method of a suspension board with circuit that can permit a terminal portion to be formed by electrolysis plating without exposing a conductor layer to outside and also can reduce the number of processes, and the suspension board with circuit produced by the same producing method. After an insulating base layer 3 is formed on a suspension board 2 in a specific pattern in which a second opening 12 is formed, a thin metal film 13 is formed on an entire surface of the insulating base layer 3 and on a surface of the suspension board 2 including the second opening 12 exposed from the insulating base layer 3.Then, a conductor layer 4 is formed in the form of a wired circuit pattern on the thin metal film 13. Thereafter, the insulating cover layer 10 is formed in such a manner that a pad opening 11 is formed in the insulating cover layer 10 and then a pad portion 16 is formed in the pad opening 11 using the suspension board 2 as a lead portion of the electrolysis plating. Thereafter, a first opening 25 larger than the second opening 12 is formed in the suspension board 2 at a portion thereof corresponding to the second opening 12.

In a method of manufacturing an electronic component built-in substrate of the present invention, a mounted body including a first insulating layer, a stopper metal layer formed under the first insulating layer of a portion corresponding to a component mounting region and a second insulating layer formed on a lower surface of the first insulating layer and covering the stopper metal layer is prepared, and a concave portion is obtained by penetration-processing a portion of the first insulating layer, which corresponds to the component mounting region to form an opening portion, while using the stopper metal layer as a stopper. Also, the stopper metal layer in the concave portion is removed, then an electronic component is mounted on the concave portion, and then a third insulating layer is formed on the electronic component.

According to embodiments of the present invention, a method for manufacturing a pattern of conductive elements on a substrate is provided. The method includes coating an aluminum foil laminated onto the substrate with an electrically conductive material, applying an etch-resist material on selective areas pre-designed to carry the conductive objects, chemically etching to remove the aluminum and the electrically conductive material from areas not covered by the etch-resist material that are complementary to the selective areas and removing the etch-resist material.

The object is to provide a printed wiring board high in reliability of an interlayer connection even when a conductor bump is miniaturized and a manufacturing method of such printed wiring board. On a conductor plate 1, approximately conical conductor bumps 1a, 1a, . . . are formed, the conductor bumps 1a, 1a, . . . being caused to penetrate through a prepreg 5 to project tip ends of the conductor bumps 1a, 1a, . . . from an opposite side of the prepreg 5. The tip ends of the conductor bumps 1a, 1a, . . . and interconnection patterns 7a and 7b on surfaces of core material 17A, before bonding, are exposed to plasma to activate. The activated tip ends of the conductor bump 1a, 1a, . . . and interconnection patterns 7a and 7b on the surface of the core material are stacked to bond both.

The present invention deposits a conductive material from an electrolyte solution to a predetermined area of a wafer. The steps that are used when making this application include applying the conductive material to the predetermined area of the wafer using an electrolyte solution disposed on a surface of the wafer, when the wafer is disposed between a cathode and an anode, and preventing accumulation of the conductive material to areas other than the predetermine area by mechanically polishing the other areas while the conductive material is being applied.

Polishing compositions and methods for removing conductive materials from a substrate surface are provided. In one aspect, a method is provided for processing a substrate to remove conductive material disposed over narrow feature definitions formed in a substrate at a higher removal rate than conductive material disposed over wide feature definitions formed in a substrate by an electrochemical mechanical polishing technique, and then polishing the substrate by at least a chemical mechanical polishing technique.

The invention discloses a microneedle array chip comprising metal microneedles and a substrate, wherein the microneedle consists of a needle head with a tip at its top, a needle bar and a needle seat, and is fixed onto the substrate via the needle seat; and the needle bar of the metal microneedle, having a cylindrical or conical shape, is inclined toward the substrate at a preset angle, and the needle head has a conical shape, or the upper surface of the tip is an oval plane or oval ring plane parallel to the substrate or inclined toward it at a preset acute angle. The metal microneedles in the microneedle array chip of the invention have firm structures to avoid fracture, and have sharp tips to facilitate puncturing. The maximal puncturing depth of the microneedles is easy to adjust and control. The microneedles in the array have good uniformity, and are safe and reliable to use. The hollow microneedles, like conventional syringe needles, have lateral openings, and thus can effectively avoid the blockage of the infusion poles by skin, thereby facilitating rapid diffusion and absorption of drugs, and resulting in significant therapeutic effects.

A self-assembled nanometer conductive bump and a method for fabricating the bump. In the method, a multiplicity of carbon nanotubes that are coated at two ends with chemically functional groups is first provided. A substrate that is equipped with at least one bond pad on a surface is then positioned juxtaposed to the carbon nanotubes for forming a bond between the carbon nanotubes and the metal pads facilitated by a chemical affinity existed between the functional groups and the metal pad.

A method of fabricating a component is provided. The method includes depositing a fugitive coating on a surface of a substrate, where the substrate has at least one hollow interior space. The method further includes machining the substrate through the fugitive coating to form one or more grooves in the surface of the substrate. Each of the one or more grooves has a base and extends at least partially along the surface of the substrate. The method further includes forming one or more access holes through the base of a respective one of the one or more grooves to connect the respective groove in fluid communication with the respective hollow interior space. The method further includes filling the one or more grooves with a filler, removing the fugitive coating, disposing a coating over at least a portion of the surface of the substrate, and removing the filler from the one or more grooves, such that the one or more grooves and the coating together define a number of channels for cooling the component.

The present invention is directed to systems, devices and methods for identifying biopolymers, such as strands of DNA, as they pass through a constriction such as a carbon nanotube nanopore. More particularly, the invention is directed to such systems, devices and methods in which a newly translocated portion of the biopolymer forms a temporary electrical circuit between the nanotube nanopore and a second electrode, which may also be a nanotube. Further, the invention is directed to such systems, devices and methods in which the constriction is provided with a functionalized unit which, together with a newly translocated portion of the biopolymer, forms a temporary electrical circuit that can be used to characterize that portion of the biopolymer.

Various embodiments of a planarization device and methods of using the same are provided. In one aspect, a device for planarizing a surface of a semiconductor workpiece is provided that includes a table for holding a quantity of an electrically conducting solution thereon. A member is included for holding the semiconductor workpiece such that the surface is in contact with the solution and operates as a working electrode. The member has a first conductor for establishing electrical connection with the semiconductor workpiece. A counter electrode is provided for making electrical connection with the solution and a reference electrode is provided for making electrical connection with the solution with a known electrode potential. A power source is operable to control the electric potential between the working electrode and the counter electrode. Slurry consumption may be dramatically reduced and static etch rate due to aborts may be virtually eliminated.

A circuit substrate manufacturing method of the present invention includes the steps of preparing a substrate on which a metallic foil made of a first metal (copper) is formed in a releasable state, forming a build-up wiring including a metal layer made of a second metal (solder) on the metallic foil, obtaining a circuit member having a structure that the build-up wiring is formed on the metallic foil by releasing the metallic foil from the substrate, and exposing the metal layer by removing selectively the metallic foil of the circuit member with respect to the metal layer.

A new method of creating thin free-standing pin hole-free hydrogen-selective palladium-bearing membranes that comprises thinning cold-rolled membranes by chemical etching or electrochemically electrolyzing of at least one membrane surface, and novel membranes produced thereby and including membranes with selected portions only thereof so thinned.

A producing method of a flexible wired circuit board that can prevent the formation of a gap between an elongate substrate and a stiffener sheet bonded thereto to prevent contamination of the flexible wired circuit board obtained. In the process subsequent to the process of forming a conductive pattern 3 on a surface of the elongate substrate 1 by the semi-additive process using electrolysis plating and then annealing the elongate substrate 1 with the conductive pattern 3 in its wound up state, a stiffener sheet 9 having a width narrower than the elongate substrate 1 is bonded to the back side of the elongate substrate 1. Thereafter, an oxidized film formed on a surface of the conductive pattern 3 is removed and then a solder resist 11 is formed thereon. This prevents the strip of the stiffener sheet 9 from the elongate substrate 1 and in turn prevents etching solution or developing solution from entraining in a gap therebetween.

A method is provided for forming a conductive interconnect, the method comprising forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first conductive structure in the first opening. The method also comprises forming a second dielectric layer above the first dielectric layer and above the first conductive structure, forming a second opening in the second dielectric layer above at least a portion of the first conductive structure, the second opening having a side surface and a bottom surface, and forming at least one barrier metal layer in the second opening on the side surface and on the bottom surface. In addition, the method comprises removing a portion of the at least one barrier metal layer from the bottom surface, and forming a second conductive structure in the second opening, the second conductive structure contacting the at least the portion of the first conductive structure. The method further comprises forming the conductive interconnect by annealing the second conductive structure and the first conductive structure.