4results about How to "Uniform current" patented technology

A flexible circuit board includes a substrate, a plurality of circuit patterns disposed on the substrate, and a protective layer disposed on the circuit patterns, wherein each of the plurality of circuit patterns has a thickness greater than 8 µm and less than or equal to 25 µm, and wherein a thickness deviation between the plurality of circuit patterns is 0.5 µm to 3 µm. When the flexible circuit board is connected with a display panel, the display panel can have high performance and high current can flow through the display panel. The circuit pattern having the features according to the present invention is prevented from being damaged by high current.

This application relates to semiconductor technology and discloses a power semiconductor module and its driving circuit and electronic device. The power semiconductor module includes at least two groups of power semiconductor devices, a substrate, and multiple control signal pins. Each power semiconductor device group includes two power semiconductor devices forming a bridge arm structure, with each group connected in parallel. Each power semiconductor device is mounted on the substrate. The control terminal of each power semiconductor device is connected to a corresponding control signal pin. By using parallel power semiconductor device groups for current shunting, the system's power capacity and heat dissipation efficiency are greatly improved. Furthermore, connecting the control terminals of each power semiconductor device to separate control signal pins allows for individual control of each device, ensuring current balance among the parallel power semiconductor device groups and significantly improving the module's reliability.

The application discloses a power module terminal and a power module, and belongs to the field of power electronic power modules. The power module terminal comprises a main body part and a leading-out part extending outwards from the main body part. Two current introduction holes are arranged on the main body part, and a current leading-out hole is arranged on the leading-out part. A groove is arranged between the current leading-out hole and the outer edge of the main body part. The power module comprises a substrate, an upper bridge power chip set and a lower bridge power chip set arranged on the substrate, a positive copper layer and a negative copper layer, and further comprises a positive terminal and a negative terminal. The positive terminal and the negative terminal are the power module terminal described above, and are electrically connected to the positive copper layer and the negative copper layer through two current introduction holes respectively. The application solves the problems of large deformation in the welding process and large residual stress of the welding points after welding of the large-area terminal.

The application provides a chip ESD repair method, system and storage medium based on via optimization, locates a failure point based on a chip ESD test result, determines corresponding ESD protection devices and discharge paths, screens via defects in combination with a layout design file to mark defect points, formulates a via optimization strategy for each discharge path according to the defect points, performs via supplement and through operation according to the optimization strategy, performs symmetry checking on each discharge branch of the ESD protection devices and adjusts a via layout, and outputs a repaired layout after performing design rule checking and electrical rule checking on the optimized layout. The application realizes impedance reduction of the discharge path through via supplement and through operation, realizes current balance of each branch through symmetry checking, and does not need to change the original circuit architecture, and gives consideration to ESD protection performance improvement and high-speed signal integrity maintenance.