40results about How to "Low switching voltage" patented technology

The invention discloses a grid-connected photovoltaic inverter and relates to equipment which employs irreversible DC power input conversion as AC power output for a semiconductor device with a control electrode and is used for being used together with a power supply system of a power supply. The equipment consists of a photovoltaic array module, four identical switching tubes, two identical diodes, four identical capacitors, an inductor and a power grid; and the topology ensures not to generate DC component or common mode current for the power grid. Meanwhile, the inverter has low output current ripple and higher efficiency, and overcomes the defects that the conventional full-bridge inverters and other types of transformerless photovoltaic inverters generate DC component in the power grid and generate common mode current or/and higher current ripple. Compared with a half-bridge inverter, the grid-connected photovoltaic inverter reduces the differential mode voltage and current ripple by half.

The object of providing a non-volatile semiconductor memory that stands out by good scalability and a high retention time as well as ensures low switching voltages at low switching times and achieves a great number of switching cycles at good temperature stability is solved by the present invention with a semiconductor memory whose memory cells comprise at least one silicon matrix material layer with open or disturbed nanocrystalline or amorphous network structures and structural voids which has a resistively switching property between two stable states, utilizing the ion drift in the silicon matrix material layer. The memory concept suggested in the present invention thus offers an alternative to the flash and DRAM memory concepts since it is not based on the storing of charges, but on the difference of the electric resistance between two stable states that are caused by the mobility of ions in the amorphous silicon matrix material with an externally applied electric field.

A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

A magnetic resonance antenna has longitudinal antenna rods in a birdcage structure, and antenna ferrules connecting the longitudinal antenna rods at their ends in terms of radio-frequency. The magnetic resonance antenna has a number of radio-frequency switching elements that interrupt, in terms of radio-frequency, at least one part of the longitudinal antenna rod to detune the eigen-resonance frequency of the antenna with respect to an operating magnetic resonance frequency. For this purpose, the magnetic resonance antenna is provided with two switching lines, directed to the radio-frequency switching elements from outside of the birdcage structure, the switching lines having a ring line connected thereto running annularly on or in the birdcage structure and transverse to the longitudinal antenna rods.

Integrated optical intensity or phase modulators capable of very low modulation voltage, broad modulation bandwidth, low optical power loss for device insertion, and very small device size are of interest. Such modulators can be of electro-optic or electro-absorption type made of an appropriate electro-optic or electro-absorption material in particular or referred to as an active material in general. An efficient optical waveguide structure for achieving high overlapping between the optical beam mode and the active electro-active region leads to reduced modulation voltage. In an embodiment, ultra-low modulation voltage, high-frequency response, and very compact device size are enabled by a semiconductor modulator device structure, together with an active semiconductor material that is an electro-optic or electro-absorption material, that are appropriately doped with carriers to substantially lower the modulator voltage and still maintain the high frequency response. In another embodiment, an efficient optical coupling structure further enables low optical loss. Various embodiments combined enable the modulator to reach lower voltage, higher frequency, low optical loss, and more compact size than previously possible in the prior arts.

The present invention relates to a display comprising at least one substrate, at least one electrically conductive layer and at least one electronically modulated imaging layer, wherein the electronically modulated imaging layer comprises a self-assembled, close-packed, ordered monolayer of domains of electrically modulated material in a random coil fixed polymer matrix and filler.

Abstract of Disclosure A P_STSCR structure includes a P-type substrate, an N-well in the P-type substrate, a first N+ diffusion region located in the P-type substrate connected to the cathode, a second P+ diffusion region located in the N-well connected to the anode, and a third P+ diffusion region as a trigger node located in the P-type substrate and between the first N+ diffusion region and the second P+ diffusion region. A lateral SCR device including the second P+ diffusion region, the N-well, the P-type substrate and the first N+ diffusion region is thereby formed. When a current flows from the trigger node into the P-type substrate, the lateral SCR device is triggered on into its latch state to discharge ESD current. Since the present invention utilizes a substrate-triggered current Itrig flowing into or flowing out from the P-type substrate or the N-well through the inserted trigger node, a much lower switching voltage in the SCR device is obtained.With such a lower switching voltage in the SCR device, the total layout area of the ESD protection circuit can be reduced, and the turn-on speed of SCR device is further improved to quickly discharge ESD current.ESD current flowing through surface channels, and heat dissipation issues, are avoided, while presenting no increase to the overall complexity and difficulty of CMOS IC manufacturing.

There are provided an organic bistable element, which is simple in structure, can eliminate the need to increase production process steps, and has a low switching voltage, a memory device using the same, and a method for driving the organic bistable element and the memory device. The organic bistable element has a laminate structure comprising an organic thin film interposed between a first electrode and a second electrode. The organic thin film comprises an organic compound represented by formula (I):

The invention discloses a high-efficiency inverter topology which inverts direct current into alternating current in a lower cost and high efficiency manner, simultaneously does not cause a common mode interference problem, and can be conveniently applied to inverter systems without isolation transformers. The principle of the topology is that high-frequency chopping switches are respectively arranged on a positive end and a negative end of a direct current input side and switched on/off simultaneously, and the duty ratios of the switches are regulated so as to vary the amplitudes of the output voltage; flat wave inductors are respectively connected at the rear stages of the switches, and a subsequent flow circuit is arranged at one sides, which are connected with the chopping switches, of the two flat wave inductors, so that the subsequent current of the flat wave inductors are ensured when the chopping switches are switched off; H inverting bridges are arranged at the rear stages of the inductors and invert at the output frequency which is required by an inverter, and accordingly, inverting is realized. By utilizing the topology, the switching voltages of switching tubes are reduced, and accordingly, the switching loss of a system is decreased; and moreover, the topology does not cause the common mode interference problem and can be used for the inverter systems without the isolation transformers.

A synchronous follow current inverter topology without common-mode interference realizes the high-efficiency inversion of electric energy from direct current to alternating current with lower cost, and meanwhile, the topology is free of the problem of common-mode interference, and the synchronous follow current inverter topology can be conveniently applicable to an inversion system without isolation transformers. The topology adopts the following principle: high-frequency chopping switches are arranged at the positive end and the negative end of the direct current input side and are switched on and off simultaneously, and the duty cycle of switching of the high-frequency chopping switches is modulated to realize the amplitude change of the output voltage; the rear stage of each high-frequency chopping switch is connected with a flat wave inductor, one side of each flat wave inductor is connected with the chopping switch and is also provided with a follow current circuit with a follow current switch, and the follow current of each flat wave inductor is ensured when the chopping switch is switched off; the rear stage of each inductor is provided with an H reversing bridge, and the H reversing bridges carry out reversing according to the frequency of the expected output of an inverter, so that the inversion is realized. With the topology, the switching voltage of a switching tube is reduced, the switching loss of the system is reduced, meanwhile, the topology is free of the problem of common-mode interference, and is applicable to an inversion system without transformers.

Programming a resistive memory structure at a temperature well above the operating temperature can create a defect distribution with higher stability, leading to a potential improvement of the retention time. The programming temperature can be up to 100 C above the operating temperature. The memory chip can include embedded heaters in the chip package, allowing for heating the memory cells before the programming operations.

The invention discloses a multielement metal oxide thin film based resistive random access memory and a preparation method therefor, and belongs to the technical field of a memory. A bottom electrode layer, a resistive random layer and a top electrode layer are arranged on a substrate in sequence; the bottom electrode material is 2at% Al doped ZnO; the resistive random layer is CuGaZnO; and the top electrode material is Cu. The preparation method comprises the following steps of adopting a radio frequency magnetron sputtering method to prepare the bottom electrode on the substrate; placing a metal mask on the bottom electrode layer; then preparing the CuGaZnO thin film on the metal mask to form the resistive random layer; and finally adopting a vacuum coating technology to prepare the Cu top electrode on the CuGaZnO thin film so as to form the bottom electrode-resistive random layer-top electrode structure. The resistive random access memory has the characteristics of high switch ratio, relatively low switching voltage, stable retention, and anti-fatigue; the problem of high cost of the material of the resistive random layer in the preparation process is effectively solved; and the preparation process is high in portability, and the implementation of a full-transparent device can be facilitated.

A two-wire switching device includes a primary switching unit; a rectifying unit; a first power supply unit for generating a DC power while a power is stopped being supplied from the AC power supply to the load; a second power supply unit for generating a DC power while the power is supplied from the AC power supply to the load; a stabilizing unit; a control unit for starting an operation of the second power supply unit when an electric power is supplied from the AC power supply to the load; a secondary switching unit for short-circuiting the output terminals of the rectifying unit while the second power unit is operated; and at least one auxiliary switching unit. The auxiliary switching unit is on during a time interval from output terminals of the rectifying unit being short-circuited to the primary switching unit being turned on.

The invention provides soluble isomerized anthracene-containing polyimide with an information storage function, and belongs to the field of organic information storage materials. Isomerized anthracene-containing diamine with the electron supply property is firstly synthesized, and then isomerized anthracene-containing diamine and dicarboxylic anhydride with the electron acceptor property are subjected to polycondensation to prepare isomerized anthracene-containing polyimide with the excellent information storage function, wherein the structure of isomerized anthracene-containing polyimide is shown as a formula (I) (please see the formula in the description). Isomerized polyimide has the advantages of being low in switching voltage, high in response speed and stable in storage property, and the information storage behavior of the material can be regulated and controlled by changing the site where an anthracene group is connected into a polyimide main chain; in addition, polyimide has the good solubility in a polar solvent to be beneficial for material processing and preparing of an information storage device. Meanwhile, a preparation technology of polyimide is simple, high in efficiency and beneficial for batch preparation and has the very high practical value and the wide application prospect.

An apparatus that includes first and second parallel converter branches, each parallel converter branch including an input node, N output nodes, a plurality of switches, a converter output node, and control logic. The control logic generates a first set of switch signals to control the switches of the first parallel converter branch and a second set of switch signals to control the second parallelconverter branch, the first set switch signals and the second set of switch signals having respective duty cycles to cause each of the first and second parallel converter branches to output the DC output voltage on each of the N output nodes.