881 results about "Current sample" patented technology

A method for compressing data in an implantable device is provided. A current data sample is received. A difference value is determined between the current data sample and a previous data sample. The current data sample is compressed to at least one output symbol based on the difference value between the current sample and the previous data sample. Systems and programs of using the method are also provided.

A power control system includes a transformer and a controller regulates a current on a secondary-side of the transformer based on a primary-side signal value. In at least one embodiment, the secondary-side current is a current out of a filter coupled to a rectifier and the secondary-side of the transformer and into a load. In at least one embodiment, the primary-side signal value is a sample of a current in the primary-side windings of the transformer. In at least one embodiment, the primary-side signal value represents a sample value of a primary-side transformer current. Proper timing of sampling the primary-side signal value substantially eliminates contributions of a transformer magnetizing current from the primary-side transformer current sample. Sampling the primary-side signal value when contributions of the transformer magnetizing current are substantially eliminated allows at least an average of the secondary-side current to be determined from the primary-side signal value.

When finding a current on an AC side of an inverter by observing that on a DC side, a current that is not affected by pulsating components contained in the AC current must be detected. Timing of change of a gate signal for driving a switch element of a phase having an intermediate magnitude among three-phase voltage command signals to ON/OFF is used as a reference time point for DC bus current detection. DC bus currents sampled T1 before and T2 after the reference time point are designated as IDC1 and IDC2, respectively. A detected current value of a maximum voltage phase is computed by using IDC2 and IDC1 respectively in an increase period and a decrease period of a carrier signal alternately. A detected current value of a minimum voltage phase is computed by using IDC1 and IDC2 respectively in an increase period and a decrease period alternately.

Disclosed is an apparatus and method for modeling and estimating the characteristics of a power amplifier with memory. A predistortion module generates a predistorted signal in response to coefficients of a complex polynomial representative of the amplifier and to an input signal. A power amplifier receives time-spaced samples of the predistorted signal and generates an output signal. A polynomial module updates the coefficients of the complex polynomial in response to a current sample of the output signal and to the time-spaced samples of the predistorted signal. In particular, the complex polynomial is implemented with both even and odd terms.

A controller for determining the duty-ratio for a pulse width modulator of a converter includes an inner current loop, an outer voltage loop and a multiplier with an input voltage feed forward to connect both loops. A prediction unit determines a correction signal i_cor that is added to the reference current i_ref by means of an adder and it further determines a sample correction signal to correct the current samples in the current loop. This error-controlled duty-ratio prediction with sample correction results in an improved total harmonic distortion as well as in an improved power factor of the converter.

A digital current-mode controller for a DC-DC converter is disclosed. The controller comprises a digital current reference; and a current loop compensator adapted to receive a digital current error signal derived from a digital current sample sensed from the DC-DC converter and the digital current reference and to generate a duty-cycle command, wherein the current loop compensator comprises a low-pass filter that is used in generating the duty-cycle command. A DC-DC regulator comprising a digital current-mode controller and a method of controlling a DC-DC converter are also disclosed.

The invention relates to a digital control device and method for an LLC (logical link control) synchronously-rectified resonant converter. The device comprises a digital signal processor, a primary high-frequency driving circuit, a current sampling detection circuit, a voltage sampling detection circuit and a secondary high-frequency driving circuit, wherein the digital signal processor judges an operation area of a circuit according to an output voltage fed back by the voltage sampling detection circuit, after the circuit performs three-pole two-zero compensation, the values of an on-chip period register are respectively changed so as to generate high-frequency driving signals which are then output to the primary and secondary high-frequency driving circuits by the digital signal processor; the current sampling detection circuit detects a secondary output current which is then output to the digital signal processor, then the digital signal processor judges whether an overloading or overcurrent phenomenon (generated in the process of area switching) occurs according to the size of the current so as to cut off the primary and secondary high-frequency driving circuits in time. In the invention, the LLC resonant converter is subjected to the following digital control by a digital signal processing chip-peripheral timer combined circuit: the advanced conduction of secondary synchronous rectifying tubes is realized by the design of software/hardware auxiliary circuits, and the control on secondary driving signals is performed by adding a 555 timer, so the application of a timer in a DSP (digital signal processing) chip is reduced, thereby effectively solving the problem of conduction loss of synchronous rectifying tubes introduced in the process of underloading in the traditional control strategy; and the application of a PWM (pulse-width modulation) port of the digital signal processing chip is reduced, thereby improving the reliability of the whole device.

A technique for reconstructing phase currents based on measurements of a DC bus current. Non-observable regions of DC bus current samples to reconstruct phase currents are reduced in size by using two phase space vector modulation. The non-observable regions can be further reduced by omitting deadtime insertions for switch actuations when output current is higher than a given threshold. Voltage command vectors in non-observable areas can be constructed by two time averaged vectors one of which is constructed to obtain an observable DC bus current reflecting motor phase current. The additive vectors have the same combined time average value as that of the voltage command vector in order to preserve volt-seconds. Current samples may also be averaged to provide a more accurate reconstruction of phase current. Current samples are time delayed to avoid transients for more accurate readings. When three phase PWM inverter modulation results in inability to determine the motor phase current from the DC bus measurement, the technique includes dynamically switching to two phase PWM modulation to reduce the time interval when the motor phase current is not determinable through the DC bus current measurement.

An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) fetch a plurality of reference samples from a memory to a plurality of slots in a buffer and (ii) motion estimate a plurality of current sample units of a current picture to generate a plurality of motion vectors. The motion vectors may be stored in a plurality of lines of a table. Each line generally identifies a corresponding slot in the buffer. Duplicates among the lines may be consolidated. The second circuit may be configured to evaluate the reference samples in the buffer based on the motion vectors to select a prediction sample unit.

The invention discloses a fault diagnosis method during the industrial process. The method comprises the steps of collecting historical normal data during the industrial process; calculating a detection statistics based on the historical normal data during the industrial process; collecting the to-be-detected data of the industrial process; on the condition that the industrial process is detected to be out of order, extracting a statistic feature based on the relative refactoring contribution method; according to the statistic feature, calculating a conditional probability density function in the fault mode and a conditional probability density function in the normal mode; according to the prior probability and the conditional probability density function, calculating a posterior probability; conducting the fault variable recognition on a current time sample based on the minimum risk Bayesian decision theory; according to a diagnosis result, updating the prior probability for the next time sample and conducting the fault diagnosis and recognition again for the next round. According to the technical scheme of the invention, the major failure variable, the secondary process variable and the normal variable of the current sample are distinguished. Meanwhile, the diagnosis result of the process variable of the previous time sample is applied to the diagnosis of the current sample. Therefore, the pollution effect during the fault diagnosis of the industrial process is eliminated.

A system and method for fusing the outputs from multiple LiDAR sensors on a vehicle. The method includes providing object files for objects detected by the sensors at a previous sample time, where the object files identify the position, orientation and velocity of the detected objects. The method also includes receiving a plurality of scan returns from objects detected in the field-of-view of the sensors at a current sample time and constructing a point cloud from the scan returns. The method then segments the scan points in the point cloud into predicted clusters, where each cluster initially identifies an object detected by the sensors. The method matches the predicted clusters with predicted object models generated from objects being tracked during the previous sample time. The method creates new object models, deletes dying object models and updates the object files based on the object models for the current sample time.

The invention discloses a method and a device for intra-frame prediction and an intra-frame prediction-based encoding/decoding method and an intra-frame prediction-based encoding/decoding system. The prediction method comprises the following steps of: determining adjacent blocks of M*N blocks to be predicted, and selecting corresponding Ki reference sample points from the adjacent blocks according to the length Ki (i is equal to 0, 1, 2,...,(M*N-1)) of a filter at each position i in the blocks to be predicted to form a sample point set for the intra-frame prediction, wherein ki is equal to 0, 1, 2,..., Ki-1, Ki is a natural number and is more than 1, and M and N are natural numbers; selecting a prediction direction m, and determining the prediction weighting coefficient Wi (m, k) of each sample point Ci to be predicted in the blocks to be predicted respectively, wherein i is equal to 0, 1, 2,...,(M*N-1); and calculating prediction values of current sample points to be encoded according to the prediction weighting coefficients Wi (m, k) and the sample point set for the intra-frame prediction. The prediction method improves the prediction precision of an intra-frame prediction mode, so that the integral encoding performance is improved.

The invention provides a support vector machine based fault electric arc detection method, relating to the technical field of electric arc protection and solving the technical problem of improving fault electric arc identifying and judging accuracy. The method provided by the invention comprises the following concrete steps of: 1) acquiring current samples of circuits to be detected under different loads and working conditions; 2) normalizing the waveform of each current sample; 3) obtaining a test sample combination according to the normalized current samples; 4) dividing the test sample combination into a train set and a verification set; 5) calculating a kernel function parameter and a punishment parameter which have the highest prediction accuracy rate; 6) predicting each sample in the verification set; 7) training by utilizing different sample sets to obtain a weight matrix; 8) verifying the samples in the verification set by utilizing the weight matrix, and creating a detection model according to the verification result; and 9) identifying and judging the fault electric arc by utilizing the detection model. By applying the method provided by the invention, false operation of fault electric arc detection equipment under the action of an interference load can be effectively avoided.

A current output device of a data driving apparatus sequentially applying data signals to data lines. The data signals correspond to analog converted output currents and the current output device includes a switch controlling supply of the analog output currents according to a first control signal, a master current sample/hold circuit sampling or holding the analog output currents according to a second control signal, a slave current sample/hold circuit holding or sampling the analog output currents according to a third control signal, and a multiplexer selecting an output current held in the master current sample/hold circuit or the slave current sample/hold circuit according to the fourth control signal and applying the selected output current to a corresponding data line.

An image decoding method, which is performed by a decoding device according to the present invention, comprises the steps of: acquiring the information on an intra-prediction mode of a current block from a received bit stream; deriving neighboring reference samples of the current block; deriving a first prediction value for a current sample of the current block on the basis of the intra-prediction mode and the neighboring reference samples; deriving a second prediction value for the current sample on the basis of adjacent samples of the current sample; and deriving a prediction value for the current sample on the basis of the first prediction value and the second prediction value. According to the present invention, the intra-prediction value can be derived on the basis of the adjacent samples of the current sample within the present block, and the intra-prediction accuracy can be improved therethrough.

A digital phase lock loop (PLL) for maintaining synchronization with the phase of a received data signal including a preamble and an information-containing data frame, by incrementing a state machine through an internal cyclic count, each cycle thereof including a center count tending to coincide with center regions of the successive pulses and an edge count tending to coincide with edges of the successive pulses. The PLL selects a current sample of the signal whenever the internal count reaches the predetermined center count value. The state machine internal count is updated in accordance with a cumulative phase error obtained by summing the phase errors detected over successive edges between each edge and the corresponding center count. The interval over which the cumulative phase error is computed depends upon the number of received edges during the preamble and depends upon elapsed time during the data frame.

The invention discloses an overcurrent protection circuit for a low dropout linear voltage regulator. The overcurrent protection circuit for the low dropout linear voltage regulator comprises a current sampling circuit, a current comparison circuit and an upward pull circuit, wherein the current sampling circuit samples gate-drain voltage of a power tube of the low dropout linear voltage regulator, and outputs a sampling current to the current comparison circuit, the current comparison circuit mirrors the sampling current through a current mirror, and then compares the sampling current with a current of a current source, and after output current value of the low dropout linear voltage regulator exceeds current protection threshold value, control voltage output by the current comparison circuit powers on the upward pull circuit, and the upward pull circuit pulls up gate end voltage of the power tube of the low dropout linear voltage regulator, and thereby limits increasing of the output current, and plays a part in overcurrent protection. The overcurrent protection circuit for the low dropout linear voltage regulator can effectively restrain channel length modulation effects of a current sampling tube in the current sampling circuit, decreases occurrence rate of the problem that deviation between value of the current sampled by the current sampling circuit and ideal value is overlarge, improves current sampling accuracy of the overcurrent protection circuit, and obtains accurate starting threshold value of the overcurrent protection circuit.

The invention discloses a control circuit for a direct current converter, comprising a current sampling module for providing a current sample signal based on an inductive current of the direct current converter; a slope compensation module for providing the slope compensation signal based on a clock signal and a control signal; a peak detector for detecting the amplitude value of the slope compensation signal and providing the peak detection signal; an error amplifier for providing the error amplifying signal based on a feedback signal and a reference signal; a clipper for clipping the error amplification signal based on the peak detection signal and the inductive current setting peak value; a compared logic module for providing the control signal to control the output level of the directcurrent converter based on the clock signal, the error amplifying signal, the slope compensation signal and the current sampling signal. The invention also comprises a method corresponding with the circuit. The real induction current peak value is adjusted to the required induction current peak value by adjusting the inductive current based on the inductive current limit signal RAMP and the clipping signal VCLAMP, therefore the output current of the direct current converter is limited.