77 results about "Channel length modulation" patented technology

Subpixels on an electroluminescent (EL) display panel, such as an organic light-emitting diode (OLED) panel, are compensated for initial nonuniformity (“mura”) and for aging effects such as threshold voltage V_th shift, EL voltage V_oled shift, and OLED efficiency loss. The drive current of each subpixel is measured at one or more measurement reference gate voltages to form status signals representing the characteristics of the drive transistor and EL emitter of those subpixels. Current measurements are taken in the linear region of drive transistor operation to improve signal-to-noise ratio in systems such as modern LTPS PMOS OLED displays, which have relatively small V_oled shift over their lifetimes and thus relatively small current change due to channel-length modulation. Various sources of noise are also suppressed to further increase signal-to-noise ratio.

The invention discloses an overcurrent protection circuit for a low dropout linear voltage regulator. The overcurrent protection circuit for the low dropout linear voltage regulator comprises a current sampling circuit, a current comparison circuit and an upward pull circuit, wherein the current sampling circuit samples gate-drain voltage of a power tube of the low dropout linear voltage regulator, and outputs a sampling current to the current comparison circuit, the current comparison circuit mirrors the sampling current through a current mirror, and then compares the sampling current with a current of a current source, and after output current value of the low dropout linear voltage regulator exceeds current protection threshold value, control voltage output by the current comparison circuit powers on the upward pull circuit, and the upward pull circuit pulls up gate end voltage of the power tube of the low dropout linear voltage regulator, and thereby limits increasing of the output current, and plays a part in overcurrent protection. The overcurrent protection circuit for the low dropout linear voltage regulator can effectively restrain channel length modulation effects of a current sampling tube in the current sampling circuit, decreases occurrence rate of the problem that deviation between value of the current sampled by the current sampling circuit and ideal value is overlarge, improves current sampling accuracy of the overcurrent protection circuit, and obtains accurate starting threshold value of the overcurrent protection circuit.

The invention provides a BSIM3 HCI reliability model which is applied to MOSFET electrical simulation. The model provides a method for calculating output characteristics after the degradation of a transistor impacted by HCI effect according to bias voltage exerting time of MOSFET in a bias voltage condition. The method comprises the following steps: Conditions of the transistor impacted by hot carrier degradation effect and the occurred variation on bias voltage exerting time are considered on the basis of standard BSIM3 model, and meanwhile, parameters of seven standard BSIM3 model are redefined as follows: a long channel threshold voltage Vth0 under a condition of zero Vbs, first-order body effect factor of threshold voltage K1, the mobility ratio under zero offset electric field Mu0, mobility ratio decay effector Muc, channel length modulation parameter of silicon charge effect A0, grid-bias voltage modulation parameter of silicon charge effect Ags and silicon bias voltage modulation parameter Keta of silicon charge effect.

In first and second gate electrodes constituting a gate electrode, the gate length of the second gate electrode is set shorter than the gate length of the first gate electrode and short enough to produce the short channel effect. The threshold voltage of a second transistor corresponding to the second gate electrode can thereby be made lower than the threshold voltage of a first transistor corresponding to the first gate electrode. When the same voltage is applied to the first and second gate electrodes, an electric field concentration at the channel edge on the drain side is reduced. This in result reduces the channel length modulation effect.

The invention discloses a sub-threshold reference source compensated by adopting electric resistance temperature, which belongs to a range of power supply temperature compensating circuits. The sub-threshold reference source adopts positive temperature coefficient compensating circuit and temperature compensating reference voltage source technology of electric resistance, and consists of three parts comprising a peak current mirror, a negative temperature coefficient current generating circuit and a reference voltage output circuit. A sub-threshold reference circuit for generating constant reference voltage output by using the positive temperature coefficient of the electric resistance and the negative temperature coefficient of the current on a resistor can overcome the influence that the output voltage brought by channel length modulation effect is changed by the fluctuation of power supply voltage to a certain degree; and the sub-threshold reference source has a simple structure and low power consumption, can be applied to an analog integrated circuit with low-power consumption design, and can be broadly applied to a reference voltage source circuit required by a low-power consumption analog and digital-analog mixed circuit for generating low temperature coefficients.

The invention discloses a band-gap reference source with low offset voltage and a high PSRR (power supply rejection ratio). The band-gap reference source comprises a first P-channel field-effect transistor, a second P-channel field-effect transistor, a third P-channel field-effect transistor, a fourth P-channel field-effect transistor, a first resistor, a second resistor, a third resistor, a first bipolar transistor, a second bipolar transistor and a voltage feedback circuit. According to the band-gap reference source with the low offset voltage and the high PSRR, with the adoption of a double-layer current mirror structure and addition of biasing resistors, influence of channel length modulation effects of current mirrors is reduced, the accuracy of current multiplication coefficients is guaranteed, and maladjustment of output voltage is reduced.

A bandgap reference circuit includes a reference current generator for respectively generating a first reference current on a first current path and a second reference current on a second current path, a current mirror for generating a third reference current on a third current path based on the first and second reference currents, an operation amplifier for rendering the first reference current substantially identical to the second reference current and a feedback circuit for rendering a node voltage on the first current path substantially identical to another node voltage on the third current path, so as to eliminate possible errors caused by a channel length modulation effect in the current mirror.

The invention discloses a method for building an AlGaN/GaN HEMT device direct current model. The method includes the steps of a, measuring parameters of an AlGaN/GaN HEMT device S; b, extracting parasitic antenna parameters of the AlGaN/GaN HEMT device and removing influences of parasitic antenna values; c, extracting values of device transconductance parameters beta, voltage saturation parameters alpha and channel length modulation factors gamma; d, fitting beta, alpha and gamma curves changed along with gate-to-source voltage Vgs and obtaining unified expressions, changed along with Vgs, of the parameters beta, alpha and gamma; e, substituting beta, alpha and gamma expressions into a Curtice model, and obtaining the new direct current model. By means of the method, the method of building a direct current parameter and gate-to-source voltage non-linear relationship is adopted for building the new AlGaN/GaN HEMT device direct current model, the model has the gate-to-source voltage bias correlated characteristics, and the accuracy of the direct current model is improved.

Disclosed is an internal voltage generator capable of outputting a constant voltage regardless of change of a supply voltage. The internal voltage generator includes a current mirror unit, drivers and a voltage divider and prevents a channel length modulation phenomenon by changing the structure of the current mirror unit.

The invention discloses a linear source follower, which belongs to the technical field of voltage followers and is characterized in that: transistors M1 and M3 are arranged in a cascade mode, and the grids of the transistors M1 and M3 are both connected with an input Vinp; transistors M2 and M4 are connected in a cascade mode, and the grids of the transistors M2 and M4 are both connected with aninput Vinn; the transistors M3 and M4 are both low-threshold transistors; and the transistors M1 and M2 are both high-threshold transistors. The sources S of the transistors M1, M2, M3 and M4 are allconnected with a substrate B. The grid of a transistor M5 is connected with a bias voltage Vbias1 and is connected with the input signal Vinn through a capacitor C1, the drain of the transistor M5 isconnected with an output Voutp, and the source of the transistor M5 is grounded through a resistor R1. The grid of a transistor M6 is connected with the bias voltage Vbias1 and is connected with an input signal Vinp through a capacitor C2, the drain of the transistor M6 is connected with an output Voutn, and the source of the transistor M6 is grounded through a resistor R2. In the invention, a channel length modulation effect and a bulk effect are eliminated, the change of a bias current is lowered, and the linear source follower has the advantages of high linearity under a high-speed input signal.

The invention discloses a high-linearity neuromorphic calculation circuit realized by a passive voltage stabilizing circuit. A 1R1T binary storage unit array is connected with an input sequence control switch and a plurality of bit line capacitor voltage isolation transistors, and the input sequence control switch receives input data of a neural network. Each bit line capacitor voltage isolation transistor is connected with a biasing circuit through a respective passive voltage stabilizing circuit, the plurality of bit line capacitor voltage isolation transistors are jointly connected to an analog-to-digital conversion circuit, and a calculation result is output through the analog-to-digital conversion circuit ADC. According to the invention, the influence of the channel length modulation effect caused by the drop of the capacitor voltage in the integration process can be effectively eliminated, so that the integration current is more stable; and meanwhile, the stability of the source voltage of the T0 under different loads can be ensured, and the technical problem that the linearity of the weight value of the circuit is poor due to the fact that the load change is affected is solved.

The invention relates to the technique of electronic circuits and particularly relates to a high-voltage linear voltage regulator. According to the high-voltage linear voltage regulator, a circuit structure to the ground is introduced, and a branch formed by connecting a resistor R4 with a Zener diode D1 in series is connected in parallel with a circuit branch formed by connecting a PMOS (P-channel Metal Oxide Semiconductor) tube MP5 and an NMOS (N-channel Metal Oxide Semiconductor) tube MN10 in series. The breakdown voltage of the Zener diode adopted by the invention is 6V, so that source electrodes of NMOS tubes including MN10 and MN9 namely the point potentials connected with the diode D1 are clamped to high-voltage -6V under the high voltage condition, and the higher voltage effectively protects a grid electrode of a regulating tube. Compared with an existing LDO (Low Dropout Regulator), the grid electrode of the regulating tube is protected and the channel length modulation effect of an MOS (Metal Oxide Semiconductor) in an error amplifier is inhibited under the high voltage condition in the starting process and in the transient response process, so that the use of a high voltage device is reduced, the area of the LDO is reduced, and the performance of the high-voltage LDO is improved. The invention is particularly suitable for the high-voltage linear voltage regulator.

The invention discloses an energy gap reference circuit comprising: a reference current generation circuit generating a first and second reference currents on a first and second current paths; a current mirror generating a third reference current on the third current path based on the first and second reference currents; an operational amplifier to make the first reference current equal to the second reference current; and a feedback circuit to make a mode voltage on the first current path equal to a node voltage on the third current path, to eliminate error caused by probable channel length modulation effect of the current mirror.

A high-voltage high-current control circuit applied to a high-voltage power MOSFET (metal-oxide-semiconductor field effect transistor) circuit comprises a PMOS (P-channel metal oxide semiconductor) tube MP1, a PMOS tube MP2, a PMOS tube MP3, a triode Q1, a triode Q2, an MOSFET tube M1, an MOSFET tube M2, a resistor R1 and a resistor R2, wherein the MP1, the MP2 and the MP3 share a grid electrode; the source electrodes of the MP1, the MP2 and the MP3 are connected with a VDD; the drain electrodes of the MP2 and the MP3 are connected with the collector electrodes of the Q1 and the Q2 respectively; the base electrodes of the Q1 and the Q2 are connected with each other; the emitting electrodes of the Q1 and the Q2 are connected with the R1 and the R2 respectively; the M1 and the M2 share a grid electrode and share a drain electrode; the source electrode of the M1 is connected with the R1; the source electrode of the M2, the R1 and the R2 are grounded; the Q1 is matched with the Q2; the R1 and the R2 are resistors matched with each other according to a proportional relation; the width-to-length ratio of the M1 is proportional to that of the M2. The high-voltage high-current control circuit does not consider a channel length modulation effect of a transistor, introduces a negative feedback by the R1 and converts high current into a current comparison signal, thus achieving precise control over the current in a high-voltage high-current mode.

The invention belongs to the technical field of integrated circuits, and particularly relates to a CMOS input signal buffer applied to the front end of a high-speed ADC. The circuit structure comprises an input buffer with two differential source following structures, a common-mode feedback circuit module and a bias circuit module. According to the invention, stable common-mode output of a sourcefollower can be ensured; a channel length modulation effect under a deep submicron CMOS process is avoided; a N-type transistor adopts a deep N-well device to eliminate the substrate bias modulation effect. A cascode current source with large output impedance is used for providing bias current for an input transistor so as to relieve output signal nonlinearity caused by input signal changes. The buffer is used in an ADC circuit, can play a role in improving linearity and isolating an input signal from a post-stage circuit, has good linearity even when an input signal with higher frequency is input, and is particularly suitable for a front-end buffer circuit of a high-speed ADC.

The invention discloses a band-gap reference voltage source. The band-gap reference voltage source comprises a level switching circuit, a first field-effect tube, a second field-effect tube, a third field-effect tube, a first audion, a second audion, a third audion, a first resistor, a second resistor and a clamping circuit. The level switching circuit is used for generating identical first-order positive temperature coefficient voltage at the first end and the second end according to voltage input at the input end. According to the band-gap reference voltage source, the identical positive temperature coefficient voltage is introduced to a drain electrode of MP1 and a drain electrode of MP2, the channel length modulation effect of MP1 and MP2 is used for eliminating or reducing the second-order temperature coefficient, and therefore second-order temperature coefficient compensation is achieved.