8 results about "Channel length modulation" patented technology

The invention discloses a current mirror circuit for compensating a current source to be calibrated, which comprises a compensating current source, a current mirror and a voltage unit, and is characterized in that the compensating current source is used for providing compensating current to the input end of the current mirror; the current mirror is used for outputting corresponding mirror current at the output end of the current mirror according to the compensation current, and compensating the current source Iu to be corrected through the mirror current; the voltage unit is used for providing bias voltage for the current mirror and maintaining the voltages of the input end and the output end of the current mirror to be equal. According to the current source calibration circuit, the voltage of the input end and the voltage of the output end of the current mirror are kept equal through the voltage unit, so that the influence of the MOS channel length modulation effect can be avoided, accurate copying of the current is achieved, and the accuracy of the current source calibration process is improved.

This invention relates to the field of high-speed signal transmission technology, specifically to a differential multi-band voltage-domain cross-voltage-domain voltage-controlled oscillator (VCO) for suppressing power supply noise. It includes a frequency and phase detector, a charge pump, a low-pass filter, a VCO_BIAS module, and a voltage-controlled oscillator unit. The charge pump and low-pass filter generate a differential control voltage; the VCO_BIAS module receives the differential control voltage and converts it into a differential current; the voltage-controlled oscillator unit receives the differential current; the VCO_BIAS module integrates a bias structure to suppress power supply noise, reducing the sensitivity of the tail current transistor of the voltage-controlled oscillator unit to power supply noise due to channel length modulation effects, and improving the jitter of the phase-locked loop (PLL) output frequency. In this invention, by constructing a differential structure, a cross-voltage-domain design, and tunable bias and load, a wide frequency range output under low-voltage power supply is achieved, and clock jitter caused by power supply noise is effectively suppressed.

The invention discloses a low-temperature-coefficient band-gap reference source circuit and method achieved based on the same-direction curvature difference, and belongs to the technical field of integrated circuit band-gap reference. The circuit comprises two starting circuits, two first-order current type band-gap reference circuits which are the same in structure and respectively adopt longitudinal / transverse PNP transistors, and an improved subtraction circuit; the improved subtraction circuit is additionally provided with an operational amplifier and a compensation MOS tube to form negative feedback, errors caused by the channel length modulation effect are eliminated, the compensation method utilizes the same-direction curvature difference formed by two PNP transistors to conduct high-precision difference value synthesis on output currents of the two reference circuits, and temperature curvature compensation is achieved. The output temperature coefficient is less than 5ppm / DEG C, the output voltage is less than 1V, the low-voltage CMOS technology less than 90nm is adapted, all CMOS technologies are compatible, the production cost is low, the temperature stability and the compensation precision are high, and the low-voltage temperature compensation circuit is suitable for integrated circuit application scenes with strict temperature precision requirements.

The application discloses a current model and a parameter extraction method of a field effect transistor, and comprises the following steps: constructing a current model of the field effect transistor; and extracting parameters based on the current model of the field effect transistor. DS The application can represent linear or super-linear (non-linear) behaviors that may occur at low V DS The application can also represent channel length modulation effects that may occur at high V The application can also represent different gate-source voltage power law parameter behaviors of the current of the transistor in the above two cases.

The application provides a power semiconductor circuit and chip, the circuit comprises a chip, a channel is arranged in the chip, the circuit further comprises a flip voltage follower (FVF) used as a voltage buffer to ensure stable current output in the circuit, a compensation unit electrically connected to the two ends of the flip voltage follower (FVF) to ensure loop stability without output capacitor, and a non-inverting gain stage electrically connected to a power input end (VIN), a ground wire (GND) and the flip voltage follower (FVF) respectively to offset the channel length modulation effect during operation of the chip by increasing open-loop gain. The power semiconductor circuit and chip can effectively optimize the structure of the power semiconductor circuit, so that the circuit can meet the condition of no output capacitor and has the characteristics of high stability and high gain.

The application discloses a single-ended voltage to differential current circuit with adjustable gain, comprising a single-ended voltage to differential current module and an adjustable gain control module; wherein the single-ended voltage to differential current module adopts a symmetrical structure and converts a single-ended voltage into a differential current by using a cross-connected resistor; the adjustable gain control module provides a static complementary differential current by using a current adder and realizes proportional gain adjustment by means of a proportional current mirror structure; meanwhile, the source-drain voltage of a copy PMOS transistor is fixed by using the constant emitter-base voltage difference of a bipolar transistor, the channel length modulation effect is avoided, and the accuracy of the copy current is further enhanced. The application meets the requirements of low power consumption, high signal noise distortion ratio and high integration of an audio circuit and has a large adjustable gain range.

The invention discloses a high-precision current mirror circuit for industrial Internet of Things service, which comprises a reference branch, an operational amplifier, a bias branch and a current source branch, and is characterized in that the current source branch comprises a current source MOS (Metal Oxide Semiconductor) tube and a working circuit; the output end of the operational amplifier is simultaneously connected with the grid electrode of the reference current source MOS tube, the grid electrode of the bias MOS tube and the grid electrode of the current source MOS tube, the structure of the reference working circuit is the same as that of the working circuit, and the size of the reference working circuit is 1 / N of that of the working circuit. The reference working circuit in the reference branch circuit is used for scaling the working circuit in the current source branch circuit at equal proportion, and meanwhile, operational amplifier feedback is introduced, so that the drain terminal voltage of the bias MOS tube is equal to that of the current source MOS tube, the influence of the channel length modulation effect on the current mirror image precision is eliminated, the output current of the current mirror has no error, and the current mirror image precision is improved. And a high-precision bias current source can be provided for analog and radio frequency circuits.

This invention discloses a gallium oxide device with a gradient gate dielectric structure and its fabrication method, relating to semiconductor technology, and proposes a solution to address the performance limitations of short-channel devices. A gradient dielectric layer and a gradient gate layer are deposited on a gallium oxide epitaxial layer. The gradient dielectric layer is used to control the electric field distribution under the gate and the gate-channel coupling capability. The dielectric constant of the gradient dielectric layer changes in a piecewise gradient, increasing from the side near the source layer towards the drain layer. The gradient gate layer is used to control the potential distribution on the channel surface. The work function of the gradient gate layer changes in a piecewise gradient, decreasing from the side near the source layer towards the drain layer. Its advantages lie in achieving coordinated control of the channel potential distribution and the electric field distribution under the gate. It can weaken the modulation effect of the drain voltage on the channel barrier, reduce the channel length modulation effect and output conductance, and improve the current saturation characteristics of the device; it reduces the peak electric field at the gate-drain edge and weakens the electric field concentration phenomenon, making it particularly suitable for devices with short-channel dimensions.