21 results about "Channel length modulation" patented technology

A soft start circuit of a synchronous boost DC-DC converter is used for restraining current overshoot and voltage overshoot of the synchronous boost DC-DC converter in the starting process and comprises a first soft start module and a second soft start module. The first soft start module belongs to system open-loop work, and suppresses a channel length modulation effect through the same drain end voltage of a clamping matching tube and a power upper tube, so as to obtain a precisely controlled charging current. A second soft start module belongs to system closed-loop work, and the method comprises the following steps: in the first stage, VOUT partial voltage is synchronized; in the second stage, constant-current charging is carried out; and in the third stage, the error amplifier vref rises gently through preset voltage RC charging. According to the invention, current overshoot and voltage overshoot are effectively suppressed through two soft start stages, and the starting circuit has a wide application prospect in the field of starting circuits.

According to the current-limiting circuit and the linear voltage regulator for achieving constant power control, after the current of a power tube Ppower tube of a mirror image LDO circuit of a detection tube is compared with a set current-limiting threshold, an output signal pulls up the grid electrode of the Ppower tube to reduce output current, so that output current-limiting control is achieved, and when Vin rises, the output current-limiting control is achieved through the channel length modulation effect of the detection tube and the power tube. And the rated current limiting value is reduced, so that constant power control is realized when the input and output voltage difference of the LDO circuit is increased. Meanwhile, in order to avoid the influence of different Vout on the current limiting value, a Vout clamping circuit is adopted, the drain electrode potential of the Ppower and the drain electrode potential of the detection tube are approximately the same, and the current limiting difference caused by the change of the Vout is avoided. According to the circuit, current limiting and channel length effect differences are combined, as Vin rises, the current rising proportion of the detection tube is larger than that of the power tube, current limiting protection is started in advance, the output current is reduced, the constant power effect is achieved, power rising of the power tube along with Vin rising is avoided, and risks caused by heating when the power is large are reduced.

The invention relates to a band-gap reference voltage circuit based on channel length modulation effect compensation. The circuit comprises a Zener voltage stabilization source module which is used for carrying out preliminary step-down on external input voltage to generate primary reference voltage; the linear voltage stabilization source module is coupled to the Zener voltage stabilization source module and is used for generating a linear voltage stabilization source; the first-order band-gap reference circuit module is coupled to the linear voltage stabilization source module and is used for generating a first current subjected to first-order temperature compensation; the lambda modulation effect high-order compensation circuit module is respectively coupled to the Zener voltage stabilization source module and the linear voltage stabilization source module, and the lambda modulation effect high-order compensation circuit module generates a second current with a high-order nonlinear temperature coefficient through a channel length modulation effect; and the starting circuit module is used for providing starting voltage and driving current in the power-on process of the band-gap reference voltage circuit. According to the invention, the reference voltage with an ultralow temperature coefficient can be realized.

The invention discloses a current mirror circuit for compensating a current source to be calibrated, which comprises a compensating current source, a current mirror and a voltage unit, and is characterized in that the compensating current source is used for providing compensating current to the input end of the current mirror; the current mirror is used for outputting corresponding mirror current at the output end of the current mirror according to the compensation current, and compensating the current source Iu to be corrected through the mirror current; the voltage unit is used for providing bias voltage for the current mirror and maintaining the voltages of the input end and the output end of the current mirror to be equal. According to the current source calibration circuit, the voltage of the input end and the voltage of the output end of the current mirror are kept equal through the voltage unit, so that the influence of the MOS channel length modulation effect can be avoided, accurate copying of the current is achieved, and the accuracy of the current source calibration process is improved.

This invention belongs to the field of analog integrated circuit technology, specifically to a Class-AB output stage bias circuit with low mismatch and stable output current, suitable for fully differential circuits. This invention provides a bias circuit for the Class-AB output stage with extremely low current mirror mismatch, overcoming the mismatch caused by channel length modulation. Furthermore, when the output common mode changes, the bias circuit can adapt accordingly, providing a new bias, thereby minimizing the impact of common-mode voltage changes on the output stage's quiescent current.

This invention relates to the field of high-speed signal transmission technology, specifically to a differential multi-band voltage-domain cross-voltage-domain voltage-controlled oscillator (VCO) for suppressing power supply noise. It includes a frequency and phase detector, a charge pump, a low-pass filter, a VCO_BIAS module, and a voltage-controlled oscillator unit. The charge pump and low-pass filter generate a differential control voltage; the VCO_BIAS module receives the differential control voltage and converts it into a differential current; the voltage-controlled oscillator unit receives the differential current; the VCO_BIAS module integrates a bias structure to suppress power supply noise, reducing the sensitivity of the tail current transistor of the voltage-controlled oscillator unit to power supply noise due to channel length modulation effects, and improving the jitter of the phase-locked loop (PLL) output frequency. In this invention, by constructing a differential structure, a cross-voltage-domain design, and tunable bias and load, a wide frequency range output under low-voltage power supply is achieved, and clock jitter caused by power supply noise is effectively suppressed.

The present invention relates to a low-voltage operational amplifier for reducing system offset voltage, comprising a folded cascode input module (101), a CLASS_AB output stage control circuit (102), and an output stage module (103). The low-voltage operational amplifier solves the problems of large system offset voltage, inaccurate output stage quiescent current control, and wasted dynamic power consumption in existing low-voltage CLASS_AB operational amplifiers, improves the output stage quiescent current error caused by the channel length modulation effect, and simultaneously improves the current matching of the first stage cascode tube by adding a second stage cascode tube, effectively reducing the input offset voltage of the operational amplifier system. When a large external source / sink current exists, the CLASS_AB output stage control circuit (102) is current-limited to limit the internal maximum power consumption, thereby reducing both heat generation and useless power consumption, thereby broadening the application of the CLASS_AB output stage operational amplifier in low-voltage, high-precision circuit systems.

The invention discloses a low-temperature-coefficient band-gap reference source circuit and method achieved based on the same-direction curvature difference, and belongs to the technical field of integrated circuit band-gap reference. The circuit comprises two starting circuits, two first-order current type band-gap reference circuits which are the same in structure and respectively adopt longitudinal / transverse PNP transistors, and an improved subtraction circuit; the improved subtraction circuit is additionally provided with an operational amplifier and a compensation MOS tube to form negative feedback, errors caused by the channel length modulation effect are eliminated, the compensation method utilizes the same-direction curvature difference formed by two PNP transistors to conduct high-precision difference value synthesis on output currents of the two reference circuits, and temperature curvature compensation is achieved. The output temperature coefficient is less than 5ppm / DEG C, the output voltage is less than 1V, the low-voltage CMOS technology less than 90nm is adapted, all CMOS technologies are compatible, the production cost is low, the temperature stability and the compensation precision are high, and the low-voltage temperature compensation circuit is suitable for integrated circuit application scenes with strict temperature precision requirements.

The application discloses a current model and a parameter extraction method of a field effect transistor, and comprises the following steps: constructing a current model of the field effect transistor; and extracting parameters based on the current model of the field effect transistor. DS The application can represent linear or super-linear (non-linear) behaviors that may occur at low V DS The application can also represent channel length modulation effects that may occur at high V The application can also represent different gate-source voltage power law parameter behaviors of the current of the transistor in the above two cases.

The present invention discloses a dynamic comparator circuit with a wide input common-mode voltage range applied to a SAR ADC, including: a preamplifier, a latch, and a power supply terminal VDD; both ends of the power supply terminal VDD are respectively connected to PM1 and PM2, PM1 is connected to an input pair transistor NM1, the input pair transistor NM1 is connected to VINN, PM2 is connected to an input pair transistor NM2, the input pair transistor NM2 is connected to VINP, a connection line between PM1 and the input pair transistor NM1 is connected to a comparator LATCH, and the comparator LATCH is connected to VOUTN− and VOUTP+. The novel dynamic comparator circuit applied to the SAR ADC proposed by the present invention broadens the input common-mode voltage of the comparator, weakens the performance degradation caused by input common-mode offset in the actual application of the ADC, and also weakens the channel length modulation effect of MOS devices under PVT conditions, making the performance of the dynamic comparator more stable under PVT conditions, which has engineering significance.

The application provides a power semiconductor circuit and chip, the circuit comprises a chip, a channel is arranged in the chip, the circuit further comprises a flip voltage follower (FVF) used as a voltage buffer to ensure stable current output in the circuit, a compensation unit electrically connected to the two ends of the flip voltage follower (FVF) to ensure loop stability without output capacitor, and a non-inverting gain stage electrically connected to a power input end (VIN), a ground wire (GND) and the flip voltage follower (FVF) respectively to offset the channel length modulation effect during operation of the chip by increasing open-loop gain. The power semiconductor circuit and chip can effectively optimize the structure of the power semiconductor circuit, so that the circuit can meet the condition of no output capacitor and has the characteristics of high stability and high gain.

In a charge pump-based PLL circuit, charge pump output current variation may cause phase instability at an output of a VCO. The output current variation may be caused by low-frequency disturbances (e.g., tuning voltage (Vtune) drift with channel length modulation effect), disturbance in a gate bias voltage of a transistor, or a VDD transient. Such a low-frequency disturbance may occur during initial lock, which may affect phase settling time, or after lock, which may result in phase instability. A replica charge pump and a current filtering and compensation circuit may be implemented at the output of a main charge pump to provide error current compensation to suppress channel length modulation effect, improve phase stability, and reduce phase noise.

The application discloses a single-ended voltage to differential current circuit with adjustable gain, comprising a single-ended voltage to differential current module and an adjustable gain control module; wherein the single-ended voltage to differential current module adopts a symmetrical structure and converts a single-ended voltage into a differential current by using a cross-connected resistor; the adjustable gain control module provides a static complementary differential current by using a current adder and realizes proportional gain adjustment by means of a proportional current mirror structure; meanwhile, the source-drain voltage of a copy PMOS transistor is fixed by using the constant emitter-base voltage difference of a bipolar transistor, the channel length modulation effect is avoided, and the accuracy of the copy current is further enhanced. The application meets the requirements of low power consumption, high signal noise distortion ratio and high integration of an audio circuit and has a large adjustable gain range.

The invention discloses a high-precision current mirror circuit for industrial Internet of Things service, which comprises a reference branch, an operational amplifier, a bias branch and a current source branch, and is characterized in that the current source branch comprises a current source MOS (Metal Oxide Semiconductor) tube and a working circuit; the output end of the operational amplifier is simultaneously connected with the grid electrode of the reference current source MOS tube, the grid electrode of the bias MOS tube and the grid electrode of the current source MOS tube, the structure of the reference working circuit is the same as that of the working circuit, and the size of the reference working circuit is 1 / N of that of the working circuit. The reference working circuit in the reference branch circuit is used for scaling the working circuit in the current source branch circuit at equal proportion, and meanwhile, operational amplifier feedback is introduced, so that the drain terminal voltage of the bias MOS tube is equal to that of the current source MOS tube, the influence of the channel length modulation effect on the current mirror image precision is eliminated, the output current of the current mirror has no error, and the current mirror image precision is improved. And a high-precision bias current source can be provided for analog and radio frequency circuits.

The present application relates to the technical field of LDO circuit, especially to a dynamic pole compensation LDO circuit, which eliminates the channel length modulation effect by dynamically mirroring the current of PM0 through PM1 and combining the current mirror structure composed of PM2, PM3, NM0 and NM1, adopts the super source follower composed of NM5, NM6 and NM7 to push the secondary pole of the LDO to the outside of the bandwidth, greatly improves the phase margin, mirrors the dynamic load current to PM9 (diode connection) through NM9, combines the capacitor C1 to form a dynamic zero point, compensates the secondary pole in real time following the load change, avoids the problem that the primary and secondary poles are too close in the traditional Muller compensation, introduces NM2 to break the degenerate point of the current mirror, ensures the normal starting and stable work of the circuit, adjusts the gm value of the super source follower through the dynamic current mirroring of PM5 and PM7, automatically adjusts the secondary pole frequency with the change of the load current, realizes the adaptive optimization of the pole in the full load range, and improves the stability consistency under light load and heavy load.

The invention discloses a current model and parameter extraction method of a field effect transistor. The method comprises the following steps: constructing a current model of the field effect transistor; parameters are extracted based on a current model of the field effect transistor. According to the invention, the linear or super-linear (nonlinear) behavior of the output characteristic of the transistor at a low VDS can be represented, and the channel length modulation effect of the output characteristic of the transistor at a high VDS can also be represented; and different grid-source voltage power law parameter characteristic behaviors possibly occurring in the two conditions of the current of the transistor can be represented.

A current limiting circuit and a linear voltage regulator for realizing constant power control. The current of the power tube Ppower tube of the LDO circuit is compared with the set current limiting threshold by the detection tube mirror. The output signal pulls up the gate of the Ppower tube to reduce the output current, thereby realizing output current limiting control. The channel length modulation effect of the detection tube and the power tube is utilized. When Vin rises, the rated current limiting value is reduced, thereby realizing constant power control when the input-output voltage difference of the LDO circuit rises. At the same time, in order to avoid the influence of different Vout on the current limiting value, a Vout clamping circuit is adopted to make the drain potential of Ppower and the detection tube approximately the same, thereby avoiding the current limiting difference caused by the change of Vout. The circuit of the present invention combines the difference in current limiting and channel length effects. As Vin rises, the current increase ratio of the detection tube is greater than that of the power tube, and the current limiting protection is entered in advance, thereby reducing the output current and realizing the constant power effect. The power of the power tube is prevented from rising with the increase of Vin, thereby reducing the risk of heating when the power is high.

The invention relates to the technical field of LDO (Low Dropout Regulator) circuits, in particular to a dynamic pole compensation LDO (Low Dropout Regulator) circuit, which is characterized in that the current of PM0 is dynamically mirrored through PM1, a channel length modulation effect is eliminated by combining a current mirror structure formed by PM2, PM3, NM0 and NM1, a super source follower formed by NM5, NM6 and NM7 is adopted, secondary poles of the LDO are pushed out of a bandwidth, the phase margin is greatly improved, and the performance of the LDO circuit is improved. Dynamic load current is mirrored to PM9 (diode connection) through NM9, a dynamic zero point is formed in combination with a capacitor C1, a secondary pole is compensated along with load change in real time, the problem that a primary pole and a secondary pole are too close in traditional Miller compensation is avoided, NM2 is introduced to break a degeneracy point of a current mirror, normal starting and stable working of a circuit are ensured, and the circuit is stable in performance. The gm value of the super source follower is adjusted through the dynamic current mirror images of PM5 and PM7, so that the secondary pole frequency is automatically adjusted along with the change of the load current, the adaptive optimization of the pole in the full-load range is realized, and the stability consistency under the light load and the heavy load is improved.

This invention discloses a gallium oxide device with a gradient gate dielectric structure and its fabrication method, relating to semiconductor technology, and proposes a solution to address the performance limitations of short-channel devices. A gradient dielectric layer and a gradient gate layer are deposited on a gallium oxide epitaxial layer. The gradient dielectric layer is used to control the electric field distribution under the gate and the gate-channel coupling capability. The dielectric constant of the gradient dielectric layer changes in a piecewise gradient, increasing from the side near the source layer towards the drain layer. The gradient gate layer is used to control the potential distribution on the channel surface. The work function of the gradient gate layer changes in a piecewise gradient, decreasing from the side near the source layer towards the drain layer. Its advantages lie in achieving coordinated control of the channel potential distribution and the electric field distribution under the gate. It can weaken the modulation effect of the drain voltage on the channel barrier, reduce the channel length modulation effect and output conductance, and improve the current saturation characteristics of the device; it reduces the peak electric field at the gate-drain edge and weakens the electric field concentration phenomenon, making it particularly suitable for devices with short-channel dimensions.

A broadband high-linearity input signal buffer based on a bootstrap capacitor provided by the present invention is composed of a sampling capacitor C3 technology, an input transistor M2 based on a bootstrap capacitor C1 and an AC floating resistor R technology, and a common-source common-gate structure with a low output impedance. The capacitor C3 using the sampling capacitor technology can compensate for the slew rate of the input signal buffer during high-frequency large-amplitude positive input, achieving the purpose of improving linearity; at the same time, the common-source common-gate structure with a low output impedance can reduce the output impedance of the input buffer, and the technology based on the bootstrap capacitor and the AC floating resistor ensures that the drain-source voltage of the input transistor is constant, eliminating the channel length modulation effect, thereby improving the overall performance of the analog-to-digital converter ADC.

The invention discloses a buffer, a circuit board and electronic equipment, and relates to the technical field of electronic circuits. In the buffer, a drain bias circuit is used for outputting first bias voltage to a drain of an input field effect transistor, so that drain voltage of the input field effect transistor follows output voltage, drain-source voltage of the input field effect transistor follows the output voltage, and the channel length modulation effect can be reduced. And the body bias circuit is used for outputting a second bias voltage to the substrate of the input field effect transistor, so that the substrate voltage of the input field effect transistor follows the output voltage, the voltage between the substrate of the input field effect transistor and the source electrode follows the output voltage, and the back gate effect can be reduced. The first current source can provide current for the input field effect transistor, and enables the input field effect transistor to operate in a saturation region. Therefore, the buffer provided by the embodiment of the invention can eliminate the channel length modulation effect and the back gate effect, thereby ensuring the linearity between the input voltage and the output voltage of the buffer.