192results about "Pulse modulation" patented technology

Systems and methods for performance improvements in digital switching amplifiers using low-pass filtering to reduce noise and distortion. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low-pass filter configured to filter audio signals output by the plant. The filtered output of the plant is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.

An RFID reader accessible thorough a personal computer and includes a PC card interface and a controller both operating according to clock signals from a crystal oscillator. The RFID reader further includes a linearized power amplifier modulator in a transmit path, a receive chain capable of demodulating either class_1 or class_0 signals from RFID tags, and an integrated switching device for selecting one of a plurality of antenna for transmitting or receiving RF signals.

A compact transformer coupled modulator is described. The modulator includes a transformer comprising a primary and a plurality of secondary windings, where each secondary winding has an output terminal. The modulator also includes a plurality of switches, where each switch is associated with a respective secondary winding and has input and output terminals and a control terminal. The control terminal of each switch is in electrical communication with a respective output terminal of the plurality of secondary windings. Each of the plurality of switches is substantially simultaneously switched by an input signal applied to the primary.

A coupling apparatus (1) having a mains connection (2) for connection to a low-voltage mains power supply system, and having an appliance connection (3) for connection of any appliance for transmitting and/or receiving an RF signal has a voltage converter (5) and a high-pass filter (6.1, 6.2). The voltage converter converts the mains voltage which is present at the mains connection to a very-low voltage, which is suitable for supplying the appliance connected to the appliance connection. Inductances (4.3 to 4.6) of suitable size are interposed in the appropriate connecting lines as low-pass filters for decoupling the RF signal path from the supply signal path, and for suppressing undesirable, radio-frequency signal components in the supply voltages. RF signals which are transmitted or are to be transmitted via the low-voltage mains power supply system are coupled from the mains connection via the high-pass filter to the appliance connection, and from the appliance connection to the mains connection. In order to supply further appliances with mains voltage, the coupling apparatus has an additional appliance connection (7), which is likewise low-pass-filtered by means of inductances (4.3, 4.4).

Signal-integrity measurement systems and methods utilizing unique time-base generation techniques for controlling the sampling of one or more signals under test. A time-base generator made in accordance with the present disclosure includes a phase filter and modulation circuitry that generates a rapidly varying phase signal as a function of the output of a sigma-delta modulator. The phase filter filters unwanted high-frequency phase components from the rapidly varying phase signal. The filtered signal is used to clock one or more samplers so as to create sampling instances of the signal(s) under test. The sampling instances are then analyze using any one or more of a variety of techniques suited to the type of signal(s) under test.

A method of limiting at least one peak of a composite signal having multiple carriers signals involves placing energy in at least one bandwidth gap located between respective frequency bandwidths of carrier signals.

The present invention relates to a method for reducing cycle slips in a carrier recovery loop for a phase detector, the method comprising the steps of receiving an input signal consisting of samples, each received sample having an in-phase (I) and quadrature-phase (Q) component, providing the input signal to a phase error estimator adapted to determine a phase error estimate, providing the phase error estimate to a loop filter, and forming an output signal from the carrier recovery loop by subtracting an output from the loop filter from the input signal, wherein the phase error estimate is determined based on a combination of the amplitude and phase of the samples and a probability measure for a specifically transmitted symbol, thereby improving phase tracking performance of the carrier recovery loop.

Advantages with the present invention includes reduction of cycle slips without using a high performance, and expensive, hardware solution, at the same time as it is possible to suppress the effects of decision errors which enables higher gain, thereby giving an improvement in Bit Error Rate (BER) in low SNR conditions.

The present invention also relates to a corresponding phase detector

An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a multiplexing mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. In a multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain. An output circuit passes outputs from the programmable logic units in parallel in the multi-bit operand mode. The programmable logic units have look-up tables which share the same configuration bits. The programmable logic units can also have multiplexers for passing one of the received input signals when configured to operate in a multiplexing mode of operation.

A quadrature modulator divides a first signal input as a local signal into an I channel signal and a Q channel signal orthogonal to each other and outputs a second signal having a desired phase delay corresponding to direct current voltages as for the first signal by giving the direct current voltages Vi and Vq to the I channel signal and the Q channel signal, respectively. A phase comparison unit detects a phase difference θ between the first signal and the second signal. A setting unit sets the desired phase delay. A controller section controls the direct current voltages supplied to the I channel signal and the Q channel signal respectively in the quadrature modulator so that an output value corresponding to the phase difference θ detected by the phase comparison unit is equal to a value corresponding to the desired phase delay set by the setting unit, and controls the direct current voltages to be the direct current voltages Vi and Vq satisfying the relation of Vi=cos θ and Vq=sin θ.

Methods and apparatuses are described for performing adaptive analog-to-digital conversion and time-to-delay conversion by using signal prediction to adjust reference voltages of adjustable comparators.

A method for generating an UWB pulses based on LC oscillator topology. Fast turn on of the oscillator is achieved by creating large asymmetry in a normally symmetrical topology which is used in a typical differential type oscillator. One method for achieving large asymmetry is activating one branch of a differential pair of branches for a short duration before activating both branches in a normal operation. The bandwidth of the pulse is controlled by modifying the duration of the oscillator activation. Fast turn on and turn off is essential for high bandwidth generation. The method is adaptable for generating binary phase shift keying (BPSK) modulation. Selecting the activated branch of a fully symmetrical topology controls the output phase and creates two possibilities which differ exactly by 180 degrees. In a preferred embodiment, all the pulse generator components are on-clip leading to a low cost solution. The circuit can generate high power pulses directly on a load. It is also an option to add an amplifier to drive the output and separate the load from the oscillator. This method generate high power, stable pulses under varying practical conditions like process changes, VDD changes and temperature changes.

An asynchronous delta-sigma modulator is proposed that comprises an input port, a filter, an envelope path, a phase path, an amplifier, and a feedback path that conveys the amplifier output signal to the filter. The envelope path extracts an envelope from the signal provided by the filter and issues an envelope signal. The phase path processes or processes a phase from the signal provided by the filter and issues a phase signal. The amplifier comprises input ports for the envelope signal and the phase signal. The amplifier issues an amplifier output signal based on said envelope signal and said phase signal. The feedback path conveys the amplifier output signal to the filter. The feedback signal contains both amplitude information and phase information. A corresponding method and computer-program products usable for production and operation of the delta-sigma modulator are also disclosed.

A method signals in an ultra-wide bandwidth network. A data symbol is generated. A set of reference pulses is transmitted for the data symbol. Each reference pulse is of a different type. One data pulse is also transmitted for each reference pulse. A type of each data pulse is identical to the type of the corresponding reference pulse.

Universal signal modulators structures are shown which are particularly useful for selectively generating polar-modulated digital sequences from input phase and amplitude symbols and for generating quadrature-modulated digital sequences from input first and second quadrature symbols. Significantly, the modulation structure (quadrature modulation or polar modulation) of these embodiments can selected by simply changing the state of a mode command.